2 * Platform driver for the Realtek RTL8366 ethernet switch
4 * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/gpio.h>
18 #include <linux/spinlock.h>
19 #include <linux/skbuff.h>
20 #include <linux/switch.h>
21 #include <linux/phy.h>
22 #include <linux/rtl8366_smi.h>
27 #include <linux/debugfs.h>
30 #define RTL8366_SMI_DRIVER_NAME "rtl8366-smi"
31 #define RTL8366_SMI_DRIVER_DESC "Realtek RTL8366 switch driver"
32 #define RTL8366_SMI_DRIVER_VER "0.1.1"
34 #define RTL8366S_PHY_NO_MAX 4
35 #define RTL8366S_PHY_PAGE_MAX 7
36 #define RTL8366S_PHY_ADDR_MAX 31
38 #define RTL8366_CHIP_GLOBAL_CTRL_REG 0x0000
39 #define RTL8366_CHIP_CTRL_VLAN (1 << 13)
41 #define RTL8366_RESET_CTRL_REG 0x0100
42 #define RTL8366_CHIP_CTRL_RESET_HW 1
43 #define RTL8366_CHIP_CTRL_RESET_SW (1 << 1)
45 #define RTL8366S_CHIP_VERSION_CTRL_REG 0x0104
46 #define RTL8366S_CHIP_VERSION_MASK 0xf
47 #define RTL8366S_CHIP_ID_REG 0x0105
48 #define RTL8366S_CHIP_ID_8366 0x8366
50 /* PHY registers control */
51 #define RTL8366S_PHY_ACCESS_CTRL_REG 0x8028
52 #define RTL8366S_PHY_ACCESS_DATA_REG 0x8029
54 #define RTL8366S_PHY_CTRL_READ 1
55 #define RTL8366S_PHY_CTRL_WRITE 0
57 #define RTL8366S_PHY_REG_MASK 0x1f
58 #define RTL8366S_PHY_PAGE_OFFSET 5
59 #define RTL8366S_PHY_PAGE_MASK (0x7 << 5)
60 #define RTL8366S_PHY_NO_OFFSET 9
61 #define RTL8366S_PHY_NO_MASK (0x1f << 9)
63 #define RTL8366_SMI_ACK_RETRY_COUNT 5
64 #define RTL8366_SMI_CLK_DELAY 10 /* nsec */
66 /* LED control registers */
67 #define RTL8366_LED_BLINKRATE_REG 0x0420
68 #define RTL8366_LED_BLINKRATE_BIT 0
69 #define RTL8366_LED_BLINKRATE_MASK 0x0007
71 #define RTL8366_LED_CTRL_REG 0x0421
72 #define RTL8366_LED_0_1_CTRL_REG 0x0422
73 #define RTL8366_LED_2_3_CTRL_REG 0x0423
75 #define RTL8366S_MIB_COUNT 33
76 #define RTL8366S_GLOBAL_MIB_COUNT 1
77 #define RTL8366S_MIB_COUNTER_PORT_OFFSET 0x0040
78 #define RTL8366S_MIB_COUNTER_BASE 0x1000
79 #define RTL8366S_MIB_CTRL_REG 0x11F0
80 #define RTL8366S_MIB_CTRL_USER_MASK 0x01FF
81 #define RTL8366S_MIB_CTRL_BUSY_MASK 0x0001
82 #define RTL8366S_MIB_CTRL_RESET_MASK 0x0002
84 #define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK 0x0004
85 #define RTL8366S_MIB_CTRL_PORT_RESET_BIT 0x0003
86 #define RTL8366S_MIB_CTRL_PORT_RESET_MASK 0x01FC
89 #define RTL8366S_PORT_VLAN_CTRL_BASE 0x0058
90 #define RTL8366S_VLAN_TABLE_READ_BASE 0x018B
91 #define RTL8366S_VLAN_TABLE_WRITE_BASE 0x0185
93 #define RTL8366S_VLAN_TB_CTRL_REG 0x010F
95 #define RTL8366S_TABLE_ACCESS_CTRL_REG 0x0180
96 #define RTL8366S_TABLE_VLAN_READ_CTRL 0x0E01
97 #define RTL8366S_TABLE_VLAN_WRITE_CTRL 0x0F01
99 #define RTL8366S_VLAN_MEMCONF_BASE 0x0016
102 #define RTL8366S_PORT_LINK_STATUS_BASE 0x0060
103 #define RTL8366S_PORT_STATUS_SPEED_MASK 0x0003
104 #define RTL8366S_PORT_STATUS_DUPLEX_MASK 0x0004
105 #define RTL8366S_PORT_STATUS_LINK_MASK 0x0010
106 #define RTL8366S_PORT_STATUS_TXPAUSE_MASK 0x0020
107 #define RTL8366S_PORT_STATUS_RXPAUSE_MASK 0x0040
108 #define RTL8366S_PORT_STATUS_AN_MASK 0x0080
111 #define RTL8366_PORT_NUM_CPU 5
112 #define RTL8366_NUM_PORTS 6
113 #define RTL8366_NUM_VLANS 16
114 #define RTL8366_NUM_LEDGROUPS 4
115 #define RTL8366_NUM_VIDS 4096
116 #define RTL8366S_PRIORITYMAX 7
117 #define RTL8366S_FIDMAX 7
120 #define RTL8366_PORT_1 (1 << 0) /* In userspace port 0 */
121 #define RTL8366_PORT_2 (1 << 1) /* In userspace port 1 */
122 #define RTL8366_PORT_3 (1 << 2) /* In userspace port 2 */
123 #define RTL8366_PORT_4 (1 << 3) /* In userspace port 3 */
125 #define RTL8366_PORT_UNKNOWN (1 << 4) /* No known connection */
126 #define RTL8366_PORT_CPU (1 << 5) /* CPU port */
128 #define RTL8366_PORT_ALL (RTL8366_PORT_1 | \
132 RTL8366_PORT_UNKNOWN | \
135 #define RTL8366_PORT_ALL_BUT_CPU (RTL8366_PORT_1 | \
139 RTL8366_PORT_UNKNOWN)
141 #define RTL8366_PORT_ALL_EXTERNAL (RTL8366_PORT_1 | \
146 #define RTL8366_PORT_ALL_INTERNAL (RTL8366_PORT_UNKNOWN | \
149 struct rtl8366s_vlanconfig {
160 struct rtl8366s_vlan4kentry {
170 static const char *MIBCOUNTERS[] = { "IfInOctets ",
172 "EtherStatsUnderSizePkts ",
174 "EtherStatsPkts64Octets ",
175 "EtherStatsPkts65to127Octets ",
176 "EtherStatsPkts128to255Octets ",
177 "EtherStatsPkts256to511Octets ",
178 "EtherStatsPkts512to1023Octets ",
179 "EtherStatsPkts1024to1518Octets ",
180 "EtherOversizeStats ",
181 "EtherStatsJabbers ",
183 "EtherStatsMulticastPkts ",
184 "EtherStatsBroadcastPkts ",
185 "EtherStatsDropEvents ",
186 "Dot3StatsFCSErrors ",
187 "Dot3StatsSymbolErrors ",
188 "Dot3InPauseFrames ",
189 "Dot3ControlInUnknownOpcodes ",
191 "Dot3StatsSingleCollisionFrames ",
192 "Dot3StatMultipleCollisionFrames ",
193 "Dot3sDeferredTransmissions ",
194 "Dot3StatsLateCollisions ",
195 "EtherStatsCollisions ",
196 "Dot3StatsExcessiveCollisions ",
197 "Dot3OutPauseFrames ",
198 "Dot1dBasePortDelayExceededDiscards",
199 "Dot1dTpPortInDiscards ",
201 "IfOutMulticastPkts ",
202 "IfOutBroadcastPkts ",
206 struct platform_device *pdev;
207 struct rtl8366_smi_platform_data *pdata;
209 struct mii_bus *mii_bus;
210 struct switch_dev dev;
211 int mii_irq[PHY_MAX_ADDR];
213 struct dentry *debugfs_root;
221 #define to_rtl8366(_dev) container_of(_dev, struct rtl8366_smi, dev)
223 static inline void rtl8366_smi_clk_delay(struct rtl8366_smi *smi)
225 ndelay(RTL8366_SMI_CLK_DELAY);
228 static void rtl8366_smi_start(struct rtl8366_smi *smi)
230 unsigned int sda = smi->pdata->gpio_sda;
231 unsigned int sck = smi->pdata->gpio_sck;
234 * Set GPIO pins to output mode, with initial state:
237 gpio_direction_output(sck, 0);
238 gpio_direction_output(sda, 1);
239 rtl8366_smi_clk_delay(smi);
241 /* CLK 1: 0 -> 1, 1 -> 0 */
242 gpio_set_value(sck, 1);
243 rtl8366_smi_clk_delay(smi);
244 gpio_set_value(sck, 0);
245 rtl8366_smi_clk_delay(smi);
248 gpio_set_value(sck, 1);
249 rtl8366_smi_clk_delay(smi);
250 gpio_set_value(sda, 0);
251 rtl8366_smi_clk_delay(smi);
252 gpio_set_value(sck, 0);
253 rtl8366_smi_clk_delay(smi);
254 gpio_set_value(sda, 1);
257 static void rtl8366_smi_stop(struct rtl8366_smi *smi)
259 unsigned int sda = smi->pdata->gpio_sda;
260 unsigned int sck = smi->pdata->gpio_sck;
262 rtl8366_smi_clk_delay(smi);
263 gpio_set_value(sda, 0);
264 gpio_set_value(sck, 1);
265 rtl8366_smi_clk_delay(smi);
266 gpio_set_value(sda, 1);
267 rtl8366_smi_clk_delay(smi);
268 gpio_set_value(sck, 1);
269 rtl8366_smi_clk_delay(smi);
270 gpio_set_value(sck, 0);
271 rtl8366_smi_clk_delay(smi);
272 gpio_set_value(sck, 1);
275 rtl8366_smi_clk_delay(smi);
276 gpio_set_value(sck, 0);
277 rtl8366_smi_clk_delay(smi);
278 gpio_set_value(sck, 1);
280 /* set GPIO pins to input mode */
281 gpio_direction_input(sda);
282 gpio_direction_input(sck);
285 static void rtl8366_smi_write_bits(struct rtl8366_smi *smi, u32 data, u32 len)
287 unsigned int sda = smi->pdata->gpio_sda;
288 unsigned int sck = smi->pdata->gpio_sck;
290 for (; len > 0; len--) {
291 rtl8366_smi_clk_delay(smi);
294 if ( data & ( 1 << (len - 1)) )
295 gpio_set_value(sda, 1);
297 gpio_set_value(sda, 0);
298 rtl8366_smi_clk_delay(smi);
301 gpio_set_value(sck, 1);
302 rtl8366_smi_clk_delay(smi);
303 gpio_set_value(sck, 0);
307 static void rtl8366_smi_read_bits(struct rtl8366_smi *smi, u32 len, u32 *data)
309 unsigned int sda = smi->pdata->gpio_sda;
310 unsigned int sck = smi->pdata->gpio_sck;
312 gpio_direction_input(sda);
314 for (*data = 0; len > 0; len--) {
317 rtl8366_smi_clk_delay(smi);
320 gpio_set_value(sck, 1);
321 rtl8366_smi_clk_delay(smi);
322 u = gpio_get_value(sda);
323 gpio_set_value(sck, 0);
325 *data |= (u << (len - 1));
328 gpio_direction_output(sda, 0);
331 static int rtl8366_smi_wait_for_ack(struct rtl8366_smi *smi)
339 rtl8366_smi_read_bits(smi, 1, &ack);
343 if (++retry_cnt > RTL8366_SMI_ACK_RETRY_COUNT)
350 static int rtl8366_smi_write_byte(struct rtl8366_smi *smi, u8 data)
352 rtl8366_smi_write_bits(smi, data, 8);
353 return rtl8366_smi_wait_for_ack(smi);
356 static int rtl8366_smi_read_byte0(struct rtl8366_smi *smi, u8 *data)
361 rtl8366_smi_read_bits(smi, 8, &t);
365 rtl8366_smi_write_bits(smi, 0x00, 1);
370 static int rtl8366_smi_read_byte1(struct rtl8366_smi *smi, u8 *data)
375 rtl8366_smi_read_bits(smi, 8, &t);
379 rtl8366_smi_write_bits(smi, 0x01, 1);
384 static int rtl8366_smi_read_reg(struct rtl8366_smi *smi, u32 addr, u32 *data)
391 spin_lock_irqsave(&smi->lock, flags);
393 rtl8366_smi_start(smi);
395 /* send READ command */
396 ret = rtl8366_smi_write_byte(smi, 0x0a << 4 | 0x04 << 1 | 0x01);
401 ret = rtl8366_smi_write_byte(smi, addr & 0xff);
406 ret = rtl8366_smi_write_byte(smi, addr >> 8);
411 rtl8366_smi_read_byte0(smi, &lo);
412 /* read DATA[15:8] */
413 rtl8366_smi_read_byte1(smi, &hi);
415 *data = ((u32) lo) | (((u32) hi) << 8);
420 rtl8366_smi_stop(smi);
421 spin_unlock_irqrestore(&smi->lock, flags);
426 static int rtl8366_smi_write_reg(struct rtl8366_smi *smi, u32 addr, u32 data)
431 spin_lock_irqsave(&smi->lock, flags);
433 rtl8366_smi_start(smi);
435 /* send WRITE command */
436 ret = rtl8366_smi_write_byte(smi, 0x0a << 4 | 0x04 << 1 | 0x00);
441 ret = rtl8366_smi_write_byte(smi, addr & 0xff);
446 ret = rtl8366_smi_write_byte(smi, addr >> 8);
450 /* write DATA[7:0] */
451 ret = rtl8366_smi_write_byte(smi, data & 0xff);
455 /* write DATA[15:8] */
456 ret = rtl8366_smi_write_byte(smi, data >> 8);
463 rtl8366_smi_stop(smi);
464 spin_unlock_irqrestore(&smi->lock, flags);
469 static int rtl8366_smi_read_phy_reg(struct rtl8366_smi *smi,
470 u32 phy_no, u32 page, u32 addr, u32 *data)
475 if (phy_no > RTL8366S_PHY_NO_MAX)
478 if (page > RTL8366S_PHY_PAGE_MAX)
481 if (addr > RTL8366S_PHY_ADDR_MAX)
484 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
485 RTL8366S_PHY_CTRL_READ);
489 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
490 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
491 (addr & RTL8366S_PHY_REG_MASK);
493 ret = rtl8366_smi_write_reg(smi, reg, 0);
497 ret = rtl8366_smi_read_reg(smi, RTL8366S_PHY_ACCESS_DATA_REG, data);
504 static int rtl8366_smi_write_phy_reg(struct rtl8366_smi *smi,
505 u32 phy_no, u32 page, u32 addr, u32 data)
510 if (phy_no > RTL8366S_PHY_NO_MAX)
513 if (page > RTL8366S_PHY_PAGE_MAX)
516 if (addr > RTL8366S_PHY_ADDR_MAX)
519 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
520 RTL8366S_PHY_CTRL_WRITE);
524 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
525 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
526 (addr & RTL8366S_PHY_REG_MASK);
528 ret = rtl8366_smi_write_reg(smi, reg, data);
535 static int rtl8366_get_mib_counter(struct rtl8366_smi *smi, int counter,
536 int port, unsigned long long *val)
540 u32 addr, data, regoffset;
543 /* address offset to MIBs counter */
544 const u16 mibLength[RTL8366S_MIB_COUNT] = {4, 4, 2, 2, 2, 2, 2, 2, 2,
545 2, 2, 2, 2, 2, 2, 2, 2, 2,
546 2, 2, 4, 2, 2, 2, 2, 2, 2,
549 if (port > RTL8366_NUM_PORTS || counter >= RTL8366S_MIB_COUNT)
553 regoffset = RTL8366S_MIB_COUNTER_PORT_OFFSET * (port);
555 while (i < counter) {
556 regoffset += mibLength[i];
560 addr = RTL8366S_MIB_COUNTER_BASE + regoffset;
563 /* writing access counter address first */
564 /* then ASIC will prepare 64bits counter wait for being retrived */
565 data = 0;/* writing data will be discard by ASIC */
566 err = rtl8366_smi_write_reg(smi, addr, data);
570 /* read MIB control register */
571 err = rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
575 if (data & RTL8366S_MIB_CTRL_BUSY_MASK)
578 if (data & RTL8366S_MIB_CTRL_RESET_MASK)
582 addr = addr + mibLength[counter] - 1;
583 i = mibLength[counter];
586 err = rtl8366_smi_read_reg(smi, addr, &data);
590 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
600 static int rtl8366s_get_vlan_4k_entry(struct rtl8366_smi *smi, u32 vid,
601 struct rtl8366s_vlan4kentry *vlan4k)
607 memset(vlan4k, '\0', sizeof(struct rtl8366s_vlan4kentry));
610 if (vid >= RTL8366_NUM_VIDS)
613 tableaddr = (u16 *)vlan4k;
617 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
621 /* write table access control word */
622 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
623 RTL8366S_TABLE_VLAN_READ_CTRL);
627 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE, &data);
634 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE + 1,
645 static int rtl8366s_set_vlan_4k_entry(struct rtl8366_smi *smi,
646 const struct rtl8366s_vlan4kentry *vlan4k)
652 if (vlan4k->vid >= RTL8366_NUM_VIDS ||
653 vlan4k->member > RTL8366_PORT_ALL ||
654 vlan4k->untag > RTL8366_PORT_ALL ||
655 vlan4k->fid > RTL8366S_FIDMAX)
658 tableaddr = (u16 *)vlan4k;
662 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
670 rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE + 1, data);
673 /* write table access control word */
674 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
675 RTL8366S_TABLE_VLAN_WRITE_CTRL);
682 static int rtl8366s_get_vlan_member_config(struct rtl8366_smi *smi, u32 index,
683 struct rtl8366s_vlanconfig *vlanmc)
690 memset(vlanmc, '\0', sizeof(struct rtl8366s_vlanconfig));
692 if (index >= RTL8366_NUM_VLANS)
695 tableaddr = (u16 *)vlanmc;
697 addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
699 err = rtl8366_smi_read_reg(smi, addr, &data);
706 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
708 err = rtl8366_smi_read_reg(smi, addr, &data);
717 static int rtl8366s_set_vlan_member_config(struct rtl8366_smi *smi, u32 index,
718 const struct rtl8366s_vlanconfig
726 if (index >= RTL8366_NUM_VLANS ||
727 vlanmc->vid >= RTL8366_NUM_VIDS ||
728 vlanmc->priority > RTL8366S_PRIORITYMAX ||
729 vlanmc->member > RTL8366_PORT_ALL ||
730 vlanmc->untag > RTL8366_PORT_ALL ||
731 vlanmc->fid > RTL8366S_FIDMAX)
734 addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
737 tableaddr = (u16 *)vlanmc;
740 err = rtl8366_smi_write_reg(smi, addr, data);
744 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
749 err = rtl8366_smi_write_reg(smi, addr, data);
756 static int rtl8366_get_port_vlan_index(struct rtl8366_smi *smi, int port,
763 /* bits mapping to port vlan control register of port n */
764 const u16 bits[RTL8366_NUM_PORTS] = { 0x000F, 0x00F0, 0x0F00,
765 0xF000, 0x000F, 0x00F0 };
766 /* bits offset to port vlan control register of port n */
767 const u16 bitoffset[RTL8366_NUM_PORTS] = { 0, 4, 8, 12, 0, 4 };
768 /* address offset to port vlan control register of port n */
769 const u16 addroffset[RTL8366_NUM_PORTS] = { 0, 0, 0, 0, 1, 1 };
771 if (port >= RTL8366_NUM_PORTS)
774 addr = RTL8366S_PORT_VLAN_CTRL_BASE + addroffset[port];
776 err = rtl8366_smi_read_reg(smi, addr, &data);
780 *val = (data & bits[port]) >> bitoffset[port];
786 static int rtl8366_get_vlan_port_pvid(struct rtl8366_smi *smi, int port,
791 struct rtl8366s_vlanconfig vlanmc;
793 err = rtl8366_get_port_vlan_index(smi, port, &index);
797 err = rtl8366s_get_vlan_member_config(smi, index, &vlanmc);
805 static int rtl8366_set_port_vlan_index(struct rtl8366_smi *smi, int port,
814 /* bits mapping to port vlan control register of port n */
815 const u16 bitmasks[6] = { 0x000F, 0x00F0, 0x0F00,
816 0xF000, 0x000F, 0x00F0 };
817 /* bits offset to port vlan control register of port n */
818 const u16 bitOff[6] = { 0, 4, 8, 12, 0, 4 };
819 /* address offset to port vlan control register of port n */
820 const u16 addrOff[6] = { 0, 0, 0, 0, 1, 1 };
822 if (port >= RTL8366_NUM_PORTS || index >= RTL8366_NUM_VLANS)
825 addr = RTL8366S_PORT_VLAN_CTRL_BASE + addrOff[port];
827 bits = bitmasks[port];
829 data = (index << bitOff[port]) & bits;
831 err = rtl8366_smi_read_reg(smi, addr, &vlan_data);
835 vlan_data &= ~(vlan_data & bits);
838 err = rtl8366_smi_write_reg(smi, addr, vlan_data);
845 static int rtl8366_set_vlan_port_pvid(struct rtl8366_smi *smi, int port,
849 struct rtl8366s_vlanconfig vlanmc;
850 struct rtl8366s_vlan4kentry vlan4k;
852 if (port >= RTL8366_NUM_PORTS || val >= RTL8366_NUM_VIDS)
857 /* Updating the 4K entry; lookup it and change the port member set */
858 rtl8366s_get_vlan_4k_entry(smi, val, &vlan4k);
859 vlan4k.member |= ((1 << port) | RTL8366_PORT_CPU);
860 vlan4k.untag = RTL8366_PORT_ALL_BUT_CPU;
861 rtl8366s_set_vlan_4k_entry(smi, &vlan4k);
863 /* For the 16 entries more work needs to be done. First see if such
864 VID is already there and change it */
865 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
866 rtl8366s_get_vlan_member_config(smi, i, &vlanmc);
868 /* Try to find an existing vid and update port member set */
869 if (val == vlanmc.vid) {
870 vlanmc.member |= ((1 << port) | RTL8366_PORT_CPU);
871 rtl8366s_set_vlan_member_config(smi, i, &vlanmc);
873 /* Now update PVID register settings */
874 rtl8366_set_port_vlan_index(smi, port, i);
880 /* PVID could not be found from vlan table. Replace unused (one that
881 has no member ports) with new one */
882 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
883 rtl8366s_get_vlan_member_config(smi, i, &vlanmc);
885 /* See if this vlan member configuration is unused. It is
886 unused if member set contains no ports or CPU port only */
887 if (!vlanmc.member || vlanmc.member == RTL8366_PORT_CPU) {
890 vlanmc.untag = RTL8366_PORT_ALL_BUT_CPU;
891 vlanmc.member = ((1 << port) | RTL8366_PORT_CPU);
894 rtl8366s_set_vlan_member_config(smi, i, &vlanmc);
896 /* Now update PVID register settings */
897 rtl8366_set_port_vlan_index(smi, port, i);
903 dev_err(&smi->pdev->dev, "All 16 vlan member configurations are in "
909 static int rtl8366_vlan_set_vlan(struct rtl8366_smi *smi, int enable)
912 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
914 data &= ~(data & RTL8366_CHIP_CTRL_VLAN);
916 data |= RTL8366_CHIP_CTRL_VLAN;
918 return rtl8366_smi_write_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, data);
921 static int rtl8366_vlan_set_4ktable(struct rtl8366_smi *smi, int enable)
924 rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, &data);
930 return rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, data);
933 static int rtl8366s_reset_vlan(struct rtl8366_smi *smi)
936 struct rtl8366s_vlan4kentry vlan4k;
937 struct rtl8366s_vlanconfig vlanmc;
939 /* clear 16 VLAN member configuration */
940 for (i = 0; i < RTL8366_NUM_VLANS; i++) {
946 if (rtl8366s_set_vlan_member_config(smi, i, &vlanmc) != 0)
950 /* Set a default VLAN with vid 1 to 4K table for all ports */
952 vlan4k.member = RTL8366_PORT_ALL;
953 vlan4k.untag = RTL8366_PORT_ALL;
955 if (rtl8366s_set_vlan_4k_entry(smi, &vlan4k) != 0)
958 /* Set all ports PVID to default VLAN */
959 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
960 if (rtl8366_set_vlan_port_pvid(smi, i, 0) != 0)
968 static int rtl8366_debugfs_open(struct inode *inode, struct file *file)
970 file->private_data = inode->i_private;
974 static ssize_t rtl8366_read_debugfs_mibs(struct file *file,
975 char __user *user_buf,
976 size_t count, loff_t *ppos)
980 struct rtl8366_smi *smi = (struct rtl8366_smi *)file->private_data;
982 len += snprintf(buf + len, sizeof(buf) - len, "MIB Counters:\n");
983 len += snprintf(buf + len, sizeof(buf) - len, "Counter"
985 "Port 0 \t\t Port 1 \t\t Port 2 \t\t Port 3 \t\t "
988 for (i = 0; i < 33; ++i) {
990 len += snprintf(buf + len, sizeof(buf) - len, "%d:%s ",
992 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
993 unsigned long long counter = 0;
995 if (!rtl8366_get_mib_counter(smi, i, j, &counter))
996 len += snprintf(buf + len, sizeof(buf) - len,
999 len += snprintf(buf + len, sizeof(buf) - len,
1002 if (j != RTL8366_NUM_PORTS - 1) {
1003 if (counter < 100000)
1004 len += snprintf(buf + len,
1008 len += snprintf(buf + len, sizeof(buf) - len,
1012 len += snprintf(buf + len, sizeof(buf) - len, "\n");
1015 len += snprintf(buf + len, sizeof(buf) - len, "\n");
1017 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1020 static ssize_t rtl8366_read_debugfs_vlan(struct file *file,
1021 char __user *user_buf,
1022 size_t count, loff_t *ppos)
1026 struct rtl8366_smi *smi = (struct rtl8366_smi *)file->private_data;
1028 len += snprintf(buf + len, sizeof(buf) - len, "VLAN Member Config:\n");
1029 len += snprintf(buf + len, sizeof(buf) - len,
1030 "\t id \t vid \t prio \t member \t untag \t fid "
1033 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
1034 struct rtl8366s_vlanconfig vlanmc;
1036 rtl8366s_get_vlan_member_config(smi, i, &vlanmc);
1038 len += snprintf(buf + len, sizeof(buf) - len,
1039 "\t[%d] \t %d \t %d \t 0x%04x \t 0x%04x \t %d "
1040 "\t", i, vlanmc.vid, vlanmc.priority,
1041 vlanmc.member, vlanmc.untag, vlanmc.fid);
1043 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
1045 if (!rtl8366_get_port_vlan_index(smi, j, &index)) {
1047 len += snprintf(buf + len,
1052 len += snprintf(buf + len, sizeof(buf) - len, "\n");
1055 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1058 static ssize_t rtl8366_read_debugfs_reg(struct file *file,
1059 char __user *user_buf,
1060 size_t count, loff_t *ppos)
1062 u32 t, reg = g_dbg_reg;
1065 struct rtl8366_smi *smi = (struct rtl8366_smi *)file->private_data;
1067 memset(buf, '\0', sizeof(buf));
1069 err = rtl8366_smi_read_reg(smi, reg, &t);
1071 len += snprintf(buf, sizeof(buf),
1072 "Read failed (reg: 0x%04x)\n", reg);
1073 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1076 len += snprintf(buf, sizeof(buf), "reg = 0x%04x, val = 0x%04x\n",
1079 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1082 static ssize_t rtl8366_write_debugfs_reg(struct file *file,
1083 const char __user *user_buf,
1084 size_t count, loff_t *ppos)
1087 u32 reg = g_dbg_reg;
1091 struct rtl8366_smi *smi = (struct rtl8366_smi *)file->private_data;
1093 len = min(count, sizeof(buf) - 1);
1094 if (copy_from_user(buf, user_buf, len)) {
1095 dev_err(&smi->pdev->dev, "copy from user failed\n");
1100 if (len > 0 && buf[len - 1] == '\n')
1101 buf[len - 1] = '\0';
1104 if (strict_strtoul(buf, 16, &data)) {
1105 dev_err(&smi->pdev->dev, "Invalid reg value %s\n", buf);
1107 err = rtl8366_smi_write_reg(smi, reg, data);
1109 dev_err(&smi->pdev->dev,
1110 "writing reg 0x%04x val 0x%04lx failed\n",
1118 static const struct file_operations fops_rtl8366_regs = {
1119 .read = rtl8366_read_debugfs_reg,
1120 .write = rtl8366_write_debugfs_reg,
1121 .open = rtl8366_debugfs_open,
1122 .owner = THIS_MODULE
1125 static const struct file_operations fops_rtl8366_vlan = {
1126 .read = rtl8366_read_debugfs_vlan,
1127 .open = rtl8366_debugfs_open,
1128 .owner = THIS_MODULE
1131 static const struct file_operations fops_rtl8366_mibs = {
1132 .read = rtl8366_read_debugfs_mibs,
1133 .open = rtl8366_debugfs_open,
1134 .owner = THIS_MODULE
1137 static void rtl8366_debugfs_init(struct rtl8366_smi *smi)
1139 struct dentry *node;
1140 struct dentry *root;
1142 if (!smi->debugfs_root)
1143 smi->debugfs_root = debugfs_create_dir("rtl8366s", NULL);
1145 if (!smi->debugfs_root) {
1146 dev_err(&smi->pdev->dev, "Unable to create debugfs dir\n");
1149 root = smi->debugfs_root;
1151 node = debugfs_create_x16("reg", S_IRUGO | S_IWUSR, root, &g_dbg_reg);
1153 dev_err(&smi->pdev->dev, "Creating debugfs file reg failed\n");
1157 node = debugfs_create_file("val", S_IRUGO | S_IWUSR, root, smi,
1158 &fops_rtl8366_regs);
1160 dev_err(&smi->pdev->dev, "Creating debugfs file val failed\n");
1164 node = debugfs_create_file("vlan", S_IRUSR, root, smi,
1165 &fops_rtl8366_vlan);
1167 dev_err(&smi->pdev->dev, "Creating debugfs file vlan "
1172 node = debugfs_create_file("mibs", S_IRUSR, root, smi,
1173 &fops_rtl8366_mibs);
1175 dev_err(&smi->pdev->dev, "Creating debugfs file mibs "
1181 static void rtl8366_debugfs_remove(struct rtl8366_smi *smi)
1183 if (smi->debugfs_root) {
1184 debugfs_remove_recursive(smi->debugfs_root);
1185 smi->debugfs_root = NULL;
1190 static inline void rtl8366_debugfs_init(struct rtl8366_smi *smi) {}
1191 static inline void rtl8366_debugfs_remove(struct rtl8366_smi *smi) {}
1194 static int rtl8366_global_reset_mibs(struct switch_dev *dev,
1195 const struct switch_attr *attr,
1196 struct switch_val *val)
1199 struct rtl8366_smi *smi = to_rtl8366(dev);
1201 if (val->value.i == 1) {
1202 rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
1204 rtl8366_smi_write_reg(smi, RTL8366S_MIB_CTRL_REG, data);
1210 static int rtl8366_get_vlan(struct switch_dev *dev,
1211 const struct switch_attr *attr,
1212 struct switch_val *val)
1215 struct rtl8366_smi *smi = to_rtl8366(dev);
1217 if (attr->ofs == 1) {
1218 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
1220 if (data & RTL8366_CHIP_CTRL_VLAN)
1224 } else if (attr->ofs == 2) {
1225 rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, &data);
1236 static int rtl8366_global_get_blinkrate(struct switch_dev *dev,
1237 const struct switch_attr *attr,
1238 struct switch_val *val)
1241 struct rtl8366_smi *smi = to_rtl8366(dev);
1242 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1244 val->value.i = (data & (RTL8366_LED_BLINKRATE_MASK));
1249 static int rtl8366_global_set_blinkrate(struct switch_dev *dev,
1250 const struct switch_attr *attr,
1251 struct switch_val *val)
1254 struct rtl8366_smi *smi = to_rtl8366(dev);
1256 if (val->value.i >= 6)
1259 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1261 data &= ~(data & RTL8366_LED_BLINKRATE_MASK);
1262 data |= val->value.i;
1264 rtl8366_smi_write_reg(smi, RTL8366_LED_BLINKRATE_REG, data);
1269 static int rtl8366_set_vlan(struct switch_dev *dev,
1270 const struct switch_attr *attr,
1271 struct switch_val *val)
1273 struct rtl8366_smi *smi = to_rtl8366(dev);
1276 return rtl8366_vlan_set_vlan(smi, val->value.i);
1278 return rtl8366_vlan_set_4ktable(smi, val->value.i);
1281 static int rtl8366_init_vlan(struct switch_dev *dev,
1282 const struct switch_attr *attr,
1283 struct switch_val *val)
1285 struct rtl8366_smi *smi = to_rtl8366(dev);
1286 return rtl8366s_reset_vlan(smi);
1289 static int rtl8366_attr_get_port_link(struct switch_dev *dev,
1290 const struct switch_attr *attr,
1291 struct switch_val *val)
1294 u32 len = 0, data = 0;
1295 int speed, duplex, link, txpause, rxpause, nway;
1296 struct rtl8366_smi *smi = to_rtl8366(dev);
1298 if (val->port_vlan >= RTL8366_NUM_PORTS)
1301 memset(buf, '\0', sizeof(buf));
1302 rtl8366_smi_read_reg(smi, RTL8366S_PORT_LINK_STATUS_BASE +
1303 (val->port_vlan >> 1),
1306 if (val->port_vlan & 0x1)
1309 speed = (data & RTL8366S_PORT_STATUS_SPEED_MASK);
1310 duplex = (data & RTL8366S_PORT_STATUS_DUPLEX_MASK) >> 2;
1311 link = (data & RTL8366S_PORT_STATUS_LINK_MASK) >> 4;
1312 txpause = (data & RTL8366S_PORT_STATUS_TXPAUSE_MASK) >> 5;
1313 rxpause = (data & RTL8366S_PORT_STATUS_RXPAUSE_MASK) >> 6;
1314 nway = (data & RTL8366S_PORT_STATUS_AN_MASK) >> 7;
1316 len += snprintf(buf + len, sizeof(buf) - len, "Port %d: ",
1320 len += snprintf(buf + len, sizeof(buf) - len,
1321 "Link UP, Speed: ");
1323 len += snprintf(buf + len, sizeof(buf) - len,
1324 "Link DOWN, Speed: ");
1327 len += snprintf(buf + len, sizeof(buf) - len, "10Base-TX ");
1328 else if (speed == 1)
1329 len += snprintf(buf + len, sizeof(buf) - len, "100Base-TX ");
1330 else if (speed == 2)
1331 len += snprintf(buf + len, sizeof(buf) - len, "1000Base-TX ");
1334 len += snprintf(buf + len, sizeof(buf) - len, "Full-Duplex, ");
1336 len += snprintf(buf + len, sizeof(buf) - len, "Half-Duplex, ");
1339 len += snprintf(buf + len, sizeof(buf) - len, "TX-Pause ");
1341 len += snprintf(buf + len, sizeof(buf) - len, "RX-Pause ");
1343 len += snprintf(buf + len, sizeof(buf) - len, "nway ");
1351 static int rtl8366_attr_get_vlan_info(struct switch_dev *dev,
1352 const struct switch_attr *attr,
1353 struct switch_val *val)
1358 struct rtl8366s_vlanconfig vlanmc;
1359 struct rtl8366s_vlan4kentry vlan4k;
1360 struct rtl8366_smi *smi = to_rtl8366(dev);
1362 if (val->port_vlan >= RTL8366_NUM_PORTS)
1365 memset(buf, '\0', sizeof(buf));
1367 rtl8366s_get_vlan_member_config(smi, val->port_vlan, &vlanmc);
1368 rtl8366s_get_vlan_4k_entry(smi, vlanmc.vid, &vlan4k);
1370 len += snprintf(buf + len, sizeof(buf) - len, "VLAN %d: Ports: ",
1373 for (i = 0; i < RTL8366_NUM_PORTS; ++i) {
1375 if (!rtl8366_get_port_vlan_index(smi, i, &index) &&
1376 index == val->port_vlan)
1377 len += snprintf(buf + len, sizeof(buf) - len, "%d", i);
1379 len += snprintf(buf + len, sizeof(buf) - len, "\n");
1381 len += snprintf(buf + len, sizeof(buf) - len,
1382 "\t\t vid \t prio \t member \t untag \t fid\n");
1383 len += snprintf(buf + len, sizeof(buf) - len, "\tMC:\t");
1384 len += snprintf(buf + len, sizeof(buf) - len,
1385 "%d \t %d \t 0x%04x \t 0x%04x \t %d\n",
1386 vlanmc.vid, vlanmc.priority, vlanmc.member,
1387 vlanmc.untag, vlanmc.fid);
1388 len += snprintf(buf + len, sizeof(buf) - len, "\t4K:\t");
1389 len += snprintf(buf + len, sizeof(buf) - len,
1390 "%d \t \t 0x%04x \t 0x%04x \t %d",
1391 vlan4k.vid, vlan4k.member, vlan4k.untag, vlan4k.fid);
1399 static int rtl8366_set_port_led(struct switch_dev *dev,
1400 const struct switch_attr *attr,
1401 struct switch_val *val)
1404 struct rtl8366_smi *smi = to_rtl8366(dev);
1405 if (val->port_vlan >= RTL8366_NUM_PORTS ||
1406 (1 << val->port_vlan) == RTL8366_PORT_UNKNOWN)
1409 if (val->port_vlan == RTL8366_PORT_NUM_CPU) {
1410 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1411 data = (data & (~(0xF << 4))) | (val->value.i << 4);
1412 rtl8366_smi_write_reg(smi, RTL8366_LED_BLINKRATE_REG, data);
1414 rtl8366_smi_read_reg(smi, RTL8366_LED_CTRL_REG, &data);
1415 data = (data & (~(0xF << (val->port_vlan * 4)))) |
1416 (val->value.i << (val->port_vlan * 4));
1417 rtl8366_smi_write_reg(smi, RTL8366_LED_CTRL_REG, data);
1423 static int rtl8366_get_port_led(struct switch_dev *dev,
1424 const struct switch_attr *attr,
1425 struct switch_val *val)
1428 struct rtl8366_smi *smi = to_rtl8366(dev);
1429 if (val->port_vlan >= RTL8366_NUM_LEDGROUPS)
1432 rtl8366_smi_read_reg(smi, RTL8366_LED_CTRL_REG, &data);
1433 val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
1438 static int rtl8366_reset_port_mibs(struct switch_dev *dev,
1439 const struct switch_attr *attr,
1440 struct switch_val *val)
1443 struct rtl8366_smi *smi = to_rtl8366(dev);
1444 if (val->port_vlan >= RTL8366_NUM_PORTS)
1447 rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
1448 data |= (1 << (val->port_vlan + 3));
1449 rtl8366_smi_write_reg(smi, RTL8366S_MIB_CTRL_REG, data);
1454 static int rtl8366_get_port_mib(struct switch_dev *dev,
1455 const struct switch_attr *attr,
1456 struct switch_val *val)
1460 unsigned long long counter = 0;
1461 struct rtl8366_smi *smi = to_rtl8366(dev);
1462 if (val->port_vlan >= RTL8366_NUM_PORTS)
1465 len += snprintf(buf + len, sizeof(buf) - len, "Port %d MIB counters\n",
1467 for (i = 0; i < RTL8366S_MIB_COUNT; ++i) {
1469 len += snprintf(buf + len, sizeof(buf) - len,
1470 "%d:%s\t", i, MIBCOUNTERS[i]);
1471 if (!rtl8366_get_mib_counter(smi, i, val->port_vlan, &counter))
1472 len += snprintf(buf + len, sizeof(buf) - len,
1473 "[%llu]\n", counter);
1475 len += snprintf(buf + len, sizeof(buf) - len,
1484 static int rtl8366_set_member(struct switch_dev *dev,
1485 const struct switch_attr *attr,
1486 struct switch_val *val)
1488 struct rtl8366s_vlanconfig vlanmc;
1489 struct rtl8366s_vlan4kentry vlan4k;
1490 struct rtl8366_smi *smi = to_rtl8366(dev);
1492 if (val->port_vlan >= RTL8366_NUM_VLANS)
1495 rtl8366s_get_vlan_member_config(smi, val->port_vlan, &vlanmc);
1497 rtl8366s_get_vlan_4k_entry(smi, vlanmc.vid, &vlan4k);
1499 vlan4k.member = vlanmc.member = val->value.i;
1500 rtl8366s_set_vlan_member_config(smi, val->port_vlan, &vlanmc);
1501 rtl8366s_set_vlan_4k_entry(smi, &vlan4k);
1506 static int rtl8366_get_member(struct switch_dev *dev,
1507 const struct switch_attr *attr,
1508 struct switch_val *val)
1510 struct rtl8366s_vlanconfig vlanmc;
1511 struct rtl8366s_vlan4kentry vlan4k;
1512 struct rtl8366_smi *smi = to_rtl8366(dev);
1514 if (val->port_vlan >= RTL8366_NUM_VLANS)
1517 rtl8366s_get_vlan_member_config(smi, val->port_vlan, &vlanmc);
1519 rtl8366s_get_vlan_4k_entry(smi, vlanmc.vid, &vlan4k);
1521 val->value.i = vlanmc.member;
1526 static int rtl8366_set_untag(struct switch_dev *dev,
1527 const struct switch_attr *attr,
1528 struct switch_val *val)
1530 struct rtl8366s_vlanconfig vlanmc;
1531 struct rtl8366s_vlan4kentry vlan4k;
1532 struct rtl8366_smi *smi = to_rtl8366(dev);
1534 if (val->port_vlan >= RTL8366_NUM_VLANS)
1537 rtl8366s_get_vlan_member_config(smi, val->port_vlan, &vlanmc);
1538 rtl8366s_get_vlan_4k_entry(smi, vlanmc.vid, &vlan4k);
1540 vlan4k.untag = vlanmc.untag = val->value.i;
1541 rtl8366s_set_vlan_member_config(smi, val->port_vlan, &vlanmc);
1542 rtl8366s_set_vlan_4k_entry(smi, &vlan4k);
1547 static int rtl8366_get_untag(struct switch_dev *dev,
1548 const struct switch_attr *attr,
1549 struct switch_val *val)
1551 struct rtl8366s_vlanconfig vlanmc;
1552 struct rtl8366s_vlan4kentry vlan4k;
1553 struct rtl8366_smi *smi = to_rtl8366(dev);
1555 if (val->port_vlan >= RTL8366_NUM_VLANS)
1558 rtl8366s_get_vlan_member_config(smi, val->port_vlan, &vlanmc);
1559 rtl8366s_get_vlan_4k_entry(smi, vlanmc.vid, &vlan4k);
1562 val->value.i = vlanmc.untag;
1567 static int rtl8366_get_port_pvid(struct switch_dev *dev, int port, int *val)
1569 struct rtl8366_smi *smi = to_rtl8366(dev);
1570 return rtl8366_get_vlan_port_pvid(smi, port, val);
1573 static int rtl8366_set_port_pvid(struct switch_dev *dev, int port, int val)
1575 struct rtl8366_smi *smi = to_rtl8366(dev);
1576 return rtl8366_set_vlan_port_pvid(smi, port, val);
1579 static int rtl8366_reset_switch(struct switch_dev *dev)
1581 struct rtl8366_smi *smi = to_rtl8366(dev);
1582 rtl8366_smi_write_reg(smi, RTL8366_RESET_CTRL_REG,
1583 RTL8366_CHIP_CTRL_RESET_HW);
1587 static struct switch_attr rtl8366_globals[] = {
1589 .type = SWITCH_TYPE_INT,
1590 .name = "enable_vlan",
1591 .description = "Enable VLAN mode",
1592 .set = rtl8366_set_vlan,
1593 .get = rtl8366_get_vlan,
1598 .type = SWITCH_TYPE_INT,
1599 .name = "enable_vlan4k",
1600 .description = "Enable VLAN 4K mode",
1601 .set = rtl8366_set_vlan,
1602 .get = rtl8366_get_vlan,
1607 .type = SWITCH_TYPE_INT,
1608 .name = "init_vlan",
1609 .description = "Initialize VLAN tables to defaults",
1610 .set = rtl8366_init_vlan,
1616 .type = SWITCH_TYPE_INT,
1617 .name = "reset_mibs",
1618 .description = "Reset all MIB counters",
1619 .set = rtl8366_global_reset_mibs,
1624 .type = SWITCH_TYPE_INT,
1625 .name = "blinkrate",
1626 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1627 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1628 .set = rtl8366_global_set_blinkrate,
1629 .get = rtl8366_global_get_blinkrate,
1634 static struct switch_attr rtl8366_port[] = {
1636 .type = SWITCH_TYPE_STRING,
1638 .description = "Get port link information",
1641 .get = rtl8366_attr_get_port_link
1644 .type = SWITCH_TYPE_INT,
1645 .name = "reset_mib",
1646 .description = "Reset single port MIB counters",
1648 .set = rtl8366_reset_port_mibs,
1652 .type = SWITCH_TYPE_STRING,
1654 .description = "Get MIB counters for port",
1657 .get = rtl8366_get_port_mib
1660 .type = SWITCH_TYPE_INT,
1662 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1664 .set = rtl8366_set_port_led,
1665 .get = rtl8366_get_port_led
1669 static struct switch_attr rtl8366_vlan[] = {
1671 .type = SWITCH_TYPE_INT,
1673 .description = "Get/Set VLAN untag port set (bitmask)",
1674 .set = rtl8366_set_untag,
1675 .get = rtl8366_get_untag,
1679 .type = SWITCH_TYPE_INT,
1681 .description = "Get/Set VLAN member port set (bitmask)",
1682 .set = rtl8366_set_member,
1683 .get = rtl8366_get_member,
1687 .type = SWITCH_TYPE_STRING,
1689 .description = "Get vlan information",
1692 .get = rtl8366_attr_get_vlan_info
1698 static struct switch_dev rtldev = {
1700 .cpu_port = RTL8366_PORT_NUM_CPU,
1701 .ports = RTL8366_NUM_PORTS,
1702 .vlans = RTL8366_NUM_VLANS,
1704 .attr = rtl8366_globals,
1705 .n_attr = ARRAY_SIZE(rtl8366_globals),
1708 .attr = rtl8366_port,
1709 .n_attr = ARRAY_SIZE(rtl8366_port),
1712 .attr = rtl8366_vlan,
1713 .n_attr = ARRAY_SIZE(rtl8366_vlan),
1716 .get_port_pvid = rtl8366_get_port_pvid,
1717 .set_port_pvid = rtl8366_set_port_pvid,
1718 .reset_switch = rtl8366_reset_switch,
1721 static int rtl8366_smi_switch_init(struct rtl8366_smi *smi)
1723 struct switch_dev *dev = &smi->dev;
1726 memcpy(dev, &rtldev, sizeof(struct switch_dev));
1728 dev->devname = dev_name(&smi->pdev->dev);
1730 err = register_switch(dev, NULL);
1732 dev_err(&smi->pdev->dev, "switch registration failed\n");
1737 static void rtl8366_smi_switch_cleanup(struct rtl8366_smi *smi)
1739 unregister_switch(&smi->dev);
1742 static int rtl8366_smi_mii_read(struct mii_bus *bus, int addr, int reg)
1744 struct rtl8366_smi *smi = bus->priv;
1748 err = rtl8366_smi_read_phy_reg(smi, addr, 0, reg, &val);
1755 static int rtl8366_smi_mii_write(struct mii_bus *bus, int addr, int reg,
1758 struct rtl8366_smi *smi = bus->priv;
1762 err = rtl8366_smi_write_phy_reg(smi, addr, 0, reg, val);
1764 (void) rtl8366_smi_read_phy_reg(smi, addr, 0, reg, &t);
1769 static int rtl8366_smi_mii_init(struct rtl8366_smi *smi)
1774 smi->mii_bus = mdiobus_alloc();
1775 if (smi->mii_bus == NULL) {
1780 spin_lock_init(&smi->lock);
1781 smi->mii_bus->priv = (void *) smi;
1782 smi->mii_bus->name = "rtl8366-smi";
1783 smi->mii_bus->read = rtl8366_smi_mii_read;
1784 smi->mii_bus->write = rtl8366_smi_mii_write;
1785 snprintf(smi->mii_bus->id, MII_BUS_ID_SIZE, "%s",
1786 dev_name(&smi->pdev->dev));
1787 smi->mii_bus->parent = &smi->pdev->dev;
1788 smi->mii_bus->phy_mask = ~(0x1f);
1789 smi->mii_bus->irq = smi->mii_irq;
1790 for (i = 0; i < PHY_MAX_ADDR; i++)
1791 smi->mii_irq[i] = PHY_POLL;
1793 ret = mdiobus_register(smi->mii_bus);
1800 mdiobus_free(smi->mii_bus);
1805 static void rtl8366_smi_mii_cleanup(struct rtl8366_smi *smi)
1807 mdiobus_unregister(smi->mii_bus);
1808 mdiobus_free(smi->mii_bus);
1811 static int rtl8366_smi_mii_bus_match(struct mii_bus *bus)
1813 return (bus->read == rtl8366_smi_mii_read &&
1814 bus->write == rtl8366_smi_mii_write);
1817 static int rtl8366_smi_setup(struct rtl8366_smi *smi)
1823 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id);
1825 dev_err(&smi->pdev->dev, "unable to read chip id\n");
1830 case RTL8366S_CHIP_ID_8366:
1833 dev_err(&smi->pdev->dev, "unknown chip id (%04x)\n", chip_id);
1837 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_VERSION_CTRL_REG,
1840 dev_err(&smi->pdev->dev, "unable to read chip version\n");
1844 dev_info(&smi->pdev->dev, "RTL%04x ver. %u chip found\n",
1845 chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK);
1847 rtl8366_debugfs_init(smi);
1852 static int __init rtl8366_smi_probe(struct platform_device *pdev)
1854 static int rtl8366_smi_version_printed;
1855 struct rtl8366_smi_platform_data *pdata;
1856 struct rtl8366_smi *smi;
1859 if (!rtl8366_smi_version_printed++)
1860 printk(KERN_NOTICE RTL8366_SMI_DRIVER_DESC
1861 " version " RTL8366_SMI_DRIVER_VER"\n");
1863 pdata = pdev->dev.platform_data;
1865 dev_err(&pdev->dev, "no platform data specified\n");
1870 smi = kzalloc(sizeof(struct rtl8366_smi), GFP_KERNEL);
1872 dev_err(&pdev->dev, "no memory for private data\n");
1877 err = gpio_request(pdata->gpio_sda, dev_name(&pdev->dev));
1879 dev_err(&pdev->dev, "gpio_request failed for %u, err=%d\n",
1880 pdata->gpio_sda, err);
1884 err = gpio_request(pdata->gpio_sck, dev_name(&pdev->dev));
1886 dev_err(&pdev->dev, "gpio_request failed for %u, err=%d\n",
1887 pdata->gpio_sck, err);
1893 spin_lock_init(&smi->lock);
1895 platform_set_drvdata(pdev, smi);
1897 dev_info(&pdev->dev, "using GPIO pins %u (SDA) and %u (SCK)\n",
1898 pdata->gpio_sda, pdata->gpio_sck);
1900 err = rtl8366_smi_setup(smi);
1902 goto err_clear_drvdata;
1904 err = rtl8366_smi_mii_init(smi);
1906 goto err_clear_drvdata;
1908 err = rtl8366_smi_switch_init(smi);
1910 goto err_mii_cleanup;
1915 rtl8366_smi_mii_cleanup(smi);
1917 platform_set_drvdata(pdev, NULL);
1918 gpio_free(pdata->gpio_sck);
1920 gpio_free(pdata->gpio_sda);
1927 int rtl8366_phy_config_init(struct phy_device *phydev)
1929 if (!rtl8366_smi_mii_bus_match(phydev->bus))
1935 int rtl8366_phy_config_aneg(struct phy_device *phydev)
1940 static struct phy_driver rtl8366_smi_phy_driver = {
1941 .phy_id = 0x001cc960,
1942 .name = "Realtek RTL8366",
1943 .phy_id_mask = 0x1ffffff0,
1944 .features = PHY_GBIT_FEATURES,
1945 .config_aneg = rtl8366_phy_config_aneg,
1946 .config_init = rtl8366_phy_config_init,
1947 .read_status = genphy_read_status,
1949 .owner = THIS_MODULE,
1953 static int __devexit rtl8366_smi_remove(struct platform_device *pdev)
1955 struct rtl8366_smi *smi = platform_get_drvdata(pdev);
1958 struct rtl8366_smi_platform_data *pdata;
1960 pdata = pdev->dev.platform_data;
1962 rtl8366_smi_switch_cleanup(smi);
1963 rtl8366_debugfs_remove(smi);
1964 rtl8366_smi_mii_cleanup(smi);
1965 platform_set_drvdata(pdev, NULL);
1966 gpio_free(pdata->gpio_sck);
1967 gpio_free(pdata->gpio_sda);
1974 static struct platform_driver rtl8366_smi_driver = {
1976 .name = RTL8366_SMI_DRIVER_NAME,
1977 .owner = THIS_MODULE,
1979 .probe = rtl8366_smi_probe,
1980 .remove = __devexit_p(rtl8366_smi_remove),
1983 static int __init rtl8366_smi_init(void)
1986 ret = platform_driver_register(&rtl8366_smi_driver);
1990 ret = phy_driver_register(&rtl8366_smi_phy_driver);
1992 goto err_platform_unregister;
1996 err_platform_unregister:
1997 platform_driver_unregister(&rtl8366_smi_driver);
2000 module_init(rtl8366_smi_init);
2002 static void __exit rtl8366_smi_exit(void)
2004 phy_driver_unregister(&rtl8366_smi_phy_driver);
2005 platform_driver_unregister(&rtl8366_smi_driver);
2007 module_exit(rtl8366_smi_exit);
2009 MODULE_DESCRIPTION(RTL8366_SMI_DRIVER_DESC);
2010 MODULE_VERSION(RTL8366_SMI_DRIVER_VER);
2011 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
2012 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
2013 MODULE_LICENSE("GPL v2");
2014 MODULE_ALIAS("platform:" RTL8366_SMI_DRIVER_NAME);