2 * Atheros AR71xx built-in ethernet mac driver
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 * Based on Atheros' AG7100 driver
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
16 #define AG71XX_DEFAULT_MSG_ENABLE \
26 static int ag71xx_msg_level = -1;
28 module_param_named(msg_level, ag71xx_msg_level, int, 0);
29 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
31 static void ag71xx_dump_dma_regs(struct ag71xx *ag)
33 DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
35 ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
36 ag71xx_rr(ag, AG71XX_REG_TX_DESC),
37 ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
39 DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
41 ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
42 ag71xx_rr(ag, AG71XX_REG_RX_DESC),
43 ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
46 static void ag71xx_dump_regs(struct ag71xx *ag)
48 DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
50 ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
51 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
52 ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
53 ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
54 ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
55 DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
57 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
58 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
59 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
60 DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
62 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
63 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
64 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
65 DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
67 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
68 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
69 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
72 static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
74 DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
75 ag->dev->name, label, intr,
76 (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
77 (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
78 (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
79 (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
80 (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
81 (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
84 static void ag71xx_ring_free(struct ag71xx_ring *ring)
89 dma_free_coherent(NULL, ring->size * ring->desc_size,
90 ring->descs_cpu, ring->descs_dma);
93 static int ag71xx_ring_alloc(struct ag71xx_ring *ring)
98 ring->desc_size = sizeof(struct ag71xx_desc);
99 if (ring->desc_size % cache_line_size()) {
100 DBG("ag71xx: ring %p, desc size %u rounded to %u\n",
101 ring, ring->desc_size,
102 roundup(ring->desc_size, cache_line_size()));
103 ring->desc_size = roundup(ring->desc_size, cache_line_size());
106 ring->descs_cpu = dma_alloc_coherent(NULL, ring->size * ring->desc_size,
107 &ring->descs_dma, GFP_ATOMIC);
108 if (!ring->descs_cpu) {
114 ring->buf = kzalloc(ring->size * sizeof(*ring->buf), GFP_KERNEL);
120 for (i = 0; i < ring->size; i++) {
121 int idx = i * ring->desc_size;
122 ring->buf[i].desc = (struct ag71xx_desc *)&ring->descs_cpu[idx];
123 DBG("ag71xx: ring %p, desc %d at %p\n",
124 ring, i, ring->buf[i].desc);
133 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
135 struct ag71xx_ring *ring = &ag->tx_ring;
136 struct net_device *dev = ag->dev;
137 u32 bytes_compl = 0, pkts_compl = 0;
139 while (ring->curr != ring->dirty) {
140 u32 i = ring->dirty % ring->size;
142 if (!ag71xx_desc_empty(ring->buf[i].desc)) {
143 ring->buf[i].desc->ctrl = 0;
144 dev->stats.tx_errors++;
147 if (ring->buf[i].skb) {
148 bytes_compl += ring->buf[i].skb->len;
150 dev_kfree_skb_any(ring->buf[i].skb);
152 ring->buf[i].skb = NULL;
156 /* flush descriptors */
159 netdev_completed_queue(dev, pkts_compl, bytes_compl);
162 static void ag71xx_ring_tx_init(struct ag71xx *ag)
164 struct ag71xx_ring *ring = &ag->tx_ring;
167 for (i = 0; i < ring->size; i++) {
168 ring->buf[i].desc->next = (u32) (ring->descs_dma +
169 ring->desc_size * ((i + 1) % ring->size));
171 ring->buf[i].desc->ctrl = DESC_EMPTY;
172 ring->buf[i].skb = NULL;
175 /* flush descriptors */
180 netdev_reset_queue(ag->dev);
183 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
185 struct ag71xx_ring *ring = &ag->rx_ring;
191 for (i = 0; i < ring->size; i++)
192 if (ring->buf[i].skb) {
193 dma_unmap_single(&ag->dev->dev, ring->buf[i].dma_addr,
194 AG71XX_RX_PKT_SIZE, DMA_FROM_DEVICE);
195 kfree_skb(ring->buf[i].skb);
199 static int ag71xx_rx_reserve(struct ag71xx *ag)
203 if (ag71xx_get_pdata(ag)->is_ar724x) {
204 if (!ag71xx_has_ar8216(ag))
208 reserve += 4 - (ag->phy_dev->pkt_align % 4);
213 return reserve + AG71XX_RX_PKT_RESERVE;
217 static int ag71xx_ring_rx_init(struct ag71xx *ag)
219 struct ag71xx_ring *ring = &ag->rx_ring;
220 unsigned int reserve = ag71xx_rx_reserve(ag);
225 for (i = 0; i < ring->size; i++) {
226 ring->buf[i].desc->next = (u32) (ring->descs_dma +
227 ring->desc_size * ((i + 1) % ring->size));
229 DBG("ag71xx: RX desc at %p, next is %08x\n",
231 ring->buf[i].desc->next);
234 for (i = 0; i < ring->size; i++) {
238 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE + reserve);
245 skb_reserve(skb, reserve);
247 dma_addr = dma_map_single(&ag->dev->dev, skb->data,
250 ring->buf[i].skb = skb;
251 ring->buf[i].dma_addr = dma_addr;
252 ring->buf[i].desc->data = (u32) dma_addr;
253 ring->buf[i].desc->ctrl = DESC_EMPTY;
256 /* flush descriptors */
265 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
267 struct ag71xx_ring *ring = &ag->rx_ring;
268 unsigned int reserve = ag71xx_rx_reserve(ag);
272 for (; ring->curr - ring->dirty > 0; ring->dirty++) {
275 i = ring->dirty % ring->size;
277 if (ring->buf[i].skb == NULL) {
281 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE + reserve);
285 skb_reserve(skb, reserve);
288 dma_addr = dma_map_single(&ag->dev->dev, skb->data,
292 ring->buf[i].skb = skb;
293 ring->buf[i].dma_addr = dma_addr;
294 ring->buf[i].desc->data = (u32) dma_addr;
297 ring->buf[i].desc->ctrl = DESC_EMPTY;
301 /* flush descriptors */
304 DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
309 static int ag71xx_rings_init(struct ag71xx *ag)
313 ret = ag71xx_ring_alloc(&ag->tx_ring);
317 ag71xx_ring_tx_init(ag);
319 ret = ag71xx_ring_alloc(&ag->rx_ring);
323 ret = ag71xx_ring_rx_init(ag);
327 static void ag71xx_rings_cleanup(struct ag71xx *ag)
329 ag71xx_ring_rx_clean(ag);
330 ag71xx_ring_free(&ag->rx_ring);
332 ag71xx_ring_tx_clean(ag);
333 netdev_reset_queue(ag->dev);
334 ag71xx_ring_free(&ag->tx_ring);
337 static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
351 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
355 t = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16)
356 | (((u32) mac[3]) << 8) | ((u32) mac[2]);
358 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
360 t = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16);
361 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
364 static void ag71xx_dma_reset(struct ag71xx *ag)
369 ag71xx_dump_dma_regs(ag);
372 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
373 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
376 * give the hardware some time to really stop all rx/tx activity
377 * clearing the descriptors too early causes random memory corruption
381 /* clear descriptor addresses */
382 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->stop_desc_dma);
383 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->stop_desc_dma);
385 /* clear pending RX/TX interrupts */
386 for (i = 0; i < 256; i++) {
387 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
388 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
391 /* clear pending errors */
392 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
393 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
395 val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
397 pr_alert("%s: unable to clear DMA Rx status: %08x\n",
400 val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
402 /* mask out reserved bits */
406 pr_alert("%s: unable to clear DMA Tx status: %08x\n",
409 ag71xx_dump_dma_regs(ag);
412 #define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
413 MAC_CFG1_SRX | MAC_CFG1_STX)
415 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
417 #define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
418 FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
419 FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
420 FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
421 FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
424 #define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
425 FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
426 FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
427 FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
428 FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
429 FIFO_CFG5_17 | FIFO_CFG5_SF)
431 static void ag71xx_hw_stop(struct ag71xx *ag)
433 /* disable all interrupts and stop the rx/tx engine */
434 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
435 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
436 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
439 static void ag71xx_hw_setup(struct ag71xx *ag)
441 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
443 /* setup MAC configuration registers */
444 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT);
446 ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
447 MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
449 /* setup max frame length */
450 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, AG71XX_TX_MTU_LEN);
452 /* setup FIFO configuration registers */
453 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
454 if (pdata->is_ar724x) {
455 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, pdata->fifo_cfg1);
456 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, pdata->fifo_cfg2);
458 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
459 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
461 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
462 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
465 static void ag71xx_hw_init(struct ag71xx *ag)
467 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
468 u32 reset_mask = pdata->reset_bit;
472 if (pdata->is_ar724x) {
473 u32 reset_phy = reset_mask;
475 reset_phy &= AR71XX_RESET_GE0_PHY | AR71XX_RESET_GE1_PHY;
476 reset_mask &= ~(AR71XX_RESET_GE0_PHY | AR71XX_RESET_GE1_PHY);
478 ath79_device_reset_set(reset_phy);
480 ath79_device_reset_clear(reset_phy);
484 ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
487 ath79_device_reset_set(reset_mask);
489 ath79_device_reset_clear(reset_mask);
494 ag71xx_dma_reset(ag);
497 static void ag71xx_fast_reset(struct ag71xx *ag)
499 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
500 struct net_device *dev = ag->dev;
501 u32 reset_mask = pdata->reset_bit;
505 reset_mask &= AR71XX_RESET_GE0_MAC | AR71XX_RESET_GE1_MAC;
507 mii_reg = ag71xx_rr(ag, AG71XX_REG_MII_CFG);
508 rx_ds = ag71xx_rr(ag, AG71XX_REG_RX_DESC);
509 tx_ds = ag71xx_rr(ag, AG71XX_REG_TX_DESC);
511 ath79_device_reset_set(reset_mask);
513 ath79_device_reset_clear(reset_mask);
516 ag71xx_dma_reset(ag);
519 ag71xx_wr(ag, AG71XX_REG_RX_DESC, rx_ds);
520 ag71xx_wr(ag, AG71XX_REG_TX_DESC, tx_ds);
521 ag71xx_wr(ag, AG71XX_REG_MII_CFG, mii_reg);
523 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
526 static void ag71xx_hw_start(struct ag71xx *ag)
528 /* start RX engine */
529 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
531 /* enable interrupts */
532 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
535 void ag71xx_link_adjust(struct ag71xx *ag)
537 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
544 netif_carrier_off(ag->dev);
545 if (netif_msg_link(ag))
546 pr_info("%s: link down\n", ag->dev->name);
550 if (pdata->is_ar724x)
551 ag71xx_fast_reset(ag);
553 cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
554 cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
555 cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
557 ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
558 ifctl &= ~(MAC_IFCTL_SPEED);
560 fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
561 fifo5 &= ~FIFO_CFG5_BM;
565 cfg2 |= MAC_CFG2_IF_1000;
566 fifo5 |= FIFO_CFG5_BM;
569 cfg2 |= MAC_CFG2_IF_10_100;
570 ifctl |= MAC_IFCTL_SPEED;
573 cfg2 |= MAC_CFG2_IF_10_100;
580 if (pdata->is_ar91xx)
581 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x00780fff);
582 else if (pdata->is_ar724x)
583 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, pdata->fifo_cfg3);
585 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x008001ff);
587 if (pdata->set_speed)
588 pdata->set_speed(ag->speed);
590 ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
591 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
592 ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
595 netif_carrier_on(ag->dev);
596 if (netif_msg_link(ag))
597 pr_info("%s: link up (%sMbps/%s duplex)\n",
599 ag71xx_speed_str(ag),
600 (DUPLEX_FULL == ag->duplex) ? "Full" : "Half");
602 DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n",
604 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
605 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
606 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
608 DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n",
610 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
611 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
612 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
614 DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x\n",
616 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
617 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL));
620 static int ag71xx_open(struct net_device *dev)
622 struct ag71xx *ag = netdev_priv(dev);
625 ret = ag71xx_rings_init(ag);
629 napi_enable(&ag->napi);
631 netif_carrier_off(dev);
632 ag71xx_phy_start(ag);
634 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
635 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
637 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
639 netif_start_queue(dev);
644 ag71xx_rings_cleanup(ag);
648 static int ag71xx_stop(struct net_device *dev)
650 struct ag71xx *ag = netdev_priv(dev);
653 netif_carrier_off(dev);
656 spin_lock_irqsave(&ag->lock, flags);
658 netif_stop_queue(dev);
661 ag71xx_dma_reset(ag);
663 napi_disable(&ag->napi);
664 del_timer_sync(&ag->oom_timer);
666 spin_unlock_irqrestore(&ag->lock, flags);
668 ag71xx_rings_cleanup(ag);
673 static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb,
674 struct net_device *dev)
676 struct ag71xx *ag = netdev_priv(dev);
677 struct ag71xx_ring *ring = &ag->tx_ring;
678 struct ag71xx_desc *desc;
682 i = ring->curr % ring->size;
683 desc = ring->buf[i].desc;
685 if (!ag71xx_desc_empty(desc))
688 if (ag71xx_has_ar8216(ag))
689 ag71xx_add_ar8216_header(ag, skb);
692 DBG("%s: packet len is too small\n", ag->dev->name);
696 dma_addr = dma_map_single(&dev->dev, skb->data, skb->len,
699 netdev_sent_queue(dev, skb->len);
700 ring->buf[i].skb = skb;
701 ring->buf[i].timestamp = jiffies;
703 /* setup descriptor fields */
704 desc->data = (u32) dma_addr;
705 desc->ctrl = (skb->len & DESC_PKTLEN_M);
707 /* flush descriptor */
711 if (ring->curr == (ring->dirty + ring->size)) {
712 DBG("%s: tx queue full\n", ag->dev->name);
713 netif_stop_queue(dev);
716 DBG("%s: packet injected into TX queue\n", ag->dev->name);
718 /* enable TX engine */
719 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
724 dev->stats.tx_dropped++;
730 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
732 struct ag71xx *ag = netdev_priv(dev);
737 if (ag->phy_dev == NULL)
740 spin_lock_irq(&ag->lock);
741 ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
742 spin_unlock_irq(&ag->lock);
747 (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
753 (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
760 if (ag->phy_dev == NULL)
763 return phy_mii_ioctl(ag->phy_dev, ifr, cmd);
772 static void ag71xx_oom_timer_handler(unsigned long data)
774 struct net_device *dev = (struct net_device *) data;
775 struct ag71xx *ag = netdev_priv(dev);
777 napi_schedule(&ag->napi);
780 static void ag71xx_tx_timeout(struct net_device *dev)
782 struct ag71xx *ag = netdev_priv(dev);
784 if (netif_msg_tx_err(ag))
785 pr_info("%s: tx timeout\n", ag->dev->name);
787 schedule_work(&ag->restart_work);
790 static void ag71xx_restart_work_func(struct work_struct *work)
792 struct ag71xx *ag = container_of(work, struct ag71xx, restart_work);
794 if (ag71xx_get_pdata(ag)->is_ar724x) {
796 ag71xx_link_adjust(ag);
800 ag71xx_stop(ag->dev);
801 ag71xx_open(ag->dev);
804 static bool ag71xx_check_dma_stuck(struct ag71xx *ag, unsigned long timestamp)
806 u32 rx_sm, tx_sm, rx_fd;
808 if (likely(time_before(jiffies, timestamp + HZ/10)))
811 if (!netif_carrier_ok(ag->dev))
814 rx_sm = ag71xx_rr(ag, AG71XX_REG_RX_SM);
815 if ((rx_sm & 0x7) == 0x3 && ((rx_sm >> 4) & 0x7) == 0x6)
818 tx_sm = ag71xx_rr(ag, AG71XX_REG_TX_SM);
819 rx_fd = ag71xx_rr(ag, AG71XX_REG_FIFO_DEPTH);
820 if (((tx_sm >> 4) & 0x7) == 0 && ((rx_sm & 0x7) == 0) &&
821 ((rx_sm >> 4) & 0x7) == 0 && rx_fd == 0)
827 static int ag71xx_tx_packets(struct ag71xx *ag)
829 struct ag71xx_ring *ring = &ag->tx_ring;
830 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
834 DBG("%s: processing TX ring\n", ag->dev->name);
836 while (ring->dirty != ring->curr) {
837 unsigned int i = ring->dirty % ring->size;
838 struct ag71xx_desc *desc = ring->buf[i].desc;
839 struct sk_buff *skb = ring->buf[i].skb;
841 if (!ag71xx_desc_empty(desc)) {
842 if (pdata->is_ar7240 &&
843 ag71xx_check_dma_stuck(ag, ring->buf[i].timestamp))
844 schedule_work(&ag->restart_work);
848 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
850 bytes_compl += skb->len;
851 ag->dev->stats.tx_bytes += skb->len;
852 ag->dev->stats.tx_packets++;
854 dev_kfree_skb_any(skb);
855 ring->buf[i].skb = NULL;
861 DBG("%s: %d packets sent out\n", ag->dev->name, sent);
863 netdev_completed_queue(ag->dev, sent, bytes_compl);
864 if ((ring->curr - ring->dirty) < (ring->size * 3) / 4)
865 netif_wake_queue(ag->dev);
870 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
872 struct net_device *dev = ag->dev;
873 struct ag71xx_ring *ring = &ag->rx_ring;
876 DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
877 dev->name, limit, ring->curr, ring->dirty);
879 while (done < limit) {
880 unsigned int i = ring->curr % ring->size;
881 struct ag71xx_desc *desc = ring->buf[i].desc;
886 if (ag71xx_desc_empty(desc))
889 if ((ring->dirty + ring->size) == ring->curr) {
894 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
896 skb = ring->buf[i].skb;
897 pktlen = ag71xx_desc_pktlen(desc);
898 pktlen -= ETH_FCS_LEN;
900 dma_unmap_single(&dev->dev, ring->buf[i].dma_addr,
901 AG71XX_RX_PKT_SIZE, DMA_FROM_DEVICE);
903 dev->last_rx = jiffies;
904 dev->stats.rx_packets++;
905 dev->stats.rx_bytes += pktlen;
907 skb_put(skb, pktlen);
908 if (ag71xx_has_ar8216(ag))
909 err = ag71xx_remove_ar8216_header(ag, skb, pktlen);
912 dev->stats.rx_dropped++;
916 skb->ip_summed = CHECKSUM_NONE;
918 ag->phy_dev->netif_receive_skb(skb);
920 skb->protocol = eth_type_trans(skb, dev);
921 netif_receive_skb(skb);
925 ring->buf[i].skb = NULL;
931 ag71xx_ring_rx_refill(ag);
933 DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
934 dev->name, ring->curr, ring->dirty, done);
939 static int ag71xx_poll(struct napi_struct *napi, int limit)
941 struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
942 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
943 struct net_device *dev = ag->dev;
944 struct ag71xx_ring *rx_ring;
951 tx_done = ag71xx_tx_packets(ag);
953 DBG("%s: processing RX ring\n", dev->name);
954 rx_done = ag71xx_rx_packets(ag, limit);
956 ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done);
958 rx_ring = &ag->rx_ring;
959 if (rx_ring->buf[rx_ring->dirty % rx_ring->size].skb == NULL)
962 status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
963 if (unlikely(status & RX_STATUS_OF)) {
964 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
965 dev->stats.rx_fifo_errors++;
968 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
971 if (rx_done < limit) {
972 if (status & RX_STATUS_PR)
975 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
976 if (status & TX_STATUS_PS)
979 DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n",
980 dev->name, rx_done, tx_done, limit);
984 /* enable interrupts */
985 spin_lock_irqsave(&ag->lock, flags);
986 ag71xx_int_enable(ag, AG71XX_INT_POLL);
987 spin_unlock_irqrestore(&ag->lock, flags);
992 DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n",
993 dev->name, rx_done, tx_done, limit);
997 if (netif_msg_rx_err(ag))
998 pr_info("%s: out of memory\n", dev->name);
1000 mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
1001 napi_complete(napi);
1005 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
1007 struct net_device *dev = dev_id;
1008 struct ag71xx *ag = netdev_priv(dev);
1011 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
1012 ag71xx_dump_intr(ag, "raw", status);
1014 if (unlikely(!status))
1017 if (unlikely(status & AG71XX_INT_ERR)) {
1018 if (status & AG71XX_INT_TX_BE) {
1019 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
1020 dev_err(&dev->dev, "TX BUS error\n");
1022 if (status & AG71XX_INT_RX_BE) {
1023 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
1024 dev_err(&dev->dev, "RX BUS error\n");
1028 if (likely(status & AG71XX_INT_POLL)) {
1029 ag71xx_int_disable(ag, AG71XX_INT_POLL);
1030 DBG("%s: enable polling mode\n", dev->name);
1031 napi_schedule(&ag->napi);
1034 ag71xx_debugfs_update_int_stats(ag, status);
1039 #ifdef CONFIG_NET_POLL_CONTROLLER
1041 * Polling 'interrupt' - used by things like netconsole to send skbs
1042 * without having to re-enable interrupts. It's not called while
1043 * the interrupt routine is executing.
1045 static void ag71xx_netpoll(struct net_device *dev)
1047 disable_irq(dev->irq);
1048 ag71xx_interrupt(dev->irq, dev);
1049 enable_irq(dev->irq);
1053 static const struct net_device_ops ag71xx_netdev_ops = {
1054 .ndo_open = ag71xx_open,
1055 .ndo_stop = ag71xx_stop,
1056 .ndo_start_xmit = ag71xx_hard_start_xmit,
1057 .ndo_do_ioctl = ag71xx_do_ioctl,
1058 .ndo_tx_timeout = ag71xx_tx_timeout,
1059 .ndo_change_mtu = eth_change_mtu,
1060 .ndo_set_mac_address = eth_mac_addr,
1061 .ndo_validate_addr = eth_validate_addr,
1062 #ifdef CONFIG_NET_POLL_CONTROLLER
1063 .ndo_poll_controller = ag71xx_netpoll,
1067 static int __devinit ag71xx_probe(struct platform_device *pdev)
1069 struct net_device *dev;
1070 struct resource *res;
1072 struct ag71xx_platform_data *pdata;
1075 pdata = pdev->dev.platform_data;
1077 dev_err(&pdev->dev, "no platform data specified\n");
1082 if (pdata->mii_bus_dev == NULL) {
1083 dev_err(&pdev->dev, "no MII bus device specified\n");
1088 dev = alloc_etherdev(sizeof(*ag));
1090 dev_err(&pdev->dev, "alloc_etherdev failed\n");
1095 SET_NETDEV_DEV(dev, &pdev->dev);
1097 ag = netdev_priv(dev);
1100 ag->msg_enable = netif_msg_init(ag71xx_msg_level,
1101 AG71XX_DEFAULT_MSG_ENABLE);
1102 spin_lock_init(&ag->lock);
1104 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
1106 dev_err(&pdev->dev, "no mac_base resource found\n");
1111 ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1);
1112 if (!ag->mac_base) {
1113 dev_err(&pdev->dev, "unable to ioremap mac_base\n");
1118 dev->irq = platform_get_irq(pdev, 0);
1119 err = request_irq(dev->irq, ag71xx_interrupt,
1123 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
1124 goto err_unmap_base;
1127 dev->base_addr = (unsigned long)ag->mac_base;
1128 dev->netdev_ops = &ag71xx_netdev_ops;
1129 dev->ethtool_ops = &ag71xx_ethtool_ops;
1131 INIT_WORK(&ag->restart_work, ag71xx_restart_work_func);
1133 init_timer(&ag->oom_timer);
1134 ag->oom_timer.data = (unsigned long) dev;
1135 ag->oom_timer.function = ag71xx_oom_timer_handler;
1137 ag->tx_ring.size = AG71XX_TX_RING_SIZE_DEFAULT;
1138 ag->rx_ring.size = AG71XX_RX_RING_SIZE_DEFAULT;
1140 ag->stop_desc = dma_alloc_coherent(NULL,
1141 sizeof(struct ag71xx_desc), &ag->stop_desc_dma, GFP_KERNEL);
1146 ag->stop_desc->data = 0;
1147 ag->stop_desc->ctrl = 0;
1148 ag->stop_desc->next = (u32) ag->stop_desc_dma;
1150 memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
1152 netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
1154 err = register_netdev(dev);
1156 dev_err(&pdev->dev, "unable to register net device\n");
1160 pr_info("%s: Atheros AG71xx at 0x%08lx, irq %d\n",
1161 dev->name, dev->base_addr, dev->irq);
1163 ag71xx_dump_regs(ag);
1167 ag71xx_dump_regs(ag);
1169 err = ag71xx_phy_connect(ag);
1171 goto err_unregister_netdev;
1173 err = ag71xx_debugfs_init(ag);
1175 goto err_phy_disconnect;
1177 platform_set_drvdata(pdev, dev);
1182 ag71xx_phy_disconnect(ag);
1183 err_unregister_netdev:
1184 unregister_netdev(dev);
1186 dma_free_coherent(NULL, sizeof(struct ag71xx_desc), ag->stop_desc,
1189 free_irq(dev->irq, dev);
1191 iounmap(ag->mac_base);
1195 platform_set_drvdata(pdev, NULL);
1199 static int __devexit ag71xx_remove(struct platform_device *pdev)
1201 struct net_device *dev = platform_get_drvdata(pdev);
1204 struct ag71xx *ag = netdev_priv(dev);
1206 ag71xx_debugfs_exit(ag);
1207 ag71xx_phy_disconnect(ag);
1208 unregister_netdev(dev);
1209 free_irq(dev->irq, dev);
1210 iounmap(ag->mac_base);
1212 platform_set_drvdata(pdev, NULL);
1218 static struct platform_driver ag71xx_driver = {
1219 .probe = ag71xx_probe,
1220 .remove = __exit_p(ag71xx_remove),
1222 .name = AG71XX_DRV_NAME,
1226 static int __init ag71xx_module_init(void)
1230 ret = ag71xx_debugfs_root_init();
1234 ret = ag71xx_mdio_driver_init();
1236 goto err_debugfs_exit;
1238 ret = platform_driver_register(&ag71xx_driver);
1245 ag71xx_mdio_driver_exit();
1247 ag71xx_debugfs_root_exit();
1252 static void __exit ag71xx_module_exit(void)
1254 platform_driver_unregister(&ag71xx_driver);
1255 ag71xx_mdio_driver_exit();
1256 ag71xx_debugfs_root_exit();
1259 module_init(ag71xx_module_init);
1260 module_exit(ag71xx_module_exit);
1262 MODULE_VERSION(AG71XX_DRV_VERSION);
1263 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1264 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
1265 MODULE_LICENSE("GPL v2");
1266 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);