2 * Atheros AR71xx built-in ethernet mac driver
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 * Based on Atheros' AG7100 driver
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
16 #define AG71XX_DEFAULT_MSG_ENABLE \
26 static int ag71xx_msg_level = -1;
28 module_param_named(msg_level, ag71xx_msg_level, int, 0);
29 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
31 #define ETH_SWITCH_HEADER_LEN 2
33 static inline unsigned int ag71xx_max_frame_len(unsigned int mtu)
35 return ETH_SWITCH_HEADER_LEN + ETH_HLEN + VLAN_HLEN + mtu + ETH_FCS_LEN;
38 static void ag71xx_dump_dma_regs(struct ag71xx *ag)
40 DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
42 ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
43 ag71xx_rr(ag, AG71XX_REG_TX_DESC),
44 ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
46 DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
48 ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
49 ag71xx_rr(ag, AG71XX_REG_RX_DESC),
50 ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
53 static void ag71xx_dump_regs(struct ag71xx *ag)
55 DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
57 ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
58 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
59 ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
60 ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
61 ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
62 DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
64 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
65 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
66 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
67 DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
69 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
70 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
71 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
72 DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
74 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
75 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
76 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
79 static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
81 DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
82 ag->dev->name, label, intr,
83 (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
84 (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
85 (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
86 (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
87 (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
88 (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
91 static void ag71xx_ring_free(struct ag71xx_ring *ring)
96 dma_free_coherent(NULL, ring->size * ring->desc_size,
97 ring->descs_cpu, ring->descs_dma);
100 static int ag71xx_ring_alloc(struct ag71xx_ring *ring)
105 ring->desc_size = sizeof(struct ag71xx_desc);
106 if (ring->desc_size % cache_line_size()) {
107 DBG("ag71xx: ring %p, desc size %u rounded to %u\n",
108 ring, ring->desc_size,
109 roundup(ring->desc_size, cache_line_size()));
110 ring->desc_size = roundup(ring->desc_size, cache_line_size());
113 ring->descs_cpu = dma_alloc_coherent(NULL, ring->size * ring->desc_size,
114 &ring->descs_dma, GFP_ATOMIC);
115 if (!ring->descs_cpu) {
121 ring->buf = kzalloc(ring->size * sizeof(*ring->buf), GFP_KERNEL);
127 for (i = 0; i < ring->size; i++) {
128 int idx = i * ring->desc_size;
129 ring->buf[i].desc = (struct ag71xx_desc *)&ring->descs_cpu[idx];
130 DBG("ag71xx: ring %p, desc %d at %p\n",
131 ring, i, ring->buf[i].desc);
140 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
142 struct ag71xx_ring *ring = &ag->tx_ring;
143 struct net_device *dev = ag->dev;
144 u32 bytes_compl = 0, pkts_compl = 0;
146 while (ring->curr != ring->dirty) {
147 u32 i = ring->dirty % ring->size;
149 if (!ag71xx_desc_empty(ring->buf[i].desc)) {
150 ring->buf[i].desc->ctrl = 0;
151 dev->stats.tx_errors++;
154 if (ring->buf[i].skb) {
155 bytes_compl += ring->buf[i].len;
157 dev_kfree_skb_any(ring->buf[i].skb);
159 ring->buf[i].skb = NULL;
163 /* flush descriptors */
166 netdev_completed_queue(dev, pkts_compl, bytes_compl);
169 static void ag71xx_ring_tx_init(struct ag71xx *ag)
171 struct ag71xx_ring *ring = &ag->tx_ring;
174 for (i = 0; i < ring->size; i++) {
175 ring->buf[i].desc->next = (u32) (ring->descs_dma +
176 ring->desc_size * ((i + 1) % ring->size));
178 ring->buf[i].desc->ctrl = DESC_EMPTY;
179 ring->buf[i].skb = NULL;
182 /* flush descriptors */
187 netdev_reset_queue(ag->dev);
190 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
192 struct ag71xx_ring *ring = &ag->rx_ring;
198 for (i = 0; i < ring->size; i++)
199 if (ring->buf[i].rx_buf) {
200 dma_unmap_single(&ag->dev->dev, ring->buf[i].dma_addr,
201 ag->rx_buf_size, DMA_FROM_DEVICE);
202 kfree(ring->buf[i].rx_buf);
206 static int ag71xx_buffer_offset(struct ag71xx *ag)
208 int offset = NET_SKB_PAD;
211 * On AR71xx/AR91xx packets must be 4-byte aligned.
213 * When using builtin AR8216 support, hardware adds a 2-byte header,
214 * so we don't need any extra alignment in that case.
216 if (!ag71xx_get_pdata(ag)->is_ar724x || ag71xx_has_ar8216(ag))
219 return offset + NET_IP_ALIGN;
222 static bool ag71xx_fill_rx_buf(struct ag71xx *ag, struct ag71xx_buf *buf,
227 data = kmalloc(ag->rx_buf_size +
228 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)),
234 buf->dma_addr = dma_map_single(&ag->dev->dev, data, ag->rx_buf_size,
236 buf->desc->data = (u32) buf->dma_addr + offset;
240 static int ag71xx_ring_rx_init(struct ag71xx *ag)
242 struct ag71xx_ring *ring = &ag->rx_ring;
245 int offset = ag71xx_buffer_offset(ag);
248 for (i = 0; i < ring->size; i++) {
249 ring->buf[i].desc->next = (u32) (ring->descs_dma +
250 ring->desc_size * ((i + 1) % ring->size));
252 DBG("ag71xx: RX desc at %p, next is %08x\n",
254 ring->buf[i].desc->next);
257 for (i = 0; i < ring->size; i++) {
258 if (!ag71xx_fill_rx_buf(ag, &ring->buf[i], offset)) {
263 ring->buf[i].desc->ctrl = DESC_EMPTY;
266 /* flush descriptors */
275 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
277 struct ag71xx_ring *ring = &ag->rx_ring;
279 int offset = ag71xx_buffer_offset(ag);
282 for (; ring->curr - ring->dirty > 0; ring->dirty++) {
285 i = ring->dirty % ring->size;
287 if (!ring->buf[i].rx_buf &&
288 !ag71xx_fill_rx_buf(ag, &ring->buf[i], offset))
291 ring->buf[i].desc->ctrl = DESC_EMPTY;
295 /* flush descriptors */
298 DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
303 static int ag71xx_rings_init(struct ag71xx *ag)
307 ret = ag71xx_ring_alloc(&ag->tx_ring);
311 ag71xx_ring_tx_init(ag);
313 ret = ag71xx_ring_alloc(&ag->rx_ring);
317 ret = ag71xx_ring_rx_init(ag);
321 static void ag71xx_rings_cleanup(struct ag71xx *ag)
323 ag71xx_ring_rx_clean(ag);
324 ag71xx_ring_free(&ag->rx_ring);
326 ag71xx_ring_tx_clean(ag);
327 netdev_reset_queue(ag->dev);
328 ag71xx_ring_free(&ag->tx_ring);
331 static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
345 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
349 t = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16)
350 | (((u32) mac[3]) << 8) | ((u32) mac[2]);
352 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
354 t = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16);
355 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
358 static void ag71xx_dma_reset(struct ag71xx *ag)
363 ag71xx_dump_dma_regs(ag);
366 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
367 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
370 * give the hardware some time to really stop all rx/tx activity
371 * clearing the descriptors too early causes random memory corruption
375 /* clear descriptor addresses */
376 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->stop_desc_dma);
377 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->stop_desc_dma);
379 /* clear pending RX/TX interrupts */
380 for (i = 0; i < 256; i++) {
381 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
382 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
385 /* clear pending errors */
386 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
387 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
389 val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
391 pr_alert("%s: unable to clear DMA Rx status: %08x\n",
394 val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
396 /* mask out reserved bits */
400 pr_alert("%s: unable to clear DMA Tx status: %08x\n",
403 ag71xx_dump_dma_regs(ag);
406 #define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
407 MAC_CFG1_SRX | MAC_CFG1_STX)
409 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
411 #define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
412 FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
413 FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
414 FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
415 FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
418 #define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
419 FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
420 FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
421 FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
422 FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
423 FIFO_CFG5_17 | FIFO_CFG5_SF)
425 static void ag71xx_hw_stop(struct ag71xx *ag)
427 /* disable all interrupts and stop the rx/tx engine */
428 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
429 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
430 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
433 static void ag71xx_hw_setup(struct ag71xx *ag)
435 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
437 /* setup MAC configuration registers */
438 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT);
440 ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
441 MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
443 /* setup max frame length to zero */
444 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, 0);
446 /* setup FIFO configuration registers */
447 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
448 if (pdata->is_ar724x) {
449 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, pdata->fifo_cfg1);
450 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, pdata->fifo_cfg2);
452 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
453 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
455 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
456 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
459 static void ag71xx_hw_init(struct ag71xx *ag)
461 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
462 u32 reset_mask = pdata->reset_bit;
466 if (pdata->is_ar724x) {
467 u32 reset_phy = reset_mask;
469 reset_phy &= AR71XX_RESET_GE0_PHY | AR71XX_RESET_GE1_PHY;
470 reset_mask &= ~(AR71XX_RESET_GE0_PHY | AR71XX_RESET_GE1_PHY);
472 ath79_device_reset_set(reset_phy);
474 ath79_device_reset_clear(reset_phy);
478 ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
481 ath79_device_reset_set(reset_mask);
483 ath79_device_reset_clear(reset_mask);
488 ag71xx_dma_reset(ag);
491 static void ag71xx_fast_reset(struct ag71xx *ag)
493 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
494 struct net_device *dev = ag->dev;
495 u32 reset_mask = pdata->reset_bit;
499 reset_mask &= AR71XX_RESET_GE0_MAC | AR71XX_RESET_GE1_MAC;
501 mii_reg = ag71xx_rr(ag, AG71XX_REG_MII_CFG);
502 rx_ds = ag71xx_rr(ag, AG71XX_REG_RX_DESC);
503 tx_ds = ag71xx_rr(ag, AG71XX_REG_TX_DESC);
505 ath79_device_reset_set(reset_mask);
507 ath79_device_reset_clear(reset_mask);
510 ag71xx_dma_reset(ag);
513 /* setup max frame length */
514 ag71xx_wr(ag, AG71XX_REG_MAC_MFL,
515 ag71xx_max_frame_len(ag->dev->mtu));
517 ag71xx_wr(ag, AG71XX_REG_RX_DESC, rx_ds);
518 ag71xx_wr(ag, AG71XX_REG_TX_DESC, tx_ds);
519 ag71xx_wr(ag, AG71XX_REG_MII_CFG, mii_reg);
521 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
524 static void ag71xx_hw_start(struct ag71xx *ag)
526 /* start RX engine */
527 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
529 /* enable interrupts */
530 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
533 void ag71xx_link_adjust(struct ag71xx *ag)
535 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
543 netif_carrier_off(ag->dev);
544 if (netif_msg_link(ag))
545 pr_info("%s: link down\n", ag->dev->name);
549 if (pdata->is_ar724x)
550 ag71xx_fast_reset(ag);
552 cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
553 cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
554 cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
556 ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
557 ifctl &= ~(MAC_IFCTL_SPEED);
559 fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
560 fifo5 &= ~FIFO_CFG5_BM;
564 cfg2 |= MAC_CFG2_IF_1000;
565 fifo5 |= FIFO_CFG5_BM;
568 cfg2 |= MAC_CFG2_IF_10_100;
569 ifctl |= MAC_IFCTL_SPEED;
572 cfg2 |= MAC_CFG2_IF_10_100;
579 if (pdata->is_ar91xx)
581 else if (pdata->is_ar724x)
582 fifo3 = pdata->fifo_cfg3;
586 if (ag->tx_ring.desc_split) {
588 fifo3 |= ((2048 - ag->tx_ring.desc_split) / 4) << 16;
591 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, fifo3);
593 if (pdata->set_speed)
594 pdata->set_speed(ag->speed);
596 ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
597 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
598 ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
601 netif_carrier_on(ag->dev);
602 if (netif_msg_link(ag))
603 pr_info("%s: link up (%sMbps/%s duplex)\n",
605 ag71xx_speed_str(ag),
606 (DUPLEX_FULL == ag->duplex) ? "Full" : "Half");
608 DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n",
610 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
611 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
612 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
614 DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n",
616 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
617 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
618 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
620 DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x\n",
622 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
623 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL));
626 static int ag71xx_open(struct net_device *dev)
628 struct ag71xx *ag = netdev_priv(dev);
629 unsigned int max_frame_len;
632 max_frame_len = ag71xx_max_frame_len(dev->mtu);
633 ag->rx_buf_size = max_frame_len + NET_SKB_PAD + NET_IP_ALIGN;
635 /* setup max frame length */
636 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, max_frame_len);
638 ret = ag71xx_rings_init(ag);
642 napi_enable(&ag->napi);
644 netif_carrier_off(dev);
645 ag71xx_phy_start(ag);
647 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
648 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
650 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
652 netif_start_queue(dev);
657 ag71xx_rings_cleanup(ag);
661 static int ag71xx_stop(struct net_device *dev)
663 struct ag71xx *ag = netdev_priv(dev);
666 netif_carrier_off(dev);
669 spin_lock_irqsave(&ag->lock, flags);
671 netif_stop_queue(dev);
674 ag71xx_dma_reset(ag);
676 napi_disable(&ag->napi);
677 del_timer_sync(&ag->oom_timer);
679 spin_unlock_irqrestore(&ag->lock, flags);
681 ag71xx_rings_cleanup(ag);
686 static int ag71xx_fill_dma_desc(struct ag71xx_ring *ring, u32 addr, int len)
689 struct ag71xx_desc *desc;
691 int split = ring->desc_split;
697 unsigned int cur_len = len;
699 i = (ring->curr + ndesc) % ring->size;
700 desc = ring->buf[i].desc;
702 if (!ag71xx_desc_empty(desc))
705 if (cur_len > split) {
709 * TX will hang if DMA transfers <= 4 bytes,
710 * make sure next segment is more than 4 bytes long.
712 if (len <= split + 4)
721 cur_len |= DESC_MORE;
723 /* prevent early tx attempt of this descriptor */
725 cur_len |= DESC_EMPTY;
727 desc->ctrl = cur_len;
734 static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb,
735 struct net_device *dev)
737 struct ag71xx *ag = netdev_priv(dev);
738 struct ag71xx_ring *ring = &ag->tx_ring;
739 struct ag71xx_desc *desc;
743 if (ag71xx_has_ar8216(ag))
744 ag71xx_add_ar8216_header(ag, skb);
747 DBG("%s: packet len is too small\n", ag->dev->name);
751 dma_addr = dma_map_single(&dev->dev, skb->data, skb->len,
754 i = ring->curr % ring->size;
755 desc = ring->buf[i].desc;
757 /* setup descriptor fields */
758 n = ag71xx_fill_dma_desc(ring, (u32) dma_addr, skb->len & ag->desc_pktlen_mask);
762 i = (ring->curr + n - 1) % ring->size;
763 ring->buf[i].len = skb->len;
764 ring->buf[i].skb = skb;
765 ring->buf[i].timestamp = jiffies;
767 netdev_sent_queue(dev, skb->len);
769 desc->ctrl &= ~DESC_EMPTY;
772 /* flush descriptor */
776 if (ring->desc_split)
777 ring_min *= AG71XX_TX_RING_DS_PER_PKT;
779 if (ring->curr - ring->dirty >= ring->size - ring_min) {
780 DBG("%s: tx queue full\n", dev->name);
781 netif_stop_queue(dev);
784 DBG("%s: packet injected into TX queue\n", ag->dev->name);
786 /* enable TX engine */
787 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
792 dma_unmap_single(&dev->dev, dma_addr, skb->len, DMA_TO_DEVICE);
795 dev->stats.tx_dropped++;
801 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
803 struct ag71xx *ag = netdev_priv(dev);
808 if (ag->phy_dev == NULL)
811 spin_lock_irq(&ag->lock);
812 ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
813 spin_unlock_irq(&ag->lock);
818 (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
824 (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
831 if (ag->phy_dev == NULL)
834 return phy_mii_ioctl(ag->phy_dev, ifr, cmd);
843 static void ag71xx_oom_timer_handler(unsigned long data)
845 struct net_device *dev = (struct net_device *) data;
846 struct ag71xx *ag = netdev_priv(dev);
848 napi_schedule(&ag->napi);
851 static void ag71xx_tx_timeout(struct net_device *dev)
853 struct ag71xx *ag = netdev_priv(dev);
855 if (netif_msg_tx_err(ag))
856 pr_info("%s: tx timeout\n", ag->dev->name);
858 schedule_work(&ag->restart_work);
861 static void ag71xx_restart_work_func(struct work_struct *work)
863 struct ag71xx *ag = container_of(work, struct ag71xx, restart_work);
865 if (ag71xx_get_pdata(ag)->is_ar724x) {
867 ag71xx_link_adjust(ag);
871 ag71xx_stop(ag->dev);
872 ag71xx_open(ag->dev);
875 static bool ag71xx_check_dma_stuck(struct ag71xx *ag, unsigned long timestamp)
877 u32 rx_sm, tx_sm, rx_fd;
879 if (likely(time_before(jiffies, timestamp + HZ/10)))
882 if (!netif_carrier_ok(ag->dev))
885 rx_sm = ag71xx_rr(ag, AG71XX_REG_RX_SM);
886 if ((rx_sm & 0x7) == 0x3 && ((rx_sm >> 4) & 0x7) == 0x6)
889 tx_sm = ag71xx_rr(ag, AG71XX_REG_TX_SM);
890 rx_fd = ag71xx_rr(ag, AG71XX_REG_FIFO_DEPTH);
891 if (((tx_sm >> 4) & 0x7) == 0 && ((rx_sm & 0x7) == 0) &&
892 ((rx_sm >> 4) & 0x7) == 0 && rx_fd == 0)
898 static int ag71xx_tx_packets(struct ag71xx *ag)
900 struct ag71xx_ring *ring = &ag->tx_ring;
901 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
905 DBG("%s: processing TX ring\n", ag->dev->name);
907 while (ring->dirty != ring->curr) {
908 unsigned int i = ring->dirty % ring->size;
909 struct ag71xx_desc *desc = ring->buf[i].desc;
910 struct sk_buff *skb = ring->buf[i].skb;
912 if (!ag71xx_desc_empty(desc)) {
913 if (pdata->is_ar7240 &&
914 ag71xx_check_dma_stuck(ag, ring->buf[i].timestamp))
915 schedule_work(&ag->restart_work);
919 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
922 dev_kfree_skb_any(skb);
923 ring->buf[i].skb = NULL;
925 bytes_compl += ring->buf[i].len;
932 DBG("%s: %d packets sent out\n", ag->dev->name, sent);
934 ag->dev->stats.tx_bytes += bytes_compl;
935 ag->dev->stats.tx_packets += sent;
940 netdev_completed_queue(ag->dev, sent, bytes_compl);
941 if ((ring->curr - ring->dirty) < (ring->size * 3) / 4)
942 netif_wake_queue(ag->dev);
947 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
949 struct net_device *dev = ag->dev;
950 struct ag71xx_ring *ring = &ag->rx_ring;
951 int offset = ag71xx_buffer_offset(ag);
952 unsigned int pktlen_mask = ag->desc_pktlen_mask;
955 DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
956 dev->name, limit, ring->curr, ring->dirty);
958 while (done < limit) {
959 unsigned int i = ring->curr % ring->size;
960 struct ag71xx_desc *desc = ring->buf[i].desc;
965 if (ag71xx_desc_empty(desc))
968 if ((ring->dirty + ring->size) == ring->curr) {
973 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
975 pktlen = desc->ctrl & pktlen_mask;
976 pktlen -= ETH_FCS_LEN;
978 dma_unmap_single(&dev->dev, ring->buf[i].dma_addr,
979 ag->rx_buf_size, DMA_FROM_DEVICE);
981 dev->stats.rx_packets++;
982 dev->stats.rx_bytes += pktlen;
984 skb = build_skb(ring->buf[i].rx_buf, 0);
986 kfree(ring->buf[i].rx_buf);
990 skb_reserve(skb, offset);
991 skb_put(skb, pktlen);
993 if (ag71xx_has_ar8216(ag))
994 err = ag71xx_remove_ar8216_header(ag, skb, pktlen);
997 dev->stats.rx_dropped++;
1001 skb->ip_summed = CHECKSUM_NONE;
1002 skb->protocol = eth_type_trans(skb, dev);
1003 netif_receive_skb(skb);
1007 ring->buf[i].rx_buf = NULL;
1013 ag71xx_ring_rx_refill(ag);
1015 DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
1016 dev->name, ring->curr, ring->dirty, done);
1021 static int ag71xx_poll(struct napi_struct *napi, int limit)
1023 struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
1024 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
1025 struct net_device *dev = ag->dev;
1026 struct ag71xx_ring *rx_ring;
1027 unsigned long flags;
1033 tx_done = ag71xx_tx_packets(ag);
1035 DBG("%s: processing RX ring\n", dev->name);
1036 rx_done = ag71xx_rx_packets(ag, limit);
1038 ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done);
1040 rx_ring = &ag->rx_ring;
1041 if (rx_ring->buf[rx_ring->dirty % rx_ring->size].rx_buf == NULL)
1044 status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
1045 if (unlikely(status & RX_STATUS_OF)) {
1046 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
1047 dev->stats.rx_fifo_errors++;
1050 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
1053 if (rx_done < limit) {
1054 if (status & RX_STATUS_PR)
1057 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
1058 if (status & TX_STATUS_PS)
1061 DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n",
1062 dev->name, rx_done, tx_done, limit);
1064 napi_complete(napi);
1066 /* enable interrupts */
1067 spin_lock_irqsave(&ag->lock, flags);
1068 ag71xx_int_enable(ag, AG71XX_INT_POLL);
1069 spin_unlock_irqrestore(&ag->lock, flags);
1074 DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n",
1075 dev->name, rx_done, tx_done, limit);
1079 if (netif_msg_rx_err(ag))
1080 pr_info("%s: out of memory\n", dev->name);
1082 mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
1083 napi_complete(napi);
1087 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
1089 struct net_device *dev = dev_id;
1090 struct ag71xx *ag = netdev_priv(dev);
1093 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
1094 ag71xx_dump_intr(ag, "raw", status);
1096 if (unlikely(!status))
1099 if (unlikely(status & AG71XX_INT_ERR)) {
1100 if (status & AG71XX_INT_TX_BE) {
1101 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
1102 dev_err(&dev->dev, "TX BUS error\n");
1104 if (status & AG71XX_INT_RX_BE) {
1105 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
1106 dev_err(&dev->dev, "RX BUS error\n");
1110 if (likely(status & AG71XX_INT_POLL)) {
1111 ag71xx_int_disable(ag, AG71XX_INT_POLL);
1112 DBG("%s: enable polling mode\n", dev->name);
1113 napi_schedule(&ag->napi);
1116 ag71xx_debugfs_update_int_stats(ag, status);
1121 #ifdef CONFIG_NET_POLL_CONTROLLER
1123 * Polling 'interrupt' - used by things like netconsole to send skbs
1124 * without having to re-enable interrupts. It's not called while
1125 * the interrupt routine is executing.
1127 static void ag71xx_netpoll(struct net_device *dev)
1129 disable_irq(dev->irq);
1130 ag71xx_interrupt(dev->irq, dev);
1131 enable_irq(dev->irq);
1135 static int ag71xx_change_mtu(struct net_device *dev, int new_mtu)
1137 struct ag71xx *ag = netdev_priv(dev);
1138 unsigned int max_frame_len;
1140 max_frame_len = ag71xx_max_frame_len(new_mtu);
1141 if (new_mtu < 68 || max_frame_len > ag->max_frame_len)
1144 if (netif_running(dev))
1151 static const struct net_device_ops ag71xx_netdev_ops = {
1152 .ndo_open = ag71xx_open,
1153 .ndo_stop = ag71xx_stop,
1154 .ndo_start_xmit = ag71xx_hard_start_xmit,
1155 .ndo_do_ioctl = ag71xx_do_ioctl,
1156 .ndo_tx_timeout = ag71xx_tx_timeout,
1157 .ndo_change_mtu = ag71xx_change_mtu,
1158 .ndo_set_mac_address = eth_mac_addr,
1159 .ndo_validate_addr = eth_validate_addr,
1160 #ifdef CONFIG_NET_POLL_CONTROLLER
1161 .ndo_poll_controller = ag71xx_netpoll,
1165 static const char *ag71xx_get_phy_if_mode_name(phy_interface_t mode)
1168 case PHY_INTERFACE_MODE_MII:
1170 case PHY_INTERFACE_MODE_GMII:
1172 case PHY_INTERFACE_MODE_RMII:
1174 case PHY_INTERFACE_MODE_RGMII:
1176 case PHY_INTERFACE_MODE_SGMII:
1186 static int ag71xx_probe(struct platform_device *pdev)
1188 struct net_device *dev;
1189 struct resource *res;
1191 struct ag71xx_platform_data *pdata;
1194 pdata = pdev->dev.platform_data;
1196 dev_err(&pdev->dev, "no platform data specified\n");
1201 if (pdata->mii_bus_dev == NULL && pdata->phy_mask) {
1202 dev_err(&pdev->dev, "no MII bus device specified\n");
1207 dev = alloc_etherdev(sizeof(*ag));
1209 dev_err(&pdev->dev, "alloc_etherdev failed\n");
1214 if (!pdata->max_frame_len || !pdata->desc_pktlen_mask)
1217 SET_NETDEV_DEV(dev, &pdev->dev);
1219 ag = netdev_priv(dev);
1222 ag->msg_enable = netif_msg_init(ag71xx_msg_level,
1223 AG71XX_DEFAULT_MSG_ENABLE);
1224 spin_lock_init(&ag->lock);
1226 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
1228 dev_err(&pdev->dev, "no mac_base resource found\n");
1233 ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1);
1234 if (!ag->mac_base) {
1235 dev_err(&pdev->dev, "unable to ioremap mac_base\n");
1240 dev->irq = platform_get_irq(pdev, 0);
1241 err = request_irq(dev->irq, ag71xx_interrupt,
1245 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
1246 goto err_unmap_base;
1249 dev->base_addr = (unsigned long)ag->mac_base;
1250 dev->netdev_ops = &ag71xx_netdev_ops;
1251 dev->ethtool_ops = &ag71xx_ethtool_ops;
1253 INIT_WORK(&ag->restart_work, ag71xx_restart_work_func);
1255 init_timer(&ag->oom_timer);
1256 ag->oom_timer.data = (unsigned long) dev;
1257 ag->oom_timer.function = ag71xx_oom_timer_handler;
1259 ag->tx_ring.size = AG71XX_TX_RING_SIZE_DEFAULT;
1260 ag->rx_ring.size = AG71XX_RX_RING_SIZE_DEFAULT;
1262 ag->max_frame_len = pdata->max_frame_len;
1263 ag->desc_pktlen_mask = pdata->desc_pktlen_mask;
1266 if (!pdata->is_ar724x && !pdata->is_ar91xx) {
1267 ag->tx_ring.desc_split = AG71XX_TX_RING_SPLIT;
1268 ag->tx_ring.size *= AG71XX_TX_RING_DS_PER_PKT;
1272 ag->stop_desc = dma_alloc_coherent(NULL,
1273 sizeof(struct ag71xx_desc), &ag->stop_desc_dma, GFP_KERNEL);
1278 ag->stop_desc->data = 0;
1279 ag->stop_desc->ctrl = 0;
1280 ag->stop_desc->next = (u32) ag->stop_desc_dma;
1282 memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
1284 netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
1286 ag71xx_dump_regs(ag);
1290 ag71xx_dump_regs(ag);
1292 err = ag71xx_phy_connect(ag);
1296 err = ag71xx_debugfs_init(ag);
1298 goto err_phy_disconnect;
1300 platform_set_drvdata(pdev, dev);
1302 err = register_netdev(dev);
1304 dev_err(&pdev->dev, "unable to register net device\n");
1305 goto err_debugfs_exit;
1308 pr_info("%s: Atheros AG71xx at 0x%08lx, irq %d, mode:%s\n",
1309 dev->name, dev->base_addr, dev->irq,
1310 ag71xx_get_phy_if_mode_name(pdata->phy_if_mode));
1315 ag71xx_debugfs_exit(ag);
1317 ag71xx_phy_disconnect(ag);
1319 dma_free_coherent(NULL, sizeof(struct ag71xx_desc), ag->stop_desc,
1322 free_irq(dev->irq, dev);
1324 iounmap(ag->mac_base);
1328 platform_set_drvdata(pdev, NULL);
1332 static int ag71xx_remove(struct platform_device *pdev)
1334 struct net_device *dev = platform_get_drvdata(pdev);
1337 struct ag71xx *ag = netdev_priv(dev);
1339 ag71xx_debugfs_exit(ag);
1340 ag71xx_phy_disconnect(ag);
1341 unregister_netdev(dev);
1342 free_irq(dev->irq, dev);
1343 iounmap(ag->mac_base);
1345 platform_set_drvdata(pdev, NULL);
1351 static struct platform_driver ag71xx_driver = {
1352 .probe = ag71xx_probe,
1353 .remove = ag71xx_remove,
1355 .name = AG71XX_DRV_NAME,
1359 static int __init ag71xx_module_init(void)
1363 ret = ag71xx_debugfs_root_init();
1367 ret = ag71xx_mdio_driver_init();
1369 goto err_debugfs_exit;
1371 ret = platform_driver_register(&ag71xx_driver);
1378 ag71xx_mdio_driver_exit();
1380 ag71xx_debugfs_root_exit();
1385 static void __exit ag71xx_module_exit(void)
1387 platform_driver_unregister(&ag71xx_driver);
1388 ag71xx_mdio_driver_exit();
1389 ag71xx_debugfs_root_exit();
1392 module_init(ag71xx_module_init);
1393 module_exit(ag71xx_module_exit);
1395 MODULE_VERSION(AG71XX_DRV_VERSION);
1396 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1397 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
1398 MODULE_LICENSE("GPL v2");
1399 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);