target/linux/ar71xx/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c

   1 /*
   2  *  Atheros AR71xx built-in ethernet mac driver
   3  *
   4  *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
   5  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  *  Based on Atheros' AG7100 driver
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms of the GNU General Public License version 2 as published
  11  *  by the Free Software Foundation.
  12  */
  13
  14 #include "ag71xx.h"
  15
  16 #define AG71XX_DEFAULT_MSG_ENABLE       \
  17         (NETIF_MSG_DRV                  \
  18         | NETIF_MSG_PROBE               \
  19         | NETIF_MSG_LINK                \
  20         | NETIF_MSG_TIMER               \
  21         | NETIF_MSG_IFDOWN              \
  22         | NETIF_MSG_IFUP                \
  23         | NETIF_MSG_RX_ERR              \
  24         | NETIF_MSG_TX_ERR)
  25
  26 static int ag71xx_msg_level = -1;
  27
  28 module_param_named(msg_level, ag71xx_msg_level, int, 0);
  29 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
  30
  31 static void ag71xx_dump_dma_regs(struct ag71xx *ag)
  32 {
  33         DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
  34                 ag->dev->name,
  35                 ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
  36                 ag71xx_rr(ag, AG71XX_REG_TX_DESC),
  37                 ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
  38
  39         DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
  40                 ag->dev->name,
  41                 ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
  42                 ag71xx_rr(ag, AG71XX_REG_RX_DESC),
  43                 ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
  44 }
  45
  46 static void ag71xx_dump_regs(struct ag71xx *ag)
  47 {
  48         DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
  49                 ag->dev->name,
  50                 ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
  51                 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
  52                 ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
  53                 ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
  54                 ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
  55         DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
  56                 ag->dev->name,
  57                 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
  58                 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
  59                 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
  60         DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
  61                 ag->dev->name,
  62                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
  63                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
  64                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
  65         DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
  66                 ag->dev->name,
  67                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
  68                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
  69                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
  70 }
  71
  72 static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
  73 {
  74         DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
  75                 ag->dev->name, label, intr,
  76                 (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
  77                 (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
  78                 (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
  79                 (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
  80                 (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
  81                 (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
  82 }
  83
  84 static void ag71xx_ring_free(struct ag71xx_ring *ring)
  85 {
  86         kfree(ring->buf);
  87
  88         if (ring->descs_cpu)
  89                 dma_free_coherent(NULL, ring->size * ring->desc_size,
  90                                   ring->descs_cpu, ring->descs_dma);
  91 }
  92
  93 static int ag71xx_ring_alloc(struct ag71xx_ring *ring)
  94 {
  95         int err;
  96         int i;
  97
  98         ring->desc_size = sizeof(struct ag71xx_desc);
  99         if (ring->desc_size % cache_line_size()) {
 100                 DBG("ag71xx: ring %p, desc size %u rounded to %u\n",
 101                         ring, ring->desc_size,
 102                         roundup(ring->desc_size, cache_line_size()));
 103                 ring->desc_size = roundup(ring->desc_size, cache_line_size());
 104         }
 105
 106         ring->descs_cpu = dma_alloc_coherent(NULL, ring->size * ring->desc_size,
 107                                              &ring->descs_dma, GFP_ATOMIC);
 108         if (!ring->descs_cpu) {
 109                 err = -ENOMEM;
 110                 goto err;
 111         }
 112
 113
 114         ring->buf = kzalloc(ring->size * sizeof(*ring->buf), GFP_KERNEL);
 115         if (!ring->buf) {
 116                 err = -ENOMEM;
 117                 goto err;
 118         }
 119
 120         for (i = 0; i < ring->size; i++) {
 121                 int idx = i * ring->desc_size;
 122                 ring->buf[i].desc = (struct ag71xx_desc *)&ring->descs_cpu[idx];
 123                 DBG("ag71xx: ring %p, desc %d at %p\n",
 124                         ring, i, ring->buf[i].desc);
 125         }
 126
 127         return 0;
 128
 129 err:
 130         return err;
 131 }
 132
 133 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
 134 {
 135         struct ag71xx_ring *ring = &ag->tx_ring;
 136         struct net_device *dev = ag->dev;
 137         u32 bytes_compl = 0, pkts_compl = 0;
 138
 139         while (ring->curr != ring->dirty) {
 140                 u32 i = ring->dirty % ring->size;
 141
 142                 if (!ag71xx_desc_empty(ring->buf[i].desc)) {
 143                         ring->buf[i].desc->ctrl = 0;
 144                         dev->stats.tx_errors++;
 145                 }
 146
 147                 if (ring->buf[i].skb) {
 148                         bytes_compl += ring->buf[i].skb->len;
 149                         pkts_compl++;
 150                         dev_kfree_skb_any(ring->buf[i].skb);
 151                 }
 152                 ring->buf[i].skb = NULL;
 153                 ring->dirty++;
 154         }
 155
 156         /* flush descriptors */
 157         wmb();
 158
 159         netdev_completed_queue(dev, pkts_compl, bytes_compl);
 160 }
 161
 162 static void ag71xx_ring_tx_init(struct ag71xx *ag)
 163 {
 164         struct ag71xx_ring *ring = &ag->tx_ring;
 165         int i;
 166
 167         for (i = 0; i < ring->size; i++) {
 168                 ring->buf[i].desc->next = (u32) (ring->descs_dma +
 169                         ring->desc_size * ((i + 1) % ring->size));
 170
 171                 ring->buf[i].desc->ctrl = DESC_EMPTY;
 172                 ring->buf[i].skb = NULL;
 173         }
 174
 175         /* flush descriptors */
 176         wmb();
 177
 178         ring->curr = 0;
 179         ring->dirty = 0;
 180         netdev_reset_queue(ag->dev);
 181 }
 182
 183 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
 184 {
 185         struct ag71xx_ring *ring = &ag->rx_ring;
 186         int i;
 187
 188         if (!ring->buf)
 189                 return;
 190
 191         for (i = 0; i < ring->size; i++)
 192                 if (ring->buf[i].skb) {
 193                         dma_unmap_single(&ag->dev->dev, ring->buf[i].dma_addr,
 194                                          AG71XX_RX_PKT_SIZE, DMA_FROM_DEVICE);
 195                         kfree_skb(ring->buf[i].skb);
 196                 }
 197 }
 198
 199 struct sk_buff *ag71xx_rx_alloc(struct ag71xx *ag)
 200 {
 201         /*
 202          * On AR71xx/AR91xx packets must be 4-byte aligned.
 203          *
 204          * When using builtin AR8216 support, hardware adds a 2-byte header,
 205          * so we don't need any extra alignment in that case.
 206          */
 207         if (!ag71xx_get_pdata(ag)->is_ar724x || ag71xx_has_ar8216(ag))
 208                 return netdev_alloc_skb(ag->dev, AG71XX_RX_PKT_SIZE);
 209
 210         return netdev_alloc_skb_ip_align(ag->dev, AG71XX_RX_PKT_SIZE);
 211 }
 212
 213
 214 static int ag71xx_ring_rx_init(struct ag71xx *ag)
 215 {
 216         struct ag71xx_ring *ring = &ag->rx_ring;
 217         unsigned int i;
 218         int ret;
 219
 220         ret = 0;
 221         for (i = 0; i < ring->size; i++) {
 222                 ring->buf[i].desc->next = (u32) (ring->descs_dma +
 223                         ring->desc_size * ((i + 1) % ring->size));
 224
 225                 DBG("ag71xx: RX desc at %p, next is %08x\n",
 226                         ring->buf[i].desc,
 227                         ring->buf[i].desc->next);
 228         }
 229
 230         for (i = 0; i < ring->size; i++) {
 231                 struct sk_buff *skb;
 232                 dma_addr_t dma_addr;
 233
 234                 skb = ag71xx_rx_alloc(ag);
 235                 if (!skb) {
 236                         ret = -ENOMEM;
 237                         break;
 238                 }
 239
 240                 skb->dev = ag->dev;
 241                 dma_addr = dma_map_single(&ag->dev->dev, skb->data,
 242                                           AG71XX_RX_PKT_SIZE,
 243                                           DMA_FROM_DEVICE);
 244                 ring->buf[i].skb = skb;
 245                 ring->buf[i].dma_addr = dma_addr;
 246                 ring->buf[i].desc->data = (u32) dma_addr;
 247                 ring->buf[i].desc->ctrl = DESC_EMPTY;
 248         }
 249
 250         /* flush descriptors */
 251         wmb();
 252
 253         ring->curr = 0;
 254         ring->dirty = 0;
 255
 256         return ret;
 257 }
 258
 259 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
 260 {
 261         struct ag71xx_ring *ring = &ag->rx_ring;
 262         unsigned int count;
 263
 264         count = 0;
 265         for (; ring->curr - ring->dirty > 0; ring->dirty++) {
 266                 unsigned int i;
 267
 268                 i = ring->dirty % ring->size;
 269
 270                 if (ring->buf[i].skb == NULL) {
 271                         dma_addr_t dma_addr;
 272                         struct sk_buff *skb;
 273
 274                         skb = ag71xx_rx_alloc(ag);
 275                         if (skb == NULL)
 276                                 break;
 277
 278                         skb->dev = ag->dev;
 279
 280                         dma_addr = dma_map_single(&ag->dev->dev, skb->data,
 281                                                   AG71XX_RX_PKT_SIZE,
 282                                                   DMA_FROM_DEVICE);
 283
 284                         ring->buf[i].skb = skb;
 285                         ring->buf[i].dma_addr = dma_addr;
 286                         ring->buf[i].desc->data = (u32) dma_addr;
 287                 }
 288
 289                 ring->buf[i].desc->ctrl = DESC_EMPTY;
 290                 count++;
 291         }
 292
 293         /* flush descriptors */
 294         wmb();
 295
 296         DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
 297
 298         return count;
 299 }
 300
 301 static int ag71xx_rings_init(struct ag71xx *ag)
 302 {
 303         int ret;
 304
 305         ret = ag71xx_ring_alloc(&ag->tx_ring);
 306         if (ret)
 307                 return ret;
 308
 309         ag71xx_ring_tx_init(ag);
 310
 311         ret = ag71xx_ring_alloc(&ag->rx_ring);
 312         if (ret)
 313                 return ret;
 314
 315         ret = ag71xx_ring_rx_init(ag);
 316         return ret;
 317 }
 318
 319 static void ag71xx_rings_cleanup(struct ag71xx *ag)
 320 {
 321         ag71xx_ring_rx_clean(ag);
 322         ag71xx_ring_free(&ag->rx_ring);
 323
 324         ag71xx_ring_tx_clean(ag);
 325         netdev_reset_queue(ag->dev);
 326         ag71xx_ring_free(&ag->tx_ring);
 327 }
 328
 329 static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
 330 {
 331         switch (ag->speed) {
 332         case SPEED_1000:
 333                 return "1000";
 334         case SPEED_100:
 335                 return "100";
 336         case SPEED_10:
 337                 return "10";
 338         }
 339
 340         return "?";
 341 }
 342
 343 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
 344 {
 345         u32 t;
 346
 347         t = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16)
 348           | (((u32) mac[3]) << 8) | ((u32) mac[2]);
 349
 350         ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
 351
 352         t = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16);
 353         ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
 354 }
 355
 356 static void ag71xx_dma_reset(struct ag71xx *ag)
 357 {
 358         u32 val;
 359         int i;
 360
 361         ag71xx_dump_dma_regs(ag);
 362
 363         /* stop RX and TX */
 364         ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
 365         ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
 366
 367         /*
 368          * give the hardware some time to really stop all rx/tx activity
 369          * clearing the descriptors too early causes random memory corruption
 370          */
 371         mdelay(1);
 372
 373         /* clear descriptor addresses */
 374         ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->stop_desc_dma);
 375         ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->stop_desc_dma);
 376
 377         /* clear pending RX/TX interrupts */
 378         for (i = 0; i < 256; i++) {
 379                 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
 380                 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
 381         }
 382
 383         /* clear pending errors */
 384         ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
 385         ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
 386
 387         val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
 388         if (val)
 389                 pr_alert("%s: unable to clear DMA Rx status: %08x\n",
 390                          ag->dev->name, val);
 391
 392         val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
 393
 394         /* mask out reserved bits */
 395         val &= ~0xff000000;
 396
 397         if (val)
 398                 pr_alert("%s: unable to clear DMA Tx status: %08x\n",
 399                          ag->dev->name, val);
 400
 401         ag71xx_dump_dma_regs(ag);
 402 }
 403
 404 #define MAC_CFG1_INIT   (MAC_CFG1_RXE | MAC_CFG1_TXE | \
 405                          MAC_CFG1_SRX | MAC_CFG1_STX)
 406
 407 #define FIFO_CFG0_INIT  (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
 408
 409 #define FIFO_CFG4_INIT  (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
 410                          FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
 411                          FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
 412                          FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
 413                          FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
 414                          FIFO_CFG4_VT)
 415
 416 #define FIFO_CFG5_INIT  (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
 417                          FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
 418                          FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
 419                          FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
 420                          FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
 421                          FIFO_CFG5_17 | FIFO_CFG5_SF)
 422
 423 static void ag71xx_hw_stop(struct ag71xx *ag)
 424 {
 425         /* disable all interrupts and stop the rx/tx engine */
 426         ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
 427         ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
 428         ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
 429 }
 430
 431 static void ag71xx_hw_setup(struct ag71xx *ag)
 432 {
 433         struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
 434
 435         /* setup MAC configuration registers */
 436         ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT);
 437
 438         ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
 439                   MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
 440
 441         /* setup max frame length */
 442         ag71xx_wr(ag, AG71XX_REG_MAC_MFL, AG71XX_TX_MTU_LEN);
 443
 444         /* setup FIFO configuration registers */
 445         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
 446         if (pdata->is_ar724x) {
 447                 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, pdata->fifo_cfg1);
 448                 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, pdata->fifo_cfg2);
 449         } else {
 450                 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
 451                 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
 452         }
 453         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
 454         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
 455 }
 456
 457 static void ag71xx_hw_init(struct ag71xx *ag)
 458 {
 459         struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
 460         u32 reset_mask = pdata->reset_bit;
 461
 462         ag71xx_hw_stop(ag);
 463
 464         if (pdata->is_ar724x) {
 465                 u32 reset_phy = reset_mask;
 466
 467                 reset_phy &= AR71XX_RESET_GE0_PHY | AR71XX_RESET_GE1_PHY;
 468                 reset_mask &= ~(AR71XX_RESET_GE0_PHY | AR71XX_RESET_GE1_PHY);
 469
 470                 ath79_device_reset_set(reset_phy);
 471                 mdelay(50);
 472                 ath79_device_reset_clear(reset_phy);
 473                 mdelay(200);
 474         }
 475
 476         ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
 477         udelay(20);
 478
 479         ath79_device_reset_set(reset_mask);
 480         mdelay(100);
 481         ath79_device_reset_clear(reset_mask);
 482         mdelay(200);
 483
 484         ag71xx_hw_setup(ag);
 485
 486         ag71xx_dma_reset(ag);
 487 }
 488
 489 static void ag71xx_fast_reset(struct ag71xx *ag)
 490 {
 491         struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
 492         struct net_device *dev = ag->dev;
 493         u32 reset_mask = pdata->reset_bit;
 494         u32 rx_ds, tx_ds;
 495         u32 mii_reg;
 496
 497         reset_mask &= AR71XX_RESET_GE0_MAC | AR71XX_RESET_GE1_MAC;
 498
 499         mii_reg = ag71xx_rr(ag, AG71XX_REG_MII_CFG);
 500         rx_ds = ag71xx_rr(ag, AG71XX_REG_RX_DESC);
 501         tx_ds = ag71xx_rr(ag, AG71XX_REG_TX_DESC);
 502
 503         ath79_device_reset_set(reset_mask);
 504         udelay(10);
 505         ath79_device_reset_clear(reset_mask);
 506         udelay(10);
 507
 508         ag71xx_dma_reset(ag);
 509         ag71xx_hw_setup(ag);
 510
 511         ag71xx_wr(ag, AG71XX_REG_RX_DESC, rx_ds);
 512         ag71xx_wr(ag, AG71XX_REG_TX_DESC, tx_ds);
 513         ag71xx_wr(ag, AG71XX_REG_MII_CFG, mii_reg);
 514
 515         ag71xx_hw_set_macaddr(ag, dev->dev_addr);
 516 }
 517
 518 static void ag71xx_hw_start(struct ag71xx *ag)
 519 {
 520         /* start RX engine */
 521         ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
 522
 523         /* enable interrupts */
 524         ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
 525 }
 526
 527 void ag71xx_link_adjust(struct ag71xx *ag)
 528 {
 529         struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
 530         u32 cfg2;
 531         u32 ifctl;
 532         u32 fifo5;
 533
 534         if (!ag->link) {
 535                 ag71xx_hw_stop(ag);
 536                 netif_carrier_off(ag->dev);
 537                 if (netif_msg_link(ag))
 538                         pr_info("%s: link down\n", ag->dev->name);
 539                 return;
 540         }
 541
 542         if (pdata->is_ar724x)
 543                 ag71xx_fast_reset(ag);
 544
 545         cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
 546         cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
 547         cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
 548
 549         ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
 550         ifctl &= ~(MAC_IFCTL_SPEED);
 551
 552         fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
 553         fifo5 &= ~FIFO_CFG5_BM;
 554
 555         switch (ag->speed) {
 556         case SPEED_1000:
 557                 cfg2 |= MAC_CFG2_IF_1000;
 558                 fifo5 |= FIFO_CFG5_BM;
 559                 break;
 560         case SPEED_100:
 561                 cfg2 |= MAC_CFG2_IF_10_100;
 562                 ifctl |= MAC_IFCTL_SPEED;
 563                 break;
 564         case SPEED_10:
 565                 cfg2 |= MAC_CFG2_IF_10_100;
 566                 break;
 567         default:
 568                 BUG();
 569                 return;
 570         }
 571
 572         if (pdata->is_ar91xx)
 573                 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x00780fff);
 574         else if (pdata->is_ar724x)
 575                 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, pdata->fifo_cfg3);
 576         else
 577                 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x008001ff);
 578
 579         if (pdata->set_speed)
 580                 pdata->set_speed(ag->speed);
 581
 582         ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
 583         ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
 584         ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
 585         ag71xx_hw_start(ag);
 586
 587         netif_carrier_on(ag->dev);
 588         if (netif_msg_link(ag))
 589                 pr_info("%s: link up (%sMbps/%s duplex)\n",
 590                         ag->dev->name,
 591                         ag71xx_speed_str(ag),
 592                         (DUPLEX_FULL == ag->duplex) ? "Full" : "Half");
 593
 594         DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n",
 595                 ag->dev->name,
 596                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
 597                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
 598                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
 599
 600         DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n",
 601                 ag->dev->name,
 602                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
 603                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
 604                 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
 605
 606         DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x\n",
 607                 ag->dev->name,
 608                 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
 609                 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL));
 610 }
 611
 612 static int ag71xx_open(struct net_device *dev)
 613 {
 614         struct ag71xx *ag = netdev_priv(dev);
 615         int ret;
 616
 617         ret = ag71xx_rings_init(ag);
 618         if (ret)
 619                 goto err;
 620
 621         napi_enable(&ag->napi);
 622
 623         netif_carrier_off(dev);
 624         ag71xx_phy_start(ag);
 625
 626         ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
 627         ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
 628
 629         ag71xx_hw_set_macaddr(ag, dev->dev_addr);
 630
 631         netif_start_queue(dev);
 632
 633         return 0;
 634
 635 err:
 636         ag71xx_rings_cleanup(ag);
 637         return ret;
 638 }
 639
 640 static int ag71xx_stop(struct net_device *dev)
 641 {
 642         struct ag71xx *ag = netdev_priv(dev);
 643         unsigned long flags;
 644
 645         netif_carrier_off(dev);
 646         ag71xx_phy_stop(ag);
 647
 648         spin_lock_irqsave(&ag->lock, flags);
 649
 650         netif_stop_queue(dev);
 651
 652         ag71xx_hw_stop(ag);
 653         ag71xx_dma_reset(ag);
 654
 655         napi_disable(&ag->napi);
 656         del_timer_sync(&ag->oom_timer);
 657
 658         spin_unlock_irqrestore(&ag->lock, flags);
 659
 660         ag71xx_rings_cleanup(ag);
 661
 662         return 0;
 663 }
 664
 665 static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb,
 666                                           struct net_device *dev)
 667 {
 668         struct ag71xx *ag = netdev_priv(dev);
 669         struct ag71xx_ring *ring = &ag->tx_ring;
 670         struct ag71xx_desc *desc;
 671         dma_addr_t dma_addr;
 672         int i;
 673
 674         i = ring->curr % ring->size;
 675         desc = ring->buf[i].desc;
 676
 677         if (!ag71xx_desc_empty(desc))
 678                 goto err_drop;
 679
 680         if (ag71xx_has_ar8216(ag))
 681                 ag71xx_add_ar8216_header(ag, skb);
 682
 683         if (skb->len <= 0) {
 684                 DBG("%s: packet len is too small\n", ag->dev->name);
 685                 goto err_drop;
 686         }
 687
 688         dma_addr = dma_map_single(&dev->dev, skb->data, skb->len,
 689                                   DMA_TO_DEVICE);
 690
 691         netdev_sent_queue(dev, skb->len);
 692         ring->buf[i].skb = skb;
 693         ring->buf[i].timestamp = jiffies;
 694
 695         /* setup descriptor fields */
 696         desc->data = (u32) dma_addr;
 697         desc->ctrl = (skb->len & DESC_PKTLEN_M);
 698
 699         /* flush descriptor */
 700         wmb();
 701
 702         ring->curr++;
 703         if (ring->curr == (ring->dirty + ring->size)) {
 704                 DBG("%s: tx queue full\n", ag->dev->name);
 705                 netif_stop_queue(dev);
 706         }
 707
 708         DBG("%s: packet injected into TX queue\n", ag->dev->name);
 709
 710         /* enable TX engine */
 711         ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
 712
 713         return NETDEV_TX_OK;
 714
 715 err_drop:
 716         dev->stats.tx_dropped++;
 717
 718         dev_kfree_skb(skb);
 719         return NETDEV_TX_OK;
 720 }
 721
 722 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
 723 {
 724         struct ag71xx *ag = netdev_priv(dev);
 725         int ret;
 726
 727         switch (cmd) {
 728         case SIOCETHTOOL:
 729                 if (ag->phy_dev == NULL)
 730                         break;
 731
 732                 spin_lock_irq(&ag->lock);
 733                 ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
 734                 spin_unlock_irq(&ag->lock);
 735                 return ret;
 736
 737         case SIOCSIFHWADDR:
 738                 if (copy_from_user
 739                         (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
 740                         return -EFAULT;
 741                 return 0;
 742
 743         case SIOCGIFHWADDR:
 744                 if (copy_to_user
 745                         (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
 746                         return -EFAULT;
 747                 return 0;
 748
 749         case SIOCGMIIPHY:
 750         case SIOCGMIIREG:
 751         case SIOCSMIIREG:
 752                 if (ag->phy_dev == NULL)
 753                         break;
 754
 755                 return phy_mii_ioctl(ag->phy_dev, ifr, cmd);
 756
 757         default:
 758                 break;
 759         }
 760
 761         return -EOPNOTSUPP;
 762 }
 763
 764 static void ag71xx_oom_timer_handler(unsigned long data)
 765 {
 766         struct net_device *dev = (struct net_device *) data;
 767         struct ag71xx *ag = netdev_priv(dev);
 768
 769         napi_schedule(&ag->napi);
 770 }
 771
 772 static void ag71xx_tx_timeout(struct net_device *dev)
 773 {
 774         struct ag71xx *ag = netdev_priv(dev);
 775
 776         if (netif_msg_tx_err(ag))
 777                 pr_info("%s: tx timeout\n", ag->dev->name);
 778
 779         schedule_work(&ag->restart_work);
 780 }
 781
 782 static void ag71xx_restart_work_func(struct work_struct *work)
 783 {
 784         struct ag71xx *ag = container_of(work, struct ag71xx, restart_work);
 785
 786         if (ag71xx_get_pdata(ag)->is_ar724x) {
 787                 ag->link = 0;
 788                 ag71xx_link_adjust(ag);
 789                 return;
 790         }
 791
 792         ag71xx_stop(ag->dev);
 793         ag71xx_open(ag->dev);
 794 }
 795
 796 static bool ag71xx_check_dma_stuck(struct ag71xx *ag, unsigned long timestamp)
 797 {
 798         u32 rx_sm, tx_sm, rx_fd;
 799
 800         if (likely(time_before(jiffies, timestamp + HZ/10)))
 801                 return false;
 802
 803         if (!netif_carrier_ok(ag->dev))
 804                 return false;
 805
 806         rx_sm = ag71xx_rr(ag, AG71XX_REG_RX_SM);
 807         if ((rx_sm & 0x7) == 0x3 && ((rx_sm >> 4) & 0x7) == 0x6)
 808                 return true;
 809
 810         tx_sm = ag71xx_rr(ag, AG71XX_REG_TX_SM);
 811         rx_fd = ag71xx_rr(ag, AG71XX_REG_FIFO_DEPTH);
 812         if (((tx_sm >> 4) & 0x7) == 0 && ((rx_sm & 0x7) == 0) &&
 813             ((rx_sm >> 4) & 0x7) == 0 && rx_fd == 0)
 814                 return true;
 815
 816         return false;
 817 }
 818
 819 static int ag71xx_tx_packets(struct ag71xx *ag)
 820 {
 821         struct ag71xx_ring *ring = &ag->tx_ring;
 822         struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
 823         int sent = 0;
 824         int bytes_compl = 0;
 825
 826         DBG("%s: processing TX ring\n", ag->dev->name);
 827
 828         while (ring->dirty != ring->curr) {
 829                 unsigned int i = ring->dirty % ring->size;
 830                 struct ag71xx_desc *desc = ring->buf[i].desc;
 831                 struct sk_buff *skb = ring->buf[i].skb;
 832
 833                 if (!ag71xx_desc_empty(desc)) {
 834                         if (pdata->is_ar7240 &&
 835                             ag71xx_check_dma_stuck(ag, ring->buf[i].timestamp))
 836                                 schedule_work(&ag->restart_work);
 837                         break;
 838                 }
 839
 840                 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
 841
 842                 bytes_compl += skb->len;
 843                 ag->dev->stats.tx_bytes += skb->len;
 844                 ag->dev->stats.tx_packets++;
 845
 846                 dev_kfree_skb_any(skb);
 847                 ring->buf[i].skb = NULL;
 848
 849                 ring->dirty++;
 850                 sent++;
 851         }
 852
 853         DBG("%s: %d packets sent out\n", ag->dev->name, sent);
 854
 855         netdev_completed_queue(ag->dev, sent, bytes_compl);
 856         if ((ring->curr - ring->dirty) < (ring->size * 3) / 4)
 857                 netif_wake_queue(ag->dev);
 858
 859         return sent;
 860 }
 861
 862 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
 863 {
 864         struct net_device *dev = ag->dev;
 865         struct ag71xx_ring *ring = &ag->rx_ring;
 866         int done = 0;
 867
 868         DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
 869                         dev->name, limit, ring->curr, ring->dirty);
 870
 871         while (done < limit) {
 872                 unsigned int i = ring->curr % ring->size;
 873                 struct ag71xx_desc *desc = ring->buf[i].desc;
 874                 struct sk_buff *skb;
 875                 int pktlen;
 876                 int err = 0;
 877
 878                 if (ag71xx_desc_empty(desc))
 879                         break;
 880
 881                 if ((ring->dirty + ring->size) == ring->curr) {
 882                         ag71xx_assert(0);
 883                         break;
 884                 }
 885
 886                 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
 887
 888                 skb = ring->buf[i].skb;
 889                 pktlen = ag71xx_desc_pktlen(desc);
 890                 pktlen -= ETH_FCS_LEN;
 891
 892                 dma_unmap_single(&dev->dev, ring->buf[i].dma_addr,
 893                                  AG71XX_RX_PKT_SIZE, DMA_FROM_DEVICE);
 894
 895                 dev->last_rx = jiffies;
 896                 dev->stats.rx_packets++;
 897                 dev->stats.rx_bytes += pktlen;
 898
 899                 skb_put(skb, pktlen);
 900                 if (ag71xx_has_ar8216(ag))
 901                         err = ag71xx_remove_ar8216_header(ag, skb, pktlen);
 902
 903                 if (err) {
 904                         dev->stats.rx_dropped++;
 905                         kfree_skb(skb);
 906                 } else {
 907                         skb->dev = dev;
 908                         skb->ip_summed = CHECKSUM_NONE;
 909                         skb->protocol = eth_type_trans(skb, dev);
 910                         netif_receive_skb(skb);
 911                 }
 912
 913                 ring->buf[i].skb = NULL;
 914                 done++;
 915
 916                 ring->curr++;
 917         }
 918
 919         ag71xx_ring_rx_refill(ag);
 920
 921         DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
 922                 dev->name, ring->curr, ring->dirty, done);
 923
 924         return done;
 925 }
 926
 927 static int ag71xx_poll(struct napi_struct *napi, int limit)
 928 {
 929         struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
 930         struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
 931         struct net_device *dev = ag->dev;
 932         struct ag71xx_ring *rx_ring;
 933         unsigned long flags;
 934         u32 status;
 935         int tx_done;
 936         int rx_done;
 937
 938         pdata->ddr_flush();
 939         tx_done = ag71xx_tx_packets(ag);
 940
 941         DBG("%s: processing RX ring\n", dev->name);
 942         rx_done = ag71xx_rx_packets(ag, limit);
 943
 944         ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done);
 945
 946         rx_ring = &ag->rx_ring;
 947         if (rx_ring->buf[rx_ring->dirty % rx_ring->size].skb == NULL)
 948                 goto oom;
 949
 950         status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
 951         if (unlikely(status & RX_STATUS_OF)) {
 952                 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
 953                 dev->stats.rx_fifo_errors++;
 954
 955                 /* restart RX */
 956                 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
 957         }
 958
 959         if (rx_done < limit) {
 960                 if (status & RX_STATUS_PR)
 961                         goto more;
 962
 963                 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
 964                 if (status & TX_STATUS_PS)
 965                         goto more;
 966
 967                 DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n",
 968                         dev->name, rx_done, tx_done, limit);
 969
 970                 napi_complete(napi);
 971
 972                 /* enable interrupts */
 973                 spin_lock_irqsave(&ag->lock, flags);
 974                 ag71xx_int_enable(ag, AG71XX_INT_POLL);
 975                 spin_unlock_irqrestore(&ag->lock, flags);
 976                 return rx_done;
 977         }
 978
 979 more:
 980         DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n",
 981                         dev->name, rx_done, tx_done, limit);
 982         return rx_done;
 983
 984 oom:
 985         if (netif_msg_rx_err(ag))
 986                 pr_info("%s: out of memory\n", dev->name);
 987
 988         mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
 989         napi_complete(napi);
 990         return 0;
 991 }
 992
 993 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
 994 {
 995         struct net_device *dev = dev_id;
 996         struct ag71xx *ag = netdev_priv(dev);
 997         u32 status;
 998
 999         status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
1000         ag71xx_dump_intr(ag, "raw", status);
1001
1002         if (unlikely(!status))
1003                 return IRQ_NONE;
1004
1005         if (unlikely(status & AG71XX_INT_ERR)) {
1006                 if (status & AG71XX_INT_TX_BE) {
1007                         ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
1008                         dev_err(&dev->dev, "TX BUS error\n");
1009                 }
1010                 if (status & AG71XX_INT_RX_BE) {
1011                         ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
1012                         dev_err(&dev->dev, "RX BUS error\n");
1013                 }
1014         }
1015
1016         if (likely(status & AG71XX_INT_POLL)) {
1017                 ag71xx_int_disable(ag, AG71XX_INT_POLL);
1018                 DBG("%s: enable polling mode\n", dev->name);
1019                 napi_schedule(&ag->napi);
1020         }
1021
1022         ag71xx_debugfs_update_int_stats(ag, status);
1023
1024         return IRQ_HANDLED;
1025 }
1026
1027 #ifdef CONFIG_NET_POLL_CONTROLLER
1028 /*
1029  * Polling 'interrupt' - used by things like netconsole to send skbs
1030  * without having to re-enable interrupts. It's not called while
1031  * the interrupt routine is executing.
1032  */
1033 static void ag71xx_netpoll(struct net_device *dev)
1034 {
1035         disable_irq(dev->irq);
1036         ag71xx_interrupt(dev->irq, dev);
1037         enable_irq(dev->irq);
1038 }
1039 #endif
1040
1041 static const struct net_device_ops ag71xx_netdev_ops = {
1042         .ndo_open               = ag71xx_open,
1043         .ndo_stop               = ag71xx_stop,
1044         .ndo_start_xmit         = ag71xx_hard_start_xmit,
1045         .ndo_do_ioctl           = ag71xx_do_ioctl,
1046         .ndo_tx_timeout         = ag71xx_tx_timeout,
1047         .ndo_change_mtu         = eth_change_mtu,
1048         .ndo_set_mac_address    = eth_mac_addr,
1049         .ndo_validate_addr      = eth_validate_addr,
1050 #ifdef CONFIG_NET_POLL_CONTROLLER
1051         .ndo_poll_controller    = ag71xx_netpoll,
1052 #endif
1053 };
1054
1055 static int __devinit ag71xx_probe(struct platform_device *pdev)
1056 {
1057         struct net_device *dev;
1058         struct resource *res;
1059         struct ag71xx *ag;
1060         struct ag71xx_platform_data *pdata;
1061         int err;
1062
1063         pdata = pdev->dev.platform_data;
1064         if (!pdata) {
1065                 dev_err(&pdev->dev, "no platform data specified\n");
1066                 err = -ENXIO;
1067                 goto err_out;
1068         }
1069
1070         if (pdata->mii_bus_dev == NULL) {
1071                 dev_err(&pdev->dev, "no MII bus device specified\n");
1072                 err = -EINVAL;
1073                 goto err_out;
1074         }
1075
1076         dev = alloc_etherdev(sizeof(*ag));
1077         if (!dev) {
1078                 dev_err(&pdev->dev, "alloc_etherdev failed\n");
1079                 err = -ENOMEM;
1080                 goto err_out;
1081         }
1082
1083         SET_NETDEV_DEV(dev, &pdev->dev);
1084
1085         ag = netdev_priv(dev);
1086         ag->pdev = pdev;
1087         ag->dev = dev;
1088         ag->msg_enable = netif_msg_init(ag71xx_msg_level,
1089                                         AG71XX_DEFAULT_MSG_ENABLE);
1090         spin_lock_init(&ag->lock);
1091
1092         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
1093         if (!res) {
1094                 dev_err(&pdev->dev, "no mac_base resource found\n");
1095                 err = -ENXIO;
1096                 goto err_out;
1097         }
1098
1099         ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1);
1100         if (!ag->mac_base) {
1101                 dev_err(&pdev->dev, "unable to ioremap mac_base\n");
1102                 err = -ENOMEM;
1103                 goto err_free_dev;
1104         }
1105
1106         dev->irq = platform_get_irq(pdev, 0);
1107         err = request_irq(dev->irq, ag71xx_interrupt,
1108                           IRQF_DISABLED,
1109                           dev->name, dev);
1110         if (err) {
1111                 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
1112                 goto err_unmap_base;
1113         }
1114
1115         dev->base_addr = (unsigned long)ag->mac_base;
1116         dev->netdev_ops = &ag71xx_netdev_ops;
1117         dev->ethtool_ops = &ag71xx_ethtool_ops;
1118
1119         INIT_WORK(&ag->restart_work, ag71xx_restart_work_func);
1120
1121         init_timer(&ag->oom_timer);
1122         ag->oom_timer.data = (unsigned long) dev;
1123         ag->oom_timer.function = ag71xx_oom_timer_handler;
1124
1125         ag->tx_ring.size = AG71XX_TX_RING_SIZE_DEFAULT;
1126         ag->rx_ring.size = AG71XX_RX_RING_SIZE_DEFAULT;
1127
1128         ag->stop_desc = dma_alloc_coherent(NULL,
1129                 sizeof(struct ag71xx_desc), &ag->stop_desc_dma, GFP_KERNEL);
1130
1131         if (!ag->stop_desc)
1132                 goto err_free_irq;
1133
1134         ag->stop_desc->data = 0;
1135         ag->stop_desc->ctrl = 0;
1136         ag->stop_desc->next = (u32) ag->stop_desc_dma;
1137
1138         memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
1139
1140         netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
1141
1142         err = register_netdev(dev);
1143         if (err) {
1144                 dev_err(&pdev->dev, "unable to register net device\n");
1145                 goto err_free_desc;
1146         }
1147
1148         pr_info("%s: Atheros AG71xx at 0x%08lx, irq %d\n",
1149                 dev->name, dev->base_addr, dev->irq);
1150
1151         ag71xx_dump_regs(ag);
1152
1153         ag71xx_hw_init(ag);
1154
1155         ag71xx_dump_regs(ag);
1156
1157         err = ag71xx_phy_connect(ag);
1158         if (err)
1159                 goto err_unregister_netdev;
1160
1161         err = ag71xx_debugfs_init(ag);
1162         if (err)
1163                 goto err_phy_disconnect;
1164
1165         platform_set_drvdata(pdev, dev);
1166
1167         return 0;
1168
1169 err_phy_disconnect:
1170         ag71xx_phy_disconnect(ag);
1171 err_unregister_netdev:
1172         unregister_netdev(dev);
1173 err_free_desc:
1174         dma_free_coherent(NULL, sizeof(struct ag71xx_desc), ag->stop_desc,
1175                           ag->stop_desc_dma);
1176 err_free_irq:
1177         free_irq(dev->irq, dev);
1178 err_unmap_base:
1179         iounmap(ag->mac_base);
1180 err_free_dev:
1181         kfree(dev);
1182 err_out:
1183         platform_set_drvdata(pdev, NULL);
1184         return err;
1185 }
1186
1187 static int __devexit ag71xx_remove(struct platform_device *pdev)
1188 {
1189         struct net_device *dev = platform_get_drvdata(pdev);
1190
1191         if (dev) {
1192                 struct ag71xx *ag = netdev_priv(dev);
1193
1194                 ag71xx_debugfs_exit(ag);
1195                 ag71xx_phy_disconnect(ag);
1196                 unregister_netdev(dev);
1197                 free_irq(dev->irq, dev);
1198                 iounmap(ag->mac_base);
1199                 kfree(dev);
1200                 platform_set_drvdata(pdev, NULL);
1201         }
1202
1203         return 0;
1204 }
1205
1206 static struct platform_driver ag71xx_driver = {
1207         .probe          = ag71xx_probe,
1208         .remove         = __exit_p(ag71xx_remove),
1209         .driver = {
1210                 .name   = AG71XX_DRV_NAME,
1211         }
1212 };
1213
1214 static int __init ag71xx_module_init(void)
1215 {
1216         int ret;
1217
1218         ret = ag71xx_debugfs_root_init();
1219         if (ret)
1220                 goto err_out;
1221
1222         ret = ag71xx_mdio_driver_init();
1223         if (ret)
1224                 goto err_debugfs_exit;
1225
1226         ret = platform_driver_register(&ag71xx_driver);
1227         if (ret)
1228                 goto err_mdio_exit;
1229
1230         return 0;
1231
1232 err_mdio_exit:
1233         ag71xx_mdio_driver_exit();
1234 err_debugfs_exit:
1235         ag71xx_debugfs_root_exit();
1236 err_out:
1237         return ret;
1238 }
1239
1240 static void __exit ag71xx_module_exit(void)
1241 {
1242         platform_driver_unregister(&ag71xx_driver);
1243         ag71xx_mdio_driver_exit();
1244         ag71xx_debugfs_root_exit();
1245 }
1246
1247 module_init(ag71xx_module_init);
1248 module_exit(ag71xx_module_exit);
1249
1250 MODULE_VERSION(AG71XX_DRV_VERSION);
1251 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1252 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
1253 MODULE_LICENSE("GPL v2");
1254 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);