2 * Atheros AR71xx built-in ethernet mac driver
4 * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 * Based on Atheros' AG7100 driver
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
16 static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
31 #define PLL_VAL_1000 0x00110000
32 #define PLL_VAL_100 0x00001099
33 #define PLL_VAL_10 0x00991099
35 #define PLL_VAL_1000 0x01111000
36 #define PLL_VAL_100 0x09991000
37 #define PLL_VAL_10 0x09991999
40 static void ag71xx_phy_link_update(struct ag71xx *ag)
42 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
50 netif_carrier_off(ag->dev);
51 if (netif_msg_link(ag))
52 printk(KERN_INFO "%s: link down\n", ag->dev->name);
56 cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
57 cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
58 cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
60 ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
61 ifctl &= ~(MAC_IFCTL_SPEED);
63 fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
64 fifo5 &= ~FIFO_CFG5_BM;
68 mii_speed = MII_CTRL_SPEED_1000;
69 cfg2 |= MAC_CFG2_IF_1000;
71 fifo5 |= FIFO_CFG5_BM;
74 mii_speed = MII_CTRL_SPEED_100;
75 cfg2 |= MAC_CFG2_IF_10_100;
76 ifctl |= MAC_IFCTL_SPEED;
80 mii_speed = MII_CTRL_SPEED_10;
81 cfg2 |= MAC_CFG2_IF_10_100;
89 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x008001ff);
91 ag71xx_mii_ctrl_set_speed(ag, mii_speed);
93 ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
94 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
95 ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
97 netif_carrier_on(ag->dev);
98 if (netif_msg_link(ag))
99 printk(KERN_INFO "%s: link up (%sMbps/%s duplex)\n",
101 ag71xx_speed_str(ag),
102 (DUPLEX_FULL == ag->duplex) ? "Full" : "Half");
104 DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n",
106 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
107 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
108 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
110 DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n",
112 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
113 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
114 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
116 DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x, mii_ctrl=%#x\n",
118 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
119 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
120 ag71xx_mii_ctrl_rr(ag));
123 static void ag71xx_phy_link_adjust(struct net_device *dev)
125 struct ag71xx *ag = netdev_priv(dev);
126 struct phy_device *phydev = ag->phy_dev;
128 int status_change = 0;
130 spin_lock_irqsave(&ag->lock, flags);
133 if (ag->duplex != phydev->duplex
134 || ag->speed != phydev->speed) {
139 if (phydev->link != ag->link) {
146 ag->link = phydev->link;
147 ag->duplex = phydev->duplex;
148 ag->speed = phydev->speed;
151 ag71xx_phy_link_update(ag);
153 spin_unlock_irqrestore(&ag->lock, flags);
156 void ag71xx_phy_start(struct ag71xx *ag)
159 phy_start(ag->phy_dev);
161 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
163 ag->duplex = pdata->duplex;
164 ag->speed = pdata->speed;
166 ag71xx_phy_link_update(ag);
170 void ag71xx_phy_stop(struct ag71xx *ag)
173 phy_stop(ag->phy_dev);
178 ag71xx_phy_link_update(ag);
182 int ag71xx_phy_connect(struct ag71xx *ag)
184 struct net_device *dev = ag->dev;
185 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
186 struct phy_device *phydev = NULL;
190 if (ag->mii_bus && pdata->phy_mask) {
191 /* TODO: use mutex of the mdio bus? */
192 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
193 if (!(pdata->phy_mask & (1 << phy_addr)))
196 if (ag->mii_bus->phy_map[phy_addr] == NULL)
199 DBG("%s: PHY found at %s, uid=%08x\n",
201 ag->mii_bus->phy_map[phy_addr]->dev.bus_id,
202 ag->mii_bus->phy_map[phy_addr]->phy_id);
205 phydev = ag->mii_bus->phy_map[phy_addr];
213 ag->phy_dev = phy_connect(dev, phydev->dev.bus_id,
214 &ag71xx_phy_link_adjust, 0, pdata->phy_if_mode);
216 if (IS_ERR(ag->phy_dev)) {
217 printk(KERN_ERR "%s: could not connect to PHY at %s\n",
218 dev->name, phydev->dev.bus_id);
219 return PTR_ERR(ag->phy_dev);
222 /* mask with MAC supported features */
224 phydev->supported &= PHY_GBIT_FEATURES;
226 phydev->supported &= PHY_BASIC_FEATURES;
228 phydev->advertising = phydev->supported;
230 printk(KERN_DEBUG "%s: connected to PHY at %s "
231 "[uid=%08x, driver=%s]\n",
232 dev->name, phydev->dev.bus_id,
233 phydev->phy_id, phydev->drv->name);
241 switch (pdata->speed) {
247 printk(KERN_ERR "%s: invalid speed specified\n",
253 printk(KERN_DEBUG "%s: connected to %d PHYs\n",
254 dev->name, phy_count);
261 void ag71xx_phy_disconnect(struct ag71xx *ag)
264 phy_disconnect(ag->phy_dev);