2 * Atheros AR71xx built-in ethernet mac driver
4 * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 * Based on Atheros' AG7100 driver
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
16 #define PLL_SEC_CONFIG 0x18050004
17 #define PLL_ETH0_INT_CLOCK 0x18050010
18 #define PLL_ETH1_INT_CLOCK 0x18050014
19 #define PLL_ETH_EXT_CLOCK 0x18050018
21 #define ag71xx_pll_shift(_ag) (((_ag)->pdev->id) ? 19 : 17)
22 #define ag71xx_pll_offset(_ag) (((_ag)->pdev->id) ? PLL_ETH1_INT_CLOCK \
25 static void ag71xx_set_pll(struct ag71xx *ag, u32 pll_val)
27 void __iomem *pll_reg = ioremap_nocache(ag71xx_pll_offset(ag), 4);
28 void __iomem *pll_cfg = ioremap_nocache(PLL_SEC_CONFIG, 4);
32 s = ag71xx_pll_shift(ag);
34 t = __raw_readl(pll_cfg);
37 __raw_writel(t, pll_cfg);
40 __raw_writel(pll_val, pll_reg);
43 __raw_writel(t, pll_cfg);
47 __raw_writel(t, pll_cfg);
49 DBG("%s: pll_reg %#x: %#x\n", ag->dev->name,
50 (unsigned int)pll_reg, __raw_readl(pll_reg));
56 static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
71 #define PLL_VAL_1000 0x00110000
72 #define PLL_VAL_100 0x00001099
73 #define PLL_VAL_10 0x00991099
75 #define PLL_VAL_1000 0x01111000
76 #define PLL_VAL_100 0x09991000
77 #define PLL_VAL_10 0x09991999
80 static void ag71xx_phy_link_update(struct ag71xx *ag)
89 netif_carrier_off(ag->dev);
90 printk(KERN_INFO "%s: link down\n", ag->dev->name);
94 cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
95 cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
96 cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
98 ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
99 ifctl &= ~(MAC_IFCTL_SPEED);
101 fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
102 fifo5 &= ~FIFO_CFG5_BYTE_PER_CLK;
106 mii_speed = MII_CTRL_SPEED_1000;
107 cfg2 |= MAC_CFG2_IF_1000;
109 fifo5 |= FIFO_CFG5_BYTE_PER_CLK;
112 mii_speed = MII_CTRL_SPEED_100;
113 cfg2 |= MAC_CFG2_IF_10_100;
114 ifctl |= MAC_IFCTL_SPEED;
118 mii_speed = MII_CTRL_SPEED_10;
119 cfg2 |= MAC_CFG2_IF_10_100;
127 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x008001ff);
128 ag71xx_set_pll(ag, pll);
129 ag71xx_mii_ctrl_set_speed(ag, mii_speed);
131 ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
132 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
133 ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
135 netif_carrier_on(ag->dev);
136 printk(KERN_INFO "%s: link up (%sMbps/%s duplex)\n",
138 ag71xx_speed_str(ag),
139 (DUPLEX_FULL == ag->duplex) ? "Full" : "Half");
141 DBG("%s: fifo1=%#x, fifo2=%#x, fifo3=%#x, fifo4=%#x, fifo5=%#x\n",
143 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
144 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2),
145 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
146 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
147 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
149 DBG("%s: mac_cfg2=%#x, ifctl=%#x, mii_ctrl=%#x\n",
151 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
152 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
153 ag71xx_mii_ctrl_rr(ag));
156 static void ag71xx_phy_link_adjust(struct net_device *dev)
158 struct ag71xx *ag = netdev_priv(dev);
159 struct phy_device *phydev = ag->phy_dev;
161 int status_change = 0;
163 spin_lock_irqsave(&ag->lock, flags);
166 if (ag->duplex != phydev->duplex
167 || ag->speed != phydev->speed) {
172 if (phydev->link != ag->link) {
179 ag->link = phydev->link;
180 ag->duplex = phydev->duplex;
181 ag->speed = phydev->speed;
184 ag71xx_phy_link_update(ag);
186 spin_unlock_irqrestore(&ag->lock, flags);
189 void ag71xx_phy_start(struct ag71xx *ag)
192 phy_start(ag->phy_dev);
194 ag->duplex = DUPLEX_FULL;
195 ag->speed = SPEED_100;
197 ag71xx_phy_link_update(ag);
201 void ag71xx_phy_stop(struct ag71xx *ag)
204 phy_stop(ag->phy_dev);
209 ag71xx_phy_link_update(ag);
213 int ag71xx_phy_connect(struct ag71xx *ag)
215 struct net_device *dev = ag->dev;
216 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
217 struct phy_device *phydev = NULL;
222 /* TODO: use mutex of the mdio bus */
223 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
224 if (!(pdata->phy_mask & (1 << phy_addr)))
227 if (ag->mii_bus->phy_map[phy_addr] == NULL)
230 DBG("%s: PHY found at %s, uid=%08x\n",
232 ag->mii_bus->phy_map[phy_addr]->dev.bus_id,
233 ag->mii_bus->phy_map[phy_addr]->phy_id);
236 phydev = ag->mii_bus->phy_map[phy_addr];
244 printk(KERN_ERR "%s: no PHY found\n", dev->name);
247 ag->phy_dev = phy_connect(dev, phydev->dev.bus_id,
248 &ag71xx_phy_link_adjust, 0, pdata->phy_if_mode);
250 if (IS_ERR(ag->phy_dev)) {
251 printk(KERN_ERR "%s: could not connect to PHY at %s\n",
252 dev->name, phydev->dev.bus_id);
253 return PTR_ERR(ag->phy_dev);
256 /* mask with MAC supported features */
257 phydev->supported &= (SUPPORTED_10baseT_Half
258 | SUPPORTED_10baseT_Full
259 | SUPPORTED_100baseT_Half
260 | SUPPORTED_100baseT_Full
265 phydev->advertising = phydev->supported;
267 printk(KERN_DEBUG "%s: connected to PHY at %s "
268 "[uid=%08x, driver=%s]\n",
269 dev->name, phydev->dev.bus_id,
270 phydev->phy_id, phydev->drv->name);
278 printk(KERN_DEBUG "%s: connected to multiple PHYs (%d)\n",
279 dev->name, phy_count);
286 void ag71xx_phy_disconnect(struct ag71xx *ag)
289 phy_disconnect(ag->phy_dev);