2 * Atheros AR71xx built-in ethernet mac driver
4 * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 * Based on Atheros' AG7100 driver
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
16 #define PLL_SEC_CONFIG 0x18050004
17 #define PLL_ETH0_INT_CLOCK 0x18050010
18 #define PLL_ETH1_INT_CLOCK 0x18050014
19 #define PLL_ETH_EXT_CLOCK 0x18050018
21 #define ag71xx_pll_shift(_ag) (((_ag)->pdev->id) ? 19 : 17)
22 #define ag71xx_pll_offset(_ag) (((_ag)->pdev->id) ? PLL_ETH1_INT_CLOCK \
25 static void ag71xx_set_pll(struct ag71xx *ag, u32 pll_val)
27 void __iomem *pll_reg = ioremap_nocache(ag71xx_pll_offset(ag), 4);
28 void __iomem *pll_cfg = ioremap_nocache(PLL_SEC_CONFIG, 4);
32 s = ag71xx_pll_shift(ag);
34 t = __raw_readl(pll_cfg);
37 __raw_writel(t, pll_cfg);
40 __raw_writel(pll_val, pll_reg);
43 __raw_writel(t, pll_cfg);
47 __raw_writel(t, pll_cfg);
49 DBG("%s: pll_reg %#x: %#x\n", ag->dev->name,
50 (unsigned int)pll_reg, __raw_readl(pll_reg));
56 static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
71 #define PLL_VAL_1000 0x00110000
72 #define PLL_VAL_100 0x00001099
73 #define PLL_VAL_10 0x00991099
75 #define PLL_VAL_1000 0x01111000
76 #define PLL_VAL_100 0x09991000
77 #define PLL_VAL_10 0x09991999
80 static void ag71xx_phy_link_update(struct ag71xx *ag)
89 netif_carrier_off(ag->dev);
90 if (netif_msg_link(ag))
91 printk(KERN_INFO "%s: link down\n", ag->dev->name);
95 cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
96 cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
97 cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
99 ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
100 ifctl &= ~(MAC_IFCTL_SPEED);
102 fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
103 fifo5 &= ~FIFO_CFG5_BM;
107 mii_speed = MII_CTRL_SPEED_1000;
108 cfg2 |= MAC_CFG2_IF_1000;
110 fifo5 |= FIFO_CFG5_BM;
113 mii_speed = MII_CTRL_SPEED_100;
114 cfg2 |= MAC_CFG2_IF_10_100;
115 ifctl |= MAC_IFCTL_SPEED;
119 mii_speed = MII_CTRL_SPEED_10;
120 cfg2 |= MAC_CFG2_IF_10_100;
128 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x008001ff);
129 ag71xx_set_pll(ag, pll);
130 ag71xx_mii_ctrl_set_speed(ag, mii_speed);
132 ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
133 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
134 ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
136 netif_carrier_on(ag->dev);
137 if (netif_msg_link(ag))
138 printk(KERN_INFO "%s: link up (%sMbps/%s duplex)\n",
140 ag71xx_speed_str(ag),
141 (DUPLEX_FULL == ag->duplex) ? "Full" : "Half");
143 DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n",
145 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
146 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
147 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
149 DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n",
151 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
152 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
153 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
155 DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x, mii_ctrl=%#x\n",
157 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
158 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
159 ag71xx_mii_ctrl_rr(ag));
162 static void ag71xx_phy_link_adjust(struct net_device *dev)
164 struct ag71xx *ag = netdev_priv(dev);
165 struct phy_device *phydev = ag->phy_dev;
167 int status_change = 0;
169 spin_lock_irqsave(&ag->lock, flags);
172 if (ag->duplex != phydev->duplex
173 || ag->speed != phydev->speed) {
178 if (phydev->link != ag->link) {
185 ag->link = phydev->link;
186 ag->duplex = phydev->duplex;
187 ag->speed = phydev->speed;
190 ag71xx_phy_link_update(ag);
192 spin_unlock_irqrestore(&ag->lock, flags);
195 void ag71xx_phy_start(struct ag71xx *ag)
198 phy_start(ag->phy_dev);
200 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
202 ag->duplex = pdata->duplex;
203 ag->speed = pdata->speed;
205 ag71xx_phy_link_update(ag);
209 void ag71xx_phy_stop(struct ag71xx *ag)
212 phy_stop(ag->phy_dev);
217 ag71xx_phy_link_update(ag);
221 int ag71xx_phy_connect(struct ag71xx *ag)
223 struct net_device *dev = ag->dev;
224 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
225 struct phy_device *phydev = NULL;
229 if (ag->mii_bus && pdata->phy_mask) {
230 /* TODO: use mutex of the mdio bus? */
231 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
232 if (!(pdata->phy_mask & (1 << phy_addr)))
235 if (ag->mii_bus->phy_map[phy_addr] == NULL)
238 DBG("%s: PHY found at %s, uid=%08x\n",
240 ag->mii_bus->phy_map[phy_addr]->dev.bus_id,
241 ag->mii_bus->phy_map[phy_addr]->phy_id);
244 phydev = ag->mii_bus->phy_map[phy_addr];
252 ag->phy_dev = phy_connect(dev, phydev->dev.bus_id,
253 &ag71xx_phy_link_adjust, 0, pdata->phy_if_mode);
255 if (IS_ERR(ag->phy_dev)) {
256 printk(KERN_ERR "%s: could not connect to PHY at %s\n",
257 dev->name, phydev->dev.bus_id);
258 return PTR_ERR(ag->phy_dev);
261 /* mask with MAC supported features */
263 phydev->supported &= PHY_GBIT_FEATURES;
265 phydev->supported &= PHY_BASIC_FEATURES;
267 phydev->advertising = phydev->supported;
269 printk(KERN_DEBUG "%s: connected to PHY at %s "
270 "[uid=%08x, driver=%s]\n",
271 dev->name, phydev->dev.bus_id,
272 phydev->phy_id, phydev->drv->name);
280 switch (pdata->speed) {
286 printk(KERN_ERR "%s: invalid speed specified\n",
292 printk(KERN_DEBUG "%s: connected to %d PHYs\n",
293 dev->name, phy_count);
300 void ag71xx_phy_disconnect(struct ag71xx *ag)
303 phy_disconnect(ag->phy_dev);