2 * Atheros AR71xx built-in ethernet mac driver
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 * Based on Atheros' AG7100 driver
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
16 #define AG71XX_DEFAULT_MSG_ENABLE \
26 static int ag71xx_msg_level = -1;
28 module_param_named(msg_level, ag71xx_msg_level, int, 0);
29 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
31 static void ag71xx_dump_dma_regs(struct ag71xx *ag)
33 DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
35 ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
36 ag71xx_rr(ag, AG71XX_REG_TX_DESC),
37 ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
39 DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
41 ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
42 ag71xx_rr(ag, AG71XX_REG_RX_DESC),
43 ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
46 static void ag71xx_dump_regs(struct ag71xx *ag)
48 DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
50 ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
51 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
52 ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
53 ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
54 ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
55 DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
57 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
58 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
59 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
60 DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
62 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
63 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
64 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
65 DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
67 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
68 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
69 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
72 static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
74 DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
75 ag->dev->name, label, intr,
76 (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
77 (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
78 (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
79 (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
80 (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
81 (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
84 static void ag71xx_ring_free(struct ag71xx_ring *ring)
89 dma_free_coherent(NULL, ring->size * ring->desc_size,
90 ring->descs_cpu, ring->descs_dma);
93 static int ag71xx_ring_alloc(struct ag71xx_ring *ring)
98 ring->desc_size = sizeof(struct ag71xx_desc);
99 if (ring->desc_size % cache_line_size()) {
100 DBG("ag71xx: ring %p, desc size %u rounded to %u\n",
101 ring, ring->desc_size,
102 roundup(ring->desc_size, cache_line_size()));
103 ring->desc_size = roundup(ring->desc_size, cache_line_size());
106 ring->descs_cpu = dma_alloc_coherent(NULL, ring->size * ring->desc_size,
107 &ring->descs_dma, GFP_ATOMIC);
108 if (!ring->descs_cpu) {
114 ring->buf = kzalloc(ring->size * sizeof(*ring->buf), GFP_KERNEL);
120 for (i = 0; i < ring->size; i++) {
121 int idx = i * ring->desc_size;
122 ring->buf[i].desc = (struct ag71xx_desc *)&ring->descs_cpu[idx];
123 DBG("ag71xx: ring %p, desc %d at %p\n",
124 ring, i, ring->buf[i].desc);
133 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
135 struct ag71xx_ring *ring = &ag->tx_ring;
136 struct net_device *dev = ag->dev;
138 while (ring->curr != ring->dirty) {
139 u32 i = ring->dirty % ring->size;
141 if (!ag71xx_desc_empty(ring->buf[i].desc)) {
142 ring->buf[i].desc->ctrl = 0;
143 dev->stats.tx_errors++;
146 if (ring->buf[i].skb)
147 dev_kfree_skb_any(ring->buf[i].skb);
149 ring->buf[i].skb = NULL;
154 /* flush descriptors */
159 static void ag71xx_ring_tx_init(struct ag71xx *ag)
161 struct ag71xx_ring *ring = &ag->tx_ring;
164 for (i = 0; i < ring->size; i++) {
165 ring->buf[i].desc->next = (u32) (ring->descs_dma +
166 ring->desc_size * ((i + 1) % ring->size));
168 ring->buf[i].desc->ctrl = DESC_EMPTY;
169 ring->buf[i].skb = NULL;
172 /* flush descriptors */
179 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
181 struct ag71xx_ring *ring = &ag->rx_ring;
187 for (i = 0; i < ring->size; i++)
188 if (ring->buf[i].skb) {
189 dma_unmap_single(&ag->dev->dev, ring->buf[i].dma_addr,
190 AG71XX_RX_PKT_SIZE, DMA_FROM_DEVICE);
191 kfree_skb(ring->buf[i].skb);
195 static int ag71xx_rx_reserve(struct ag71xx *ag)
199 if (ag71xx_get_pdata(ag)->is_ar724x) {
200 if (!ag71xx_has_ar8216(ag))
204 reserve += 4 - (ag->phy_dev->pkt_align % 4);
209 return reserve + AG71XX_RX_PKT_RESERVE;
213 static int ag71xx_ring_rx_init(struct ag71xx *ag)
215 struct ag71xx_ring *ring = &ag->rx_ring;
216 unsigned int reserve = ag71xx_rx_reserve(ag);
221 for (i = 0; i < ring->size; i++) {
222 ring->buf[i].desc->next = (u32) (ring->descs_dma +
223 ring->desc_size * ((i + 1) % ring->size));
225 DBG("ag71xx: RX desc at %p, next is %08x\n",
227 ring->buf[i].desc->next);
230 for (i = 0; i < ring->size; i++) {
234 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE + reserve);
241 skb_reserve(skb, reserve);
243 dma_addr = dma_map_single(&ag->dev->dev, skb->data,
246 ring->buf[i].skb = skb;
247 ring->buf[i].dma_addr = dma_addr;
248 ring->buf[i].desc->data = (u32) dma_addr;
249 ring->buf[i].desc->ctrl = DESC_EMPTY;
252 /* flush descriptors */
261 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
263 struct ag71xx_ring *ring = &ag->rx_ring;
264 unsigned int reserve = ag71xx_rx_reserve(ag);
268 for (; ring->curr - ring->dirty > 0; ring->dirty++) {
271 i = ring->dirty % ring->size;
273 if (ring->buf[i].skb == NULL) {
277 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE + reserve);
281 skb_reserve(skb, reserve);
284 dma_addr = dma_map_single(&ag->dev->dev, skb->data,
288 ring->buf[i].skb = skb;
289 ring->buf[i].dma_addr = dma_addr;
290 ring->buf[i].desc->data = (u32) dma_addr;
293 ring->buf[i].desc->ctrl = DESC_EMPTY;
297 /* flush descriptors */
300 DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
305 static int ag71xx_rings_init(struct ag71xx *ag)
309 ret = ag71xx_ring_alloc(&ag->tx_ring);
313 ag71xx_ring_tx_init(ag);
315 ret = ag71xx_ring_alloc(&ag->rx_ring);
319 ret = ag71xx_ring_rx_init(ag);
323 static void ag71xx_rings_cleanup(struct ag71xx *ag)
325 ag71xx_ring_rx_clean(ag);
326 ag71xx_ring_free(&ag->rx_ring);
328 ag71xx_ring_tx_clean(ag);
329 ag71xx_ring_free(&ag->tx_ring);
332 static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
346 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
350 t = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16)
351 | (((u32) mac[3]) << 8) | ((u32) mac[2]);
353 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
355 t = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16);
356 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
359 static void ag71xx_dma_reset(struct ag71xx *ag)
364 ag71xx_dump_dma_regs(ag);
367 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
368 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
371 * give the hardware some time to really stop all rx/tx activity
372 * clearing the descriptors too early causes random memory corruption
376 /* clear descriptor addresses */
377 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->stop_desc_dma);
378 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->stop_desc_dma);
380 /* clear pending RX/TX interrupts */
381 for (i = 0; i < 256; i++) {
382 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
383 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
386 /* clear pending errors */
387 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
388 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
390 val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
392 printk(KERN_ALERT "%s: unable to clear DMA Rx status: %08x\n",
395 val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
397 /* mask out reserved bits */
401 printk(KERN_ALERT "%s: unable to clear DMA Tx status: %08x\n",
404 ag71xx_dump_dma_regs(ag);
407 #define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
408 MAC_CFG1_SRX | MAC_CFG1_STX)
410 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
412 #define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
413 FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
414 FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
415 FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
416 FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
419 #define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
420 FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
421 FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
422 FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
423 FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
424 FIFO_CFG5_17 | FIFO_CFG5_SF)
426 static void ag71xx_hw_stop(struct ag71xx *ag)
428 /* disable all interrupts and stop the rx/tx engine */
429 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
430 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
431 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
434 static void ag71xx_hw_setup(struct ag71xx *ag)
436 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
438 /* setup MAC configuration registers */
439 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT);
441 ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
442 MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
444 /* setup max frame length */
445 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, AG71XX_TX_MTU_LEN);
447 /* setup MII interface type */
448 ag71xx_mii_ctrl_set_if(ag, pdata->mii_if);
450 /* setup FIFO configuration registers */
451 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
452 if (pdata->is_ar724x) {
453 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, pdata->fifo_cfg1);
454 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, pdata->fifo_cfg2);
456 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
457 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
459 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
460 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
463 static void ag71xx_hw_init(struct ag71xx *ag)
465 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
466 u32 reset_mask = pdata->reset_bit;
470 if (pdata->is_ar724x) {
471 u32 reset_phy = reset_mask;
473 reset_phy &= RESET_MODULE_GE0_PHY | RESET_MODULE_GE1_PHY;
474 reset_mask &= ~(RESET_MODULE_GE0_PHY | RESET_MODULE_GE1_PHY);
476 ar71xx_device_stop(reset_phy);
478 ar71xx_device_start(reset_phy);
482 ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
485 ar71xx_device_stop(reset_mask);
487 ar71xx_device_start(reset_mask);
492 ag71xx_dma_reset(ag);
495 static void ag71xx_fast_reset(struct ag71xx *ag)
497 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
498 struct net_device *dev = ag->dev;
499 u32 reset_mask = pdata->reset_bit;
503 reset_mask &= RESET_MODULE_GE0_MAC | RESET_MODULE_GE1_MAC;
505 mii_reg = ag71xx_rr(ag, AG71XX_REG_MII_CFG);
506 rx_ds = ag71xx_rr(ag, AG71XX_REG_RX_DESC);
507 tx_ds = ag71xx_rr(ag, AG71XX_REG_TX_DESC);
509 ar71xx_device_stop(reset_mask);
511 ar71xx_device_start(reset_mask);
514 ag71xx_dma_reset(ag);
517 ag71xx_wr(ag, AG71XX_REG_RX_DESC, rx_ds);
518 ag71xx_wr(ag, AG71XX_REG_TX_DESC, tx_ds);
519 ag71xx_wr(ag, AG71XX_REG_MII_CFG, mii_reg);
521 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
524 static void ag71xx_hw_start(struct ag71xx *ag)
526 /* start RX engine */
527 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
529 /* enable interrupts */
530 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
533 void ag71xx_link_adjust(struct ag71xx *ag)
535 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
543 netif_carrier_off(ag->dev);
544 if (netif_msg_link(ag))
545 printk(KERN_INFO "%s: link down\n", ag->dev->name);
549 if (pdata->is_ar724x)
550 ag71xx_fast_reset(ag);
552 cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
553 cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
554 cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
556 ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
557 ifctl &= ~(MAC_IFCTL_SPEED);
559 fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
560 fifo5 &= ~FIFO_CFG5_BM;
564 mii_speed = MII_CTRL_SPEED_1000;
565 cfg2 |= MAC_CFG2_IF_1000;
566 fifo5 |= FIFO_CFG5_BM;
569 mii_speed = MII_CTRL_SPEED_100;
570 cfg2 |= MAC_CFG2_IF_10_100;
571 ifctl |= MAC_IFCTL_SPEED;
574 mii_speed = MII_CTRL_SPEED_10;
575 cfg2 |= MAC_CFG2_IF_10_100;
582 if (pdata->is_ar91xx)
583 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x00780fff);
584 else if (pdata->is_ar724x)
585 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, pdata->fifo_cfg3);
587 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x008001ff);
590 pdata->set_pll(ag->speed);
592 ag71xx_mii_ctrl_set_speed(ag, mii_speed);
594 ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
595 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
596 ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
599 netif_carrier_on(ag->dev);
600 if (netif_msg_link(ag))
601 printk(KERN_INFO "%s: link up (%sMbps/%s duplex)\n",
603 ag71xx_speed_str(ag),
604 (DUPLEX_FULL == ag->duplex) ? "Full" : "Half");
606 DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n",
608 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
609 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
610 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
612 DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n",
614 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
615 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
616 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
618 DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x, mii_ctrl=%#x\n",
620 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
621 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
622 ag71xx_mii_ctrl_rr(ag));
625 static int ag71xx_open(struct net_device *dev)
627 struct ag71xx *ag = netdev_priv(dev);
630 ret = ag71xx_rings_init(ag);
634 napi_enable(&ag->napi);
636 netif_carrier_off(dev);
637 ag71xx_phy_start(ag);
639 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
640 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
642 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
644 netif_start_queue(dev);
649 ag71xx_rings_cleanup(ag);
653 static int ag71xx_stop(struct net_device *dev)
655 struct ag71xx *ag = netdev_priv(dev);
658 netif_carrier_off(dev);
661 spin_lock_irqsave(&ag->lock, flags);
663 netif_stop_queue(dev);
666 ag71xx_dma_reset(ag);
668 napi_disable(&ag->napi);
669 del_timer_sync(&ag->oom_timer);
671 spin_unlock_irqrestore(&ag->lock, flags);
673 ag71xx_rings_cleanup(ag);
678 static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb,
679 struct net_device *dev)
681 struct ag71xx *ag = netdev_priv(dev);
682 struct ag71xx_ring *ring = &ag->tx_ring;
683 struct ag71xx_desc *desc;
687 i = ring->curr % ring->size;
688 desc = ring->buf[i].desc;
690 if (!ag71xx_desc_empty(desc))
693 if (ag71xx_has_ar8216(ag))
694 ag71xx_add_ar8216_header(ag, skb);
697 DBG("%s: packet len is too small\n", ag->dev->name);
701 dma_addr = dma_map_single(&dev->dev, skb->data, skb->len,
704 ring->buf[i].skb = skb;
705 ring->buf[i].timestamp = jiffies;
707 /* setup descriptor fields */
708 desc->data = (u32) dma_addr;
709 desc->ctrl = (skb->len & DESC_PKTLEN_M);
711 /* flush descriptor */
715 if (ring->curr == (ring->dirty + ring->size)) {
716 DBG("%s: tx queue full\n", ag->dev->name);
717 netif_stop_queue(dev);
720 DBG("%s: packet injected into TX queue\n", ag->dev->name);
722 /* enable TX engine */
723 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
728 dev->stats.tx_dropped++;
734 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
736 struct ag71xx *ag = netdev_priv(dev);
741 if (ag->phy_dev == NULL)
744 spin_lock_irq(&ag->lock);
745 ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
746 spin_unlock_irq(&ag->lock);
751 (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
757 (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
764 if (ag->phy_dev == NULL)
767 return phy_mii_ioctl(ag->phy_dev, ifr, cmd);
776 static void ag71xx_oom_timer_handler(unsigned long data)
778 struct net_device *dev = (struct net_device *) data;
779 struct ag71xx *ag = netdev_priv(dev);
781 napi_schedule(&ag->napi);
784 static void ag71xx_tx_timeout(struct net_device *dev)
786 struct ag71xx *ag = netdev_priv(dev);
788 if (netif_msg_tx_err(ag))
789 printk(KERN_DEBUG "%s: tx timeout\n", ag->dev->name);
791 schedule_work(&ag->restart_work);
794 static void ag71xx_restart_work_func(struct work_struct *work)
796 struct ag71xx *ag = container_of(work, struct ag71xx, restart_work);
798 if (ag71xx_get_pdata(ag)->is_ar724x) {
800 ag71xx_link_adjust(ag);
804 ag71xx_stop(ag->dev);
805 ag71xx_open(ag->dev);
808 static int ag71xx_tx_packets(struct ag71xx *ag)
810 struct ag71xx_ring *ring = &ag->tx_ring;
813 DBG("%s: processing TX ring\n", ag->dev->name);
816 while (ring->dirty != ring->curr) {
817 unsigned int i = ring->dirty % ring->size;
818 struct ag71xx_desc *desc = ring->buf[i].desc;
819 struct sk_buff *skb = ring->buf[i].skb;
821 if (!ag71xx_desc_empty(desc))
824 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
826 ag->dev->stats.tx_bytes += skb->len;
827 ag->dev->stats.tx_packets++;
829 dev_kfree_skb_any(skb);
830 ring->buf[i].skb = NULL;
836 DBG("%s: %d packets sent out\n", ag->dev->name, sent);
838 if ((ring->curr - ring->dirty) < (ring->size * 3) / 4)
839 netif_wake_queue(ag->dev);
844 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
846 struct net_device *dev = ag->dev;
847 struct ag71xx_ring *ring = &ag->rx_ring;
850 DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
851 dev->name, limit, ring->curr, ring->dirty);
853 while (done < limit) {
854 unsigned int i = ring->curr % ring->size;
855 struct ag71xx_desc *desc = ring->buf[i].desc;
860 if (ag71xx_desc_empty(desc))
863 if ((ring->dirty + ring->size) == ring->curr) {
868 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
870 skb = ring->buf[i].skb;
871 pktlen = ag71xx_desc_pktlen(desc);
872 pktlen -= ETH_FCS_LEN;
874 dma_unmap_single(&dev->dev, ring->buf[i].dma_addr,
875 AG71XX_RX_PKT_SIZE, DMA_FROM_DEVICE);
877 dev->last_rx = jiffies;
878 dev->stats.rx_packets++;
879 dev->stats.rx_bytes += pktlen;
881 skb_put(skb, pktlen);
882 if (ag71xx_has_ar8216(ag))
883 err = ag71xx_remove_ar8216_header(ag, skb, pktlen);
886 dev->stats.rx_dropped++;
890 skb->ip_summed = CHECKSUM_NONE;
892 ag->phy_dev->netif_receive_skb(skb);
894 skb->protocol = eth_type_trans(skb, dev);
895 netif_receive_skb(skb);
899 ring->buf[i].skb = NULL;
905 ag71xx_ring_rx_refill(ag);
907 DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
908 dev->name, ring->curr, ring->dirty, done);
913 static int ag71xx_poll(struct napi_struct *napi, int limit)
915 struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
916 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
917 struct net_device *dev = ag->dev;
918 struct ag71xx_ring *rx_ring;
925 tx_done = ag71xx_tx_packets(ag);
927 DBG("%s: processing RX ring\n", dev->name);
928 rx_done = ag71xx_rx_packets(ag, limit);
930 ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done);
932 rx_ring = &ag->rx_ring;
933 if (rx_ring->buf[rx_ring->dirty % rx_ring->size].skb == NULL)
936 status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
937 if (unlikely(status & RX_STATUS_OF)) {
938 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
939 dev->stats.rx_fifo_errors++;
942 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
945 if (rx_done < limit) {
946 if (status & RX_STATUS_PR)
949 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
950 if (status & TX_STATUS_PS)
953 DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n",
954 dev->name, rx_done, tx_done, limit);
958 /* enable interrupts */
959 spin_lock_irqsave(&ag->lock, flags);
960 ag71xx_int_enable(ag, AG71XX_INT_POLL);
961 spin_unlock_irqrestore(&ag->lock, flags);
966 DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n",
967 dev->name, rx_done, tx_done, limit);
971 if (netif_msg_rx_err(ag))
972 printk(KERN_DEBUG "%s: out of memory\n", dev->name);
974 mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
979 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
981 struct net_device *dev = dev_id;
982 struct ag71xx *ag = netdev_priv(dev);
985 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
986 ag71xx_dump_intr(ag, "raw", status);
988 if (unlikely(!status))
991 if (unlikely(status & AG71XX_INT_ERR)) {
992 if (status & AG71XX_INT_TX_BE) {
993 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
994 dev_err(&dev->dev, "TX BUS error\n");
996 if (status & AG71XX_INT_RX_BE) {
997 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
998 dev_err(&dev->dev, "RX BUS error\n");
1002 if (likely(status & AG71XX_INT_POLL)) {
1003 ag71xx_int_disable(ag, AG71XX_INT_POLL);
1004 DBG("%s: enable polling mode\n", dev->name);
1005 napi_schedule(&ag->napi);
1008 ag71xx_debugfs_update_int_stats(ag, status);
1013 static void ag71xx_set_multicast_list(struct net_device *dev)
1018 #ifdef CONFIG_NET_POLL_CONTROLLER
1020 * Polling 'interrupt' - used by things like netconsole to send skbs
1021 * without having to re-enable interrupts. It's not called while
1022 * the interrupt routine is executing.
1024 static void ag71xx_netpoll(struct net_device *dev)
1026 disable_irq(dev->irq);
1027 ag71xx_interrupt(dev->irq, dev);
1028 enable_irq(dev->irq);
1032 static const struct net_device_ops ag71xx_netdev_ops = {
1033 .ndo_open = ag71xx_open,
1034 .ndo_stop = ag71xx_stop,
1035 .ndo_start_xmit = ag71xx_hard_start_xmit,
1036 .ndo_set_multicast_list = ag71xx_set_multicast_list,
1037 .ndo_do_ioctl = ag71xx_do_ioctl,
1038 .ndo_tx_timeout = ag71xx_tx_timeout,
1039 .ndo_change_mtu = eth_change_mtu,
1040 .ndo_set_mac_address = eth_mac_addr,
1041 .ndo_validate_addr = eth_validate_addr,
1042 #ifdef CONFIG_NET_POLL_CONTROLLER
1043 .ndo_poll_controller = ag71xx_netpoll,
1047 static int __devinit ag71xx_probe(struct platform_device *pdev)
1049 struct net_device *dev;
1050 struct resource *res;
1052 struct ag71xx_platform_data *pdata;
1055 pdata = pdev->dev.platform_data;
1057 dev_err(&pdev->dev, "no platform data specified\n");
1062 if (pdata->mii_bus_dev == NULL) {
1063 dev_err(&pdev->dev, "no MII bus device specified\n");
1068 dev = alloc_etherdev(sizeof(*ag));
1070 dev_err(&pdev->dev, "alloc_etherdev failed\n");
1075 SET_NETDEV_DEV(dev, &pdev->dev);
1077 ag = netdev_priv(dev);
1080 ag->msg_enable = netif_msg_init(ag71xx_msg_level,
1081 AG71XX_DEFAULT_MSG_ENABLE);
1082 spin_lock_init(&ag->lock);
1084 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
1086 dev_err(&pdev->dev, "no mac_base resource found\n");
1091 ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1);
1092 if (!ag->mac_base) {
1093 dev_err(&pdev->dev, "unable to ioremap mac_base\n");
1098 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mii_ctrl");
1100 dev_err(&pdev->dev, "no mii_ctrl resource found\n");
1102 goto err_unmap_base;
1105 ag->mii_ctrl = ioremap_nocache(res->start, res->end - res->start + 1);
1106 if (!ag->mii_ctrl) {
1107 dev_err(&pdev->dev, "unable to ioremap mii_ctrl\n");
1109 goto err_unmap_base;
1112 dev->irq = platform_get_irq(pdev, 0);
1113 err = request_irq(dev->irq, ag71xx_interrupt,
1117 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
1118 goto err_unmap_mii_ctrl;
1121 dev->base_addr = (unsigned long)ag->mac_base;
1122 dev->netdev_ops = &ag71xx_netdev_ops;
1123 dev->ethtool_ops = &ag71xx_ethtool_ops;
1125 INIT_WORK(&ag->restart_work, ag71xx_restart_work_func);
1127 init_timer(&ag->oom_timer);
1128 ag->oom_timer.data = (unsigned long) dev;
1129 ag->oom_timer.function = ag71xx_oom_timer_handler;
1131 ag->tx_ring.size = AG71XX_TX_RING_SIZE_DEFAULT;
1132 ag->rx_ring.size = AG71XX_RX_RING_SIZE_DEFAULT;
1134 ag->stop_desc = dma_alloc_coherent(NULL,
1135 sizeof(struct ag71xx_desc), &ag->stop_desc_dma, GFP_KERNEL);
1140 ag->stop_desc->data = 0;
1141 ag->stop_desc->ctrl = 0;
1142 ag->stop_desc->next = (u32) ag->stop_desc_dma;
1144 memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
1146 netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
1148 err = register_netdev(dev);
1150 dev_err(&pdev->dev, "unable to register net device\n");
1154 printk(KERN_INFO "%s: Atheros AG71xx at 0x%08lx, irq %d\n",
1155 dev->name, dev->base_addr, dev->irq);
1157 ag71xx_dump_regs(ag);
1161 ag71xx_dump_regs(ag);
1163 err = ag71xx_phy_connect(ag);
1165 goto err_unregister_netdev;
1167 err = ag71xx_debugfs_init(ag);
1169 goto err_phy_disconnect;
1171 platform_set_drvdata(pdev, dev);
1176 ag71xx_phy_disconnect(ag);
1177 err_unregister_netdev:
1178 unregister_netdev(dev);
1180 dma_free_coherent(NULL, sizeof(struct ag71xx_desc), ag->stop_desc,
1183 free_irq(dev->irq, dev);
1185 iounmap(ag->mii_ctrl);
1187 iounmap(ag->mac_base);
1191 platform_set_drvdata(pdev, NULL);
1195 static int __devexit ag71xx_remove(struct platform_device *pdev)
1197 struct net_device *dev = platform_get_drvdata(pdev);
1200 struct ag71xx *ag = netdev_priv(dev);
1202 ag71xx_debugfs_exit(ag);
1203 ag71xx_phy_disconnect(ag);
1204 unregister_netdev(dev);
1205 free_irq(dev->irq, dev);
1206 iounmap(ag->mii_ctrl);
1207 iounmap(ag->mac_base);
1209 platform_set_drvdata(pdev, NULL);
1215 static struct platform_driver ag71xx_driver = {
1216 .probe = ag71xx_probe,
1217 .remove = __exit_p(ag71xx_remove),
1219 .name = AG71XX_DRV_NAME,
1223 static int __init ag71xx_module_init(void)
1227 ret = ag71xx_debugfs_root_init();
1231 ret = ag71xx_mdio_driver_init();
1233 goto err_debugfs_exit;
1235 ret = platform_driver_register(&ag71xx_driver);
1242 ag71xx_mdio_driver_exit();
1244 ag71xx_debugfs_root_exit();
1249 static void __exit ag71xx_module_exit(void)
1251 platform_driver_unregister(&ag71xx_driver);
1252 ag71xx_mdio_driver_exit();
1253 ag71xx_debugfs_root_exit();
1256 module_init(ag71xx_module_init);
1257 module_exit(ag71xx_module_exit);
1259 MODULE_VERSION(AG71XX_DRV_VERSION);
1260 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1261 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
1262 MODULE_LICENSE("GPL v2");
1263 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);