2 * Atheros AR71xx built-in ethernet mac driver
4 * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 * Based on Atheros' AG7100 driver
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
16 #define AG71XX_DEFAULT_MSG_ENABLE \
26 static int ag71xx_debug = -1;
28 module_param(ag71xx_debug, int, 0);
29 MODULE_PARM_DESC(ag71xx_debug, "Debug level (-1=defaults,0=none,...,16=all)");
31 static void ag71xx_dump_dma_regs(struct ag71xx *ag)
33 DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
35 ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
36 ag71xx_rr(ag, AG71XX_REG_TX_DESC),
37 ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
39 DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
41 ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
42 ag71xx_rr(ag, AG71XX_REG_RX_DESC),
43 ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
46 static void ag71xx_dump_regs(struct ag71xx *ag)
48 DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
50 ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
51 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
52 ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
53 ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
54 ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
55 DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
57 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
58 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
59 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
60 DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
62 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
63 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
64 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
65 DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
67 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
68 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
69 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
72 static void ag71xx_ring_free(struct ag71xx_ring *ring)
77 dma_free_coherent(NULL, ring->size * sizeof(*ring->descs),
78 ring->descs, ring->descs_dma);
81 static int ag71xx_ring_alloc(struct ag71xx_ring *ring, unsigned int size)
85 ring->descs = dma_alloc_coherent(NULL, size * sizeof(*ring->descs),
95 ring->buf = kzalloc(size * sizeof(*ring->buf), GFP_KERNEL);
107 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
109 struct ag71xx_ring *ring = &ag->tx_ring;
110 struct net_device *dev = ag->dev;
112 while (ring->curr != ring->dirty) {
113 u32 i = ring->dirty % AG71XX_TX_RING_SIZE;
115 if (!ag71xx_desc_empty(&ring->descs[i])) {
116 ring->descs[i].ctrl = 0;
117 dev->stats.tx_errors++;
120 if (ring->buf[i].skb)
121 dev_kfree_skb_any(ring->buf[i].skb);
123 ring->buf[i].skb = NULL;
128 /* flush descriptors */
133 static void ag71xx_ring_tx_init(struct ag71xx *ag)
135 struct ag71xx_ring *ring = &ag->tx_ring;
138 for (i = 0; i < AG71XX_TX_RING_SIZE; i++) {
139 ring->descs[i].next = (u32) (ring->descs_dma +
140 sizeof(*ring->descs) * ((i + 1) % AG71XX_TX_RING_SIZE));
142 ring->descs[i].ctrl = DESC_EMPTY;
143 ring->buf[i].skb = NULL;
146 /* flush descriptors */
153 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
155 struct ag71xx_ring *ring = &ag->rx_ring;
161 for (i = 0; i < AG71XX_RX_RING_SIZE; i++)
162 if (ring->buf[i].skb)
163 kfree_skb(ring->buf[i].skb);
167 static int ag71xx_ring_rx_init(struct ag71xx *ag)
169 struct ag71xx_ring *ring = &ag->rx_ring;
174 for (i = 0; i < AG71XX_RX_RING_SIZE; i++)
175 ring->descs[i].next = (u32) (ring->descs_dma +
176 sizeof(*ring->descs) * ((i + 1) % AG71XX_RX_RING_SIZE));
178 for (i = 0; i < AG71XX_RX_RING_SIZE; i++) {
181 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE);
188 skb_reserve(skb, AG71XX_RX_PKT_RESERVE);
190 ring->buf[i].skb = skb;
191 ring->descs[i].data = virt_to_phys(skb->data);
192 ring->descs[i].ctrl = DESC_EMPTY;
195 /* flush descriptors */
204 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
206 struct ag71xx_ring *ring = &ag->rx_ring;
210 for (; ring->curr - ring->dirty > 0; ring->dirty++) {
213 i = ring->dirty % AG71XX_RX_RING_SIZE;
215 if (ring->buf[i].skb == NULL) {
218 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE);
220 printk(KERN_ERR "%s: no memory for skb\n",
225 skb_reserve(skb, AG71XX_RX_PKT_RESERVE);
227 ring->buf[i].skb = skb;
228 ring->descs[i].data = virt_to_phys(skb->data);
231 ring->descs[i].ctrl = DESC_EMPTY;
235 /* flush descriptors */
238 DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
243 static int ag71xx_rings_init(struct ag71xx *ag)
247 ret = ag71xx_ring_alloc(&ag->tx_ring, AG71XX_TX_RING_SIZE);
251 ag71xx_ring_tx_init(ag);
253 ret = ag71xx_ring_alloc(&ag->rx_ring, AG71XX_RX_RING_SIZE);
257 ret = ag71xx_ring_rx_init(ag);
261 static void ag71xx_rings_cleanup(struct ag71xx *ag)
263 ag71xx_ring_rx_clean(ag);
264 ag71xx_ring_free(&ag->rx_ring);
266 ag71xx_ring_tx_clean(ag);
267 ag71xx_ring_free(&ag->tx_ring);
270 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
274 t = (((u32) mac[0]) << 24) | (((u32) mac[1]) << 16)
275 | (((u32) mac[2]) << 8) | ((u32) mac[3]);
277 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
279 t = (((u32) mac[4]) << 24) | (((u32) mac[5]) << 16);
280 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
283 #define AR71XX_MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
284 MAC_CFG1_SRX | MAC_CFG1_STX)
285 #define AR71XX_FIFO_CFG5_INIT 0x0007ffef
287 #define AR91XX_MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
288 MAC_CFG1_SRX | MAC_CFG1_STX | \
289 MAC_CFG1_TFC | MAC_CFG1_RFC)
290 #define AR91XX_FIFO_CFG5_INIT 0x0007efef
292 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
294 static void ag71xx_dma_reset(struct ag71xx *ag)
298 ag71xx_dump_dma_regs(ag);
301 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
302 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
304 /* clear descriptor addresses */
305 ag71xx_wr(ag, AG71XX_REG_TX_DESC, 0);
306 ag71xx_wr(ag, AG71XX_REG_RX_DESC, 0);
308 /* clear pending RX/TX interrupts */
309 for (i = 0; i < 256; i++) {
310 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
311 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
314 /* clear pending errors */
315 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
316 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
318 ag71xx_dump_dma_regs(ag);
321 static void ag71xx_hw_init(struct ag71xx *ag)
323 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
325 ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
328 ar71xx_device_stop(pdata->reset_bit);
330 ar71xx_device_start(pdata->reset_bit);
333 /* setup MAC configuration registers */
334 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1,
335 pdata->is_ar91xx ? AR91XX_MAC_CFG1_INIT : AR71XX_MAC_CFG1_INIT);
336 ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
337 MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
339 /* setup max frame length */
340 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, AG71XX_TX_MTU_LEN);
342 /* setup MII interface type */
343 ag71xx_mii_ctrl_set_if(ag, pdata->mii_if);
345 /* setup FIFO configuration registers */
346 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
347 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
348 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
349 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, 0x0000ffff);
350 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5,
351 pdata->is_ar91xx ? AR91XX_FIFO_CFG5_INIT
352 : AR71XX_FIFO_CFG5_INIT);
354 ag71xx_dma_reset(ag);
357 static void ag71xx_hw_start(struct ag71xx *ag)
359 /* start RX engine */
360 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
362 /* enable interrupts */
363 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
366 static void ag71xx_hw_stop(struct ag71xx *ag)
368 /* disable all interrupts */
369 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
371 ag71xx_dma_reset(ag);
374 static int ag71xx_open(struct net_device *dev)
376 struct ag71xx *ag = netdev_priv(dev);
379 ret = ag71xx_rings_init(ag);
383 napi_enable(&ag->napi);
385 netif_carrier_off(dev);
386 ag71xx_phy_start(ag);
388 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
389 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
391 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
395 netif_start_queue(dev);
400 ag71xx_rings_cleanup(ag);
404 static int ag71xx_stop(struct net_device *dev)
406 struct ag71xx *ag = netdev_priv(dev);
409 spin_lock_irqsave(&ag->lock, flags);
411 netif_stop_queue(dev);
415 netif_carrier_off(dev);
418 napi_disable(&ag->napi);
420 spin_unlock_irqrestore(&ag->lock, flags);
422 ag71xx_rings_cleanup(ag);
427 static int ag71xx_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
429 struct ag71xx *ag = netdev_priv(dev);
430 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
431 struct ag71xx_ring *ring = &ag->tx_ring;
432 struct ag71xx_desc *desc;
436 i = ring->curr % AG71XX_TX_RING_SIZE;
437 desc = &ring->descs[i];
439 spin_lock_irqsave(&ag->lock, flags);
441 spin_unlock_irqrestore(&ag->lock, flags);
443 if (!ag71xx_desc_empty(desc))
447 DBG("%s: packet len is too small\n", ag->dev->name);
451 dma_cache_wback_inv((unsigned long)skb->data, skb->len);
453 ring->buf[i].skb = skb;
455 /* setup descriptor fields */
456 desc->data = virt_to_phys(skb->data);
457 desc->ctrl = (skb->len & DESC_PKTLEN_M);
459 /* flush descriptor */
463 if (ring->curr == (ring->dirty + AG71XX_TX_THRES_STOP)) {
464 DBG("%s: tx queue full\n", ag->dev->name);
465 netif_stop_queue(dev);
468 DBG("%s: packet injected into TX queue\n", ag->dev->name);
470 /* enable TX engine */
471 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
473 dev->trans_start = jiffies;
478 dev->stats.tx_dropped++;
484 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
486 struct mii_ioctl_data *data = (struct mii_ioctl_data *) &ifr->ifr_data;
487 struct ag71xx *ag = netdev_priv(dev);
492 if (ag->phy_dev == NULL)
495 spin_lock_irq(&ag->lock);
496 ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
497 spin_unlock_irq(&ag->lock);
502 (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
508 (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
515 if (ag->phy_dev == NULL)
518 return phy_mii_ioctl(ag->phy_dev, data, cmd);
527 static void ag71xx_tx_packets(struct ag71xx *ag)
529 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
530 struct ag71xx_ring *ring = &ag->tx_ring;
533 DBG("%s: processing TX ring\n", ag->dev->name);
535 #ifdef AG71XX_NAPI_TX
540 while (ring->dirty != ring->curr) {
541 unsigned int i = ring->dirty % AG71XX_TX_RING_SIZE;
542 struct ag71xx_desc *desc = &ring->descs[i];
543 struct sk_buff *skb = ring->buf[i].skb;
545 if (!ag71xx_desc_empty(desc))
548 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
550 ag->dev->stats.tx_bytes += skb->len;
551 ag->dev->stats.tx_packets++;
553 dev_kfree_skb_any(skb);
554 ring->buf[i].skb = NULL;
560 DBG("%s: %d packets sent out\n", ag->dev->name, sent);
562 if ((ring->curr - ring->dirty) < AG71XX_TX_THRES_WAKEUP)
563 netif_wake_queue(ag->dev);
567 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
569 struct net_device *dev = ag->dev;
570 struct ag71xx_ring *ring = &ag->rx_ring;
571 #ifndef AG71XX_NAPI_TX
572 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
577 #ifndef AG71XX_NAPI_TX
578 spin_lock_irqsave(&ag->lock, flags);
580 spin_unlock_irqrestore(&ag->lock, flags);
583 DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
584 dev->name, limit, ring->curr, ring->dirty);
586 while (done < limit) {
587 unsigned int i = ring->curr % AG71XX_RX_RING_SIZE;
588 struct ag71xx_desc *desc = &ring->descs[i];
592 if (ag71xx_desc_empty(desc))
595 if ((ring->dirty + AG71XX_RX_RING_SIZE) == ring->curr) {
600 skb = ring->buf[i].skb;
601 pktlen = ag71xx_desc_pktlen(desc);
602 pktlen -= ETH_FCS_LEN;
604 /* TODO: move it into the refill function */
605 dma_cache_wback_inv((unsigned long)skb->data, pktlen);
606 skb_put(skb, pktlen);
609 skb->protocol = eth_type_trans(skb, dev);
610 skb->ip_summed = CHECKSUM_UNNECESSARY;
612 netif_receive_skb(skb);
614 dev->last_rx = jiffies;
615 dev->stats.rx_packets++;
616 dev->stats.rx_bytes += pktlen;
618 ring->buf[i].skb = NULL;
621 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
624 if ((ring->curr - ring->dirty) > (AG71XX_RX_RING_SIZE / 4))
625 ag71xx_ring_rx_refill(ag);
628 ag71xx_ring_rx_refill(ag);
630 DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
631 dev->name, ring->curr, ring->dirty, done);
636 static int ag71xx_poll(struct napi_struct *napi, int limit)
638 struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
639 #ifdef AG71XX_NAPI_TX
640 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
642 struct net_device *dev = ag->dev;
647 #ifdef AG71XX_NAPI_TX
649 ag71xx_tx_packets(ag);
652 DBG("%s: processing RX ring\n", dev->name);
653 done = ag71xx_rx_packets(ag, limit);
655 /* TODO: add OOM handler */
657 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
658 status &= AG71XX_INT_POLL;
660 if ((done < limit) && (!status)) {
661 DBG("%s: disable polling mode, done=%d, status=%x\n",
662 dev->name, done, status);
664 netif_rx_complete(dev, napi);
666 /* enable interrupts */
667 spin_lock_irqsave(&ag->lock, flags);
668 ag71xx_int_enable(ag, AG71XX_INT_POLL);
669 spin_unlock_irqrestore(&ag->lock, flags);
673 if (status & AG71XX_INT_RX_OF) {
674 if (netif_msg_rx_err(ag))
675 printk(KERN_ALERT "%s: rx owerflow, restarting dma\n",
679 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
681 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
684 DBG("%s: stay in polling mode, done=%d, status=%x\n",
685 dev->name, done, status);
689 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
691 struct net_device *dev = dev_id;
692 struct ag71xx *ag = netdev_priv(dev);
695 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
696 status &= ag71xx_rr(ag, AG71XX_REG_INT_ENABLE);
698 if (unlikely(!status))
701 if (unlikely(status & AG71XX_INT_ERR)) {
702 if (status & AG71XX_INT_TX_BE) {
703 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
704 dev_err(&dev->dev, "TX BUS error\n");
706 if (status & AG71XX_INT_RX_BE) {
707 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
708 dev_err(&dev->dev, "RX BUS error\n");
713 if (unlikely(status & AG71XX_INT_TX_UR)) {
714 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_UR);
715 DBG("%s: TX underrun\n", dev->name);
719 #ifndef AG71XX_NAPI_TX
720 if (likely(status & AG71XX_INT_TX_PS))
721 ag71xx_tx_packets(ag);
724 if (likely(status & AG71XX_INT_POLL)) {
725 ag71xx_int_disable(ag, AG71XX_INT_POLL);
726 DBG("%s: enable polling mode\n", dev->name);
727 netif_rx_schedule(dev, &ag->napi);
733 static void ag71xx_set_multicast_list(struct net_device *dev)
738 static int __init ag71xx_probe(struct platform_device *pdev)
740 struct net_device *dev;
741 struct resource *res;
743 struct ag71xx_platform_data *pdata;
746 pdata = pdev->dev.platform_data;
748 dev_err(&pdev->dev, "no platform data specified\n");
753 dev = alloc_etherdev(sizeof(*ag));
755 dev_err(&pdev->dev, "alloc_etherdev failed\n");
760 SET_NETDEV_DEV(dev, &pdev->dev);
762 ag = netdev_priv(dev);
765 ag->mii_bus = &ag71xx_mdio_bus->mii_bus;
766 ag->msg_enable = netif_msg_init(ag71xx_debug,
767 AG71XX_DEFAULT_MSG_ENABLE);
768 spin_lock_init(&ag->lock);
770 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
772 dev_err(&pdev->dev, "no mac_base resource found\n");
777 ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1);
779 dev_err(&pdev->dev, "unable to ioremap mac_base\n");
784 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base2");
786 dev_err(&pdev->dev, "no mac_base2 resource found\n");
788 goto err_unmap_base1;
791 ag->mac_base2 = ioremap_nocache(res->start, res->end - res->start + 1);
793 dev_err(&pdev->dev, "unable to ioremap mac_base2\n");
795 goto err_unmap_base1;
798 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mii_ctrl");
800 dev_err(&pdev->dev, "no mii_ctrl resource found\n");
802 goto err_unmap_base2;
805 ag->mii_ctrl = ioremap_nocache(res->start, res->end - res->start + 1);
807 dev_err(&pdev->dev, "unable to ioremap mii_ctrl\n");
809 goto err_unmap_base2;
812 dev->irq = platform_get_irq(pdev, 0);
813 err = request_irq(dev->irq, ag71xx_interrupt,
814 IRQF_DISABLED | IRQF_SAMPLE_RANDOM,
817 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
818 goto err_unmap_mii_ctrl;
821 dev->base_addr = (unsigned long)ag->mac_base;
822 dev->open = ag71xx_open;
823 dev->stop = ag71xx_stop;
824 dev->hard_start_xmit = ag71xx_hard_start_xmit;
825 dev->set_multicast_list = ag71xx_set_multicast_list;
826 dev->do_ioctl = ag71xx_do_ioctl;
827 dev->ethtool_ops = &ag71xx_ethtool_ops;
829 netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
831 if (is_valid_ether_addr(pdata->mac_addr))
832 memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
834 dev->dev_addr[0] = 0xde;
835 dev->dev_addr[1] = 0xad;
836 get_random_bytes(&dev->dev_addr[2], 3);
837 dev->dev_addr[5] = pdev->id & 0xff;
840 err = register_netdev(dev);
842 dev_err(&pdev->dev, "unable to register net device\n");
846 printk(KERN_INFO "%s: Atheros AG71xx at 0x%08lx, irq %d\n",
847 dev->name, dev->base_addr, dev->irq);
849 ag71xx_dump_regs(ag);
853 ag71xx_dump_regs(ag);
855 /* Reset the mdio bus explicitly */
857 mutex_lock(&ag->mii_bus->mdio_lock);
858 ag->mii_bus->reset(ag->mii_bus);
859 mutex_unlock(&ag->mii_bus->mdio_lock);
862 err = ag71xx_phy_connect(ag);
864 goto err_unregister_netdev;
866 platform_set_drvdata(pdev, dev);
870 err_unregister_netdev:
871 unregister_netdev(dev);
873 free_irq(dev->irq, dev);
875 iounmap(ag->mii_ctrl);
877 iounmap(ag->mac_base2);
879 iounmap(ag->mac_base);
883 platform_set_drvdata(pdev, NULL);
887 static int __exit ag71xx_remove(struct platform_device *pdev)
889 struct net_device *dev = platform_get_drvdata(pdev);
892 struct ag71xx *ag = netdev_priv(dev);
894 ag71xx_phy_disconnect(ag);
895 unregister_netdev(dev);
896 free_irq(dev->irq, dev);
897 iounmap(ag->mii_ctrl);
898 iounmap(ag->mac_base2);
899 iounmap(ag->mac_base);
901 platform_set_drvdata(pdev, NULL);
907 static struct platform_driver ag71xx_driver = {
908 .probe = ag71xx_probe,
909 .remove = __exit_p(ag71xx_remove),
911 .name = AG71XX_DRV_NAME,
915 static int __init ag71xx_module_init(void)
919 ret = ag71xx_mdio_driver_init();
923 ret = platform_driver_register(&ag71xx_driver);
930 ag71xx_mdio_driver_exit();
935 static void __exit ag71xx_module_exit(void)
937 platform_driver_unregister(&ag71xx_driver);
938 ag71xx_mdio_driver_exit();
941 module_init(ag71xx_module_init);
942 module_exit(ag71xx_module_exit);
944 MODULE_VERSION(AG71XX_DRV_VERSION);
945 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
946 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
947 MODULE_LICENSE("GPL v2");
948 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);