2 * Atheros AR71xx built-in ethernet mac driver
4 * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 * Based on Atheros' AG7100 driver
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
16 #define AG71XX_DEFAULT_MSG_ENABLE \
26 static int ag71xx_debug = -1;
28 module_param(ag71xx_debug, int, 0);
29 MODULE_PARM_DESC(ag71xx_debug, "Debug level (-1=defaults,0=none,...,16=all)");
31 static void ag71xx_dump_dma_regs(struct ag71xx *ag)
33 DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
35 ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
36 ag71xx_rr(ag, AG71XX_REG_TX_DESC),
37 ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
39 DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
41 ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
42 ag71xx_rr(ag, AG71XX_REG_RX_DESC),
43 ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
46 static void ag71xx_dump_regs(struct ag71xx *ag)
48 DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
50 ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
51 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
52 ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
53 ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
54 ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
55 DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
57 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
58 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
59 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
60 DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
62 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
63 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
64 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
65 DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
67 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
68 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
69 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
72 static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
74 DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
75 ag->dev->name, label, intr,
76 (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
77 (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
78 (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
79 (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
80 (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
81 (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
84 static void ag71xx_ring_free(struct ag71xx_ring *ring)
89 dma_free_coherent(NULL, ring->size * sizeof(*ring->descs),
90 ring->descs, ring->descs_dma);
93 static int ag71xx_ring_alloc(struct ag71xx_ring *ring, unsigned int size)
97 ring->descs = dma_alloc_coherent(NULL, size * sizeof(*ring->descs),
107 ring->buf = kzalloc(size * sizeof(*ring->buf), GFP_KERNEL);
119 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
121 struct ag71xx_ring *ring = &ag->tx_ring;
122 struct net_device *dev = ag->dev;
124 while (ring->curr != ring->dirty) {
125 u32 i = ring->dirty % AG71XX_TX_RING_SIZE;
127 if (!ag71xx_desc_empty(&ring->descs[i])) {
128 ring->descs[i].ctrl = 0;
129 dev->stats.tx_errors++;
132 if (ring->buf[i].skb)
133 dev_kfree_skb_any(ring->buf[i].skb);
135 ring->buf[i].skb = NULL;
140 /* flush descriptors */
145 static void ag71xx_ring_tx_init(struct ag71xx *ag)
147 struct ag71xx_ring *ring = &ag->tx_ring;
150 for (i = 0; i < AG71XX_TX_RING_SIZE; i++) {
151 ring->descs[i].next = (u32) (ring->descs_dma +
152 sizeof(*ring->descs) * ((i + 1) % AG71XX_TX_RING_SIZE));
154 ring->descs[i].ctrl = DESC_EMPTY;
155 ring->buf[i].skb = NULL;
158 /* flush descriptors */
165 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
167 struct ag71xx_ring *ring = &ag->rx_ring;
173 for (i = 0; i < AG71XX_RX_RING_SIZE; i++)
174 if (ring->buf[i].skb)
175 kfree_skb(ring->buf[i].skb);
179 static int ag71xx_ring_rx_init(struct ag71xx *ag)
181 struct ag71xx_ring *ring = &ag->rx_ring;
186 for (i = 0; i < AG71XX_RX_RING_SIZE; i++)
187 ring->descs[i].next = (u32) (ring->descs_dma +
188 sizeof(*ring->descs) * ((i + 1) % AG71XX_RX_RING_SIZE));
190 for (i = 0; i < AG71XX_RX_RING_SIZE; i++) {
193 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE);
200 skb_reserve(skb, AG71XX_RX_PKT_RESERVE);
202 ring->buf[i].skb = skb;
203 ring->descs[i].data = virt_to_phys(skb->data);
204 ring->descs[i].ctrl = DESC_EMPTY;
207 /* flush descriptors */
216 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
218 struct ag71xx_ring *ring = &ag->rx_ring;
222 for (; ring->curr - ring->dirty > 0; ring->dirty++) {
225 i = ring->dirty % AG71XX_RX_RING_SIZE;
227 if (ring->buf[i].skb == NULL) {
230 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE);
232 printk(KERN_ERR "%s: no memory for skb\n",
237 skb_reserve(skb, AG71XX_RX_PKT_RESERVE);
239 ring->buf[i].skb = skb;
240 ring->descs[i].data = virt_to_phys(skb->data);
243 ring->descs[i].ctrl = DESC_EMPTY;
247 /* flush descriptors */
250 DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
255 static int ag71xx_rings_init(struct ag71xx *ag)
259 ret = ag71xx_ring_alloc(&ag->tx_ring, AG71XX_TX_RING_SIZE);
263 ag71xx_ring_tx_init(ag);
265 ret = ag71xx_ring_alloc(&ag->rx_ring, AG71XX_RX_RING_SIZE);
269 ret = ag71xx_ring_rx_init(ag);
273 static void ag71xx_rings_cleanup(struct ag71xx *ag)
275 ag71xx_ring_rx_clean(ag);
276 ag71xx_ring_free(&ag->rx_ring);
278 ag71xx_ring_tx_clean(ag);
279 ag71xx_ring_free(&ag->tx_ring);
282 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
286 t = (((u32) mac[0]) << 24) | (((u32) mac[1]) << 16)
287 | (((u32) mac[2]) << 8) | ((u32) mac[3]);
289 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
291 t = (((u32) mac[4]) << 24) | (((u32) mac[5]) << 16);
292 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
295 #define AR71XX_MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
296 MAC_CFG1_SRX | MAC_CFG1_STX)
297 #define AR71XX_FIFO_CFG5_INIT 0x0007ffef
299 #define AR91XX_MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
300 MAC_CFG1_SRX | MAC_CFG1_STX | \
301 MAC_CFG1_TFC | MAC_CFG1_RFC)
302 #define AR91XX_FIFO_CFG5_INIT 0x0007efef
304 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
306 static void ag71xx_dma_reset(struct ag71xx *ag)
310 ag71xx_dump_dma_regs(ag);
313 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
314 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
316 /* clear descriptor addresses */
317 ag71xx_wr(ag, AG71XX_REG_TX_DESC, 0);
318 ag71xx_wr(ag, AG71XX_REG_RX_DESC, 0);
320 /* clear pending RX/TX interrupts */
321 for (i = 0; i < 256; i++) {
322 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
323 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
326 /* clear pending errors */
327 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
328 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
330 if (ag71xx_rr(ag, AG71XX_REG_RX_STATUS))
331 printk(KERN_ALERT "%s: unable to clear DMA Rx status\n",
334 if (ag71xx_rr(ag, AG71XX_REG_TX_STATUS))
335 printk(KERN_ALERT "%s: unable to clear DMA Tx status\n",
338 ag71xx_dump_dma_regs(ag);
341 static void ag71xx_hw_init(struct ag71xx *ag)
343 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
345 ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
348 ar71xx_device_stop(pdata->reset_bit);
350 ar71xx_device_start(pdata->reset_bit);
353 /* setup MAC configuration registers */
354 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1,
355 pdata->is_ar91xx ? AR91XX_MAC_CFG1_INIT : AR71XX_MAC_CFG1_INIT);
356 ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
357 MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
359 /* setup max frame length */
360 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, AG71XX_TX_MTU_LEN);
362 /* setup MII interface type */
363 ag71xx_mii_ctrl_set_if(ag, pdata->mii_if);
365 /* setup FIFO configuration registers */
366 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
367 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
368 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
369 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, 0x0000ffff);
370 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5,
371 pdata->is_ar91xx ? AR91XX_FIFO_CFG5_INIT
372 : AR71XX_FIFO_CFG5_INIT);
374 ag71xx_dma_reset(ag);
377 static void ag71xx_hw_start(struct ag71xx *ag)
379 /* start RX engine */
380 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
382 /* enable interrupts */
383 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
386 static void ag71xx_hw_stop(struct ag71xx *ag)
388 /* disable all interrupts */
389 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
391 ag71xx_dma_reset(ag);
394 static int ag71xx_open(struct net_device *dev)
396 struct ag71xx *ag = netdev_priv(dev);
399 ret = ag71xx_rings_init(ag);
403 napi_enable(&ag->napi);
405 netif_carrier_off(dev);
406 ag71xx_phy_start(ag);
408 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
409 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
411 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
415 netif_start_queue(dev);
420 ag71xx_rings_cleanup(ag);
424 static int ag71xx_stop(struct net_device *dev)
426 struct ag71xx *ag = netdev_priv(dev);
429 spin_lock_irqsave(&ag->lock, flags);
431 netif_stop_queue(dev);
435 netif_carrier_off(dev);
438 napi_disable(&ag->napi);
440 spin_unlock_irqrestore(&ag->lock, flags);
442 ag71xx_rings_cleanup(ag);
447 static int ag71xx_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
449 struct ag71xx *ag = netdev_priv(dev);
450 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
451 struct ag71xx_ring *ring = &ag->tx_ring;
452 struct ag71xx_desc *desc;
456 i = ring->curr % AG71XX_TX_RING_SIZE;
457 desc = &ring->descs[i];
459 spin_lock_irqsave(&ag->lock, flags);
461 spin_unlock_irqrestore(&ag->lock, flags);
463 if (!ag71xx_desc_empty(desc))
467 DBG("%s: packet len is too small\n", ag->dev->name);
471 dma_cache_wback_inv((unsigned long)skb->data, skb->len);
473 ring->buf[i].skb = skb;
475 /* setup descriptor fields */
476 desc->data = virt_to_phys(skb->data);
477 desc->ctrl = (skb->len & DESC_PKTLEN_M);
479 /* flush descriptor */
483 if (ring->curr == (ring->dirty + AG71XX_TX_THRES_STOP)) {
484 DBG("%s: tx queue full\n", ag->dev->name);
485 netif_stop_queue(dev);
488 DBG("%s: packet injected into TX queue\n", ag->dev->name);
490 /* enable TX engine */
491 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
493 dev->trans_start = jiffies;
498 dev->stats.tx_dropped++;
504 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
506 struct mii_ioctl_data *data = (struct mii_ioctl_data *) &ifr->ifr_data;
507 struct ag71xx *ag = netdev_priv(dev);
512 if (ag->phy_dev == NULL)
515 spin_lock_irq(&ag->lock);
516 ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
517 spin_unlock_irq(&ag->lock);
522 (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
528 (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
535 if (ag->phy_dev == NULL)
538 return phy_mii_ioctl(ag->phy_dev, data, cmd);
547 static void ag71xx_tx_packets(struct ag71xx *ag)
549 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
550 struct ag71xx_ring *ring = &ag->tx_ring;
553 DBG("%s: processing TX ring\n", ag->dev->name);
555 #ifdef AG71XX_NAPI_TX
560 while (ring->dirty != ring->curr) {
561 unsigned int i = ring->dirty % AG71XX_TX_RING_SIZE;
562 struct ag71xx_desc *desc = &ring->descs[i];
563 struct sk_buff *skb = ring->buf[i].skb;
565 if (!ag71xx_desc_empty(desc))
568 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
570 ag->dev->stats.tx_bytes += skb->len;
571 ag->dev->stats.tx_packets++;
573 dev_kfree_skb_any(skb);
574 ring->buf[i].skb = NULL;
580 DBG("%s: %d packets sent out\n", ag->dev->name, sent);
582 if ((ring->curr - ring->dirty) < AG71XX_TX_THRES_WAKEUP)
583 netif_wake_queue(ag->dev);
587 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
589 struct net_device *dev = ag->dev;
590 struct ag71xx_ring *ring = &ag->rx_ring;
591 #ifndef AG71XX_NAPI_TX
592 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
597 #ifndef AG71XX_NAPI_TX
598 spin_lock_irqsave(&ag->lock, flags);
600 spin_unlock_irqrestore(&ag->lock, flags);
603 DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
604 dev->name, limit, ring->curr, ring->dirty);
606 while (done < limit) {
607 unsigned int i = ring->curr % AG71XX_RX_RING_SIZE;
608 struct ag71xx_desc *desc = &ring->descs[i];
612 if (ag71xx_desc_empty(desc))
615 if ((ring->dirty + AG71XX_RX_RING_SIZE) == ring->curr) {
620 skb = ring->buf[i].skb;
621 pktlen = ag71xx_desc_pktlen(desc);
622 pktlen -= ETH_FCS_LEN;
624 /* TODO: move it into the refill function */
625 dma_cache_wback_inv((unsigned long)skb->data, pktlen);
626 skb_put(skb, pktlen);
629 skb->protocol = eth_type_trans(skb, dev);
630 skb->ip_summed = CHECKSUM_UNNECESSARY;
632 netif_receive_skb(skb);
634 dev->last_rx = jiffies;
635 dev->stats.rx_packets++;
636 dev->stats.rx_bytes += pktlen;
638 ring->buf[i].skb = NULL;
641 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
644 if ((ring->curr - ring->dirty) > (AG71XX_RX_RING_SIZE / 4))
645 ag71xx_ring_rx_refill(ag);
648 ag71xx_ring_rx_refill(ag);
650 DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
651 dev->name, ring->curr, ring->dirty, done);
656 static int ag71xx_poll(struct napi_struct *napi, int limit)
658 struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
659 #ifdef AG71XX_NAPI_TX
660 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
662 struct net_device *dev = ag->dev;
667 #ifdef AG71XX_NAPI_TX
669 ag71xx_tx_packets(ag);
672 DBG("%s: processing RX ring\n", dev->name);
673 done = ag71xx_rx_packets(ag, limit);
675 /* TODO: add OOM handler */
677 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
678 status &= AG71XX_INT_POLL;
680 if ((done < limit) && (!status)) {
681 DBG("%s: disable polling mode, done=%d, status=%x\n",
682 dev->name, done, status);
684 netif_rx_complete(dev, napi);
686 /* enable interrupts */
687 spin_lock_irqsave(&ag->lock, flags);
688 ag71xx_int_enable(ag, AG71XX_INT_POLL);
689 spin_unlock_irqrestore(&ag->lock, flags);
693 if (status & AG71XX_INT_RX_OF) {
694 if (netif_msg_rx_err(ag))
695 printk(KERN_ALERT "%s: rx owerflow, restarting dma\n",
699 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
701 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
704 DBG("%s: stay in polling mode, done=%d, status=%x\n",
705 dev->name, done, status);
709 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
711 struct net_device *dev = dev_id;
712 struct ag71xx *ag = netdev_priv(dev);
715 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
716 ag71xx_dump_intr(ag, "raw", status);
717 status &= ag71xx_rr(ag, AG71XX_REG_INT_ENABLE);
718 ag71xx_dump_intr(ag, "masked", status);
720 if (unlikely(!status))
723 if (unlikely(status & AG71XX_INT_ERR)) {
724 if (status & AG71XX_INT_TX_BE) {
725 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
726 dev_err(&dev->dev, "TX BUS error\n");
728 if (status & AG71XX_INT_RX_BE) {
729 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
730 dev_err(&dev->dev, "RX BUS error\n");
735 if (unlikely(status & AG71XX_INT_TX_UR)) {
736 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_UR);
737 DBG("%s: TX underrun\n", dev->name);
741 #ifndef AG71XX_NAPI_TX
742 if (likely(status & AG71XX_INT_TX_PS))
743 ag71xx_tx_packets(ag);
746 if (likely(status & AG71XX_INT_POLL)) {
747 ag71xx_int_disable(ag, AG71XX_INT_POLL);
748 DBG("%s: enable polling mode\n", dev->name);
749 netif_rx_schedule(dev, &ag->napi);
755 static void ag71xx_set_multicast_list(struct net_device *dev)
760 static int __init ag71xx_probe(struct platform_device *pdev)
762 struct net_device *dev;
763 struct resource *res;
765 struct ag71xx_platform_data *pdata;
768 pdata = pdev->dev.platform_data;
770 dev_err(&pdev->dev, "no platform data specified\n");
775 dev = alloc_etherdev(sizeof(*ag));
777 dev_err(&pdev->dev, "alloc_etherdev failed\n");
782 SET_NETDEV_DEV(dev, &pdev->dev);
784 ag = netdev_priv(dev);
787 ag->mii_bus = &ag71xx_mdio_bus->mii_bus;
788 ag->msg_enable = netif_msg_init(ag71xx_debug,
789 AG71XX_DEFAULT_MSG_ENABLE);
790 spin_lock_init(&ag->lock);
792 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
794 dev_err(&pdev->dev, "no mac_base resource found\n");
799 ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1);
801 dev_err(&pdev->dev, "unable to ioremap mac_base\n");
806 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base2");
808 dev_err(&pdev->dev, "no mac_base2 resource found\n");
810 goto err_unmap_base1;
813 ag->mac_base2 = ioremap_nocache(res->start, res->end - res->start + 1);
815 dev_err(&pdev->dev, "unable to ioremap mac_base2\n");
817 goto err_unmap_base1;
820 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mii_ctrl");
822 dev_err(&pdev->dev, "no mii_ctrl resource found\n");
824 goto err_unmap_base2;
827 ag->mii_ctrl = ioremap_nocache(res->start, res->end - res->start + 1);
829 dev_err(&pdev->dev, "unable to ioremap mii_ctrl\n");
831 goto err_unmap_base2;
834 dev->irq = platform_get_irq(pdev, 0);
835 err = request_irq(dev->irq, ag71xx_interrupt,
836 IRQF_DISABLED | IRQF_SAMPLE_RANDOM,
839 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
840 goto err_unmap_mii_ctrl;
843 dev->base_addr = (unsigned long)ag->mac_base;
844 dev->open = ag71xx_open;
845 dev->stop = ag71xx_stop;
846 dev->hard_start_xmit = ag71xx_hard_start_xmit;
847 dev->set_multicast_list = ag71xx_set_multicast_list;
848 dev->do_ioctl = ag71xx_do_ioctl;
849 dev->ethtool_ops = &ag71xx_ethtool_ops;
851 netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
853 if (is_valid_ether_addr(pdata->mac_addr))
854 memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
856 dev->dev_addr[0] = 0xde;
857 dev->dev_addr[1] = 0xad;
858 get_random_bytes(&dev->dev_addr[2], 3);
859 dev->dev_addr[5] = pdev->id & 0xff;
862 err = register_netdev(dev);
864 dev_err(&pdev->dev, "unable to register net device\n");
868 printk(KERN_INFO "%s: Atheros AG71xx at 0x%08lx, irq %d\n",
869 dev->name, dev->base_addr, dev->irq);
871 ag71xx_dump_regs(ag);
875 ag71xx_dump_regs(ag);
877 /* Reset the mdio bus explicitly */
879 mutex_lock(&ag->mii_bus->mdio_lock);
880 ag->mii_bus->reset(ag->mii_bus);
881 mutex_unlock(&ag->mii_bus->mdio_lock);
884 err = ag71xx_phy_connect(ag);
886 goto err_unregister_netdev;
888 platform_set_drvdata(pdev, dev);
892 err_unregister_netdev:
893 unregister_netdev(dev);
895 free_irq(dev->irq, dev);
897 iounmap(ag->mii_ctrl);
899 iounmap(ag->mac_base2);
901 iounmap(ag->mac_base);
905 platform_set_drvdata(pdev, NULL);
909 static int __exit ag71xx_remove(struct platform_device *pdev)
911 struct net_device *dev = platform_get_drvdata(pdev);
914 struct ag71xx *ag = netdev_priv(dev);
916 ag71xx_phy_disconnect(ag);
917 unregister_netdev(dev);
918 free_irq(dev->irq, dev);
919 iounmap(ag->mii_ctrl);
920 iounmap(ag->mac_base2);
921 iounmap(ag->mac_base);
923 platform_set_drvdata(pdev, NULL);
929 static struct platform_driver ag71xx_driver = {
930 .probe = ag71xx_probe,
931 .remove = __exit_p(ag71xx_remove),
933 .name = AG71XX_DRV_NAME,
937 static int __init ag71xx_module_init(void)
941 ret = ag71xx_mdio_driver_init();
945 ret = platform_driver_register(&ag71xx_driver);
952 ag71xx_mdio_driver_exit();
957 static void __exit ag71xx_module_exit(void)
959 platform_driver_unregister(&ag71xx_driver);
960 ag71xx_mdio_driver_exit();
963 module_init(ag71xx_module_init);
964 module_exit(ag71xx_module_exit);
966 MODULE_VERSION(AG71XX_DRV_VERSION);
967 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
968 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
969 MODULE_LICENSE("GPL v2");
970 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);