2 * Atheros AR71xx built-in ethernet mac driver
4 * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 * Based on Atheros' AG7100 driver
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
16 #define AG71XX_DEFAULT_MSG_ENABLE \
26 static int ag71xx_debug = -1;
28 module_param(ag71xx_debug, int, 0);
29 MODULE_PARM_DESC(ag71xx_debug, "Debug level (-1=defaults,0=none,...,16=all)");
31 static void ag71xx_dump_regs(struct ag71xx *ag)
33 DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
35 ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
36 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
37 ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
38 ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
39 ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
40 DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
42 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
43 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
44 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
45 DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
47 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
48 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
49 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
50 DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
52 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
53 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
54 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
57 static void ag71xx_ring_free(struct ag71xx_ring *ring)
62 dma_free_coherent(NULL, ring->size * sizeof(*ring->descs),
63 ring->descs, ring->descs_dma);
66 static int ag71xx_ring_alloc(struct ag71xx_ring *ring, unsigned int size)
70 ring->descs = dma_alloc_coherent(NULL, size * sizeof(*ring->descs),
80 ring->buf = kzalloc(size * sizeof(*ring->buf), GFP_KERNEL);
92 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
94 struct ag71xx_ring *ring = &ag->tx_ring;
95 struct net_device *dev = ag->dev;
97 while (ring->curr != ring->dirty) {
98 u32 i = ring->dirty % AG71XX_TX_RING_SIZE;
100 if (!ag71xx_desc_empty(&ring->descs[i])) {
101 ring->descs[i].ctrl = 0;
102 dev->stats.tx_errors++;
105 if (ring->buf[i].skb)
106 dev_kfree_skb_any(ring->buf[i].skb);
108 ring->buf[i].skb = NULL;
113 /* flush descriptors */
118 static void ag71xx_ring_tx_init(struct ag71xx *ag)
120 struct ag71xx_ring *ring = &ag->tx_ring;
123 for (i = 0; i < AG71XX_TX_RING_SIZE; i++) {
124 ring->descs[i].next = (u32) (ring->descs_dma +
125 sizeof(*ring->descs) * ((i + 1) % AG71XX_TX_RING_SIZE));
127 ring->descs[i].ctrl = DESC_EMPTY;
128 ring->buf[i].skb = NULL;
131 /* flush descriptors */
138 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
140 struct ag71xx_ring *ring = &ag->rx_ring;
146 for (i = 0; i < AG71XX_RX_RING_SIZE; i++)
147 if (ring->buf[i].skb)
148 kfree_skb(ring->buf[i].skb);
152 static int ag71xx_ring_rx_init(struct ag71xx *ag)
154 struct ag71xx_ring *ring = &ag->rx_ring;
159 for (i = 0; i < AG71XX_RX_RING_SIZE; i++)
160 ring->descs[i].next = (u32) (ring->descs_dma +
161 sizeof(*ring->descs) * ((i + 1) % AG71XX_RX_RING_SIZE));
163 for (i = 0; i < AG71XX_RX_RING_SIZE; i++) {
166 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE);
173 skb_reserve(skb, AG71XX_RX_PKT_RESERVE);
175 ring->buf[i].skb = skb;
176 ring->descs[i].data = virt_to_phys(skb->data);
177 ring->descs[i].ctrl = DESC_EMPTY;
180 /* flush descriptors */
189 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
191 struct ag71xx_ring *ring = &ag->rx_ring;
195 for (; ring->curr - ring->dirty > 0; ring->dirty++) {
198 i = ring->dirty % AG71XX_RX_RING_SIZE;
200 if (ring->buf[i].skb == NULL) {
203 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE);
205 printk(KERN_ERR "%s: no memory for skb\n",
210 skb_reserve(skb, AG71XX_RX_PKT_RESERVE);
212 ring->buf[i].skb = skb;
213 ring->descs[i].data = virt_to_phys(skb->data);
216 ring->descs[i].ctrl = DESC_EMPTY;
220 /* flush descriptors */
223 DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
228 static int ag71xx_rings_init(struct ag71xx *ag)
232 ret = ag71xx_ring_alloc(&ag->tx_ring, AG71XX_TX_RING_SIZE);
236 ag71xx_ring_tx_init(ag);
238 ret = ag71xx_ring_alloc(&ag->rx_ring, AG71XX_RX_RING_SIZE);
242 ret = ag71xx_ring_rx_init(ag);
246 static void ag71xx_rings_cleanup(struct ag71xx *ag)
248 ag71xx_ring_rx_clean(ag);
249 ag71xx_ring_free(&ag->rx_ring);
251 ag71xx_ring_tx_clean(ag);
252 ag71xx_ring_free(&ag->tx_ring);
255 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
259 t = (((u32) mac[0]) << 24) | (((u32) mac[1]) << 16)
260 | (((u32) mac[2]) << 8) | ((u32) mac[2]);
262 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
264 t = (((u32) mac[4]) << 24) | (((u32) mac[5]) << 16);
265 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
268 #define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | MAC_CFG1_SRX \
271 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
273 static void ag71xx_hw_init(struct ag71xx *ag)
275 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
277 ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
280 ar71xx_device_stop(pdata->reset_bit);
282 ar71xx_device_start(pdata->reset_bit);
285 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT);
287 /* TODO: set max packet size */
289 ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
290 MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
292 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
294 ag71xx_mii_ctrl_set_if(ag, pdata->mii_if);
296 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
297 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
298 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, 0x0000ffff);
299 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, 0x0007ffef);
302 static void ag71xx_hw_start(struct ag71xx *ag)
304 /* start RX engine */
305 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
307 /* enable interrupts */
308 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
311 static void ag71xx_hw_stop(struct ag71xx *ag)
314 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
315 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
317 /* disable all interrupts */
318 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
321 static int ag71xx_open(struct net_device *dev)
323 struct ag71xx *ag = netdev_priv(dev);
326 ret = ag71xx_rings_init(ag);
330 napi_enable(&ag->napi);
332 netif_carrier_off(dev);
333 ag71xx_phy_start(ag);
335 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
336 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
338 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
342 netif_start_queue(dev);
347 ag71xx_rings_cleanup(ag);
351 static int ag71xx_stop(struct net_device *dev)
353 struct ag71xx *ag = netdev_priv(dev);
356 spin_lock_irqsave(&ag->lock, flags);
358 netif_stop_queue(dev);
362 netif_carrier_off(dev);
365 napi_disable(&ag->napi);
367 spin_unlock_irqrestore(&ag->lock, flags);
369 ag71xx_rings_cleanup(ag);
374 static int ag71xx_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
376 struct ag71xx *ag = netdev_priv(dev);
377 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
378 struct ag71xx_ring *ring = &ag->tx_ring;
379 struct ag71xx_desc *desc;
383 i = ring->curr % AG71XX_TX_RING_SIZE;
384 desc = &ring->descs[i];
386 spin_lock_irqsave(&ag->lock, flags);
388 spin_unlock_irqrestore(&ag->lock, flags);
390 if (!ag71xx_desc_empty(desc))
394 DBG("%s: packet len is too small\n", ag->dev->name);
398 dma_cache_wback_inv((unsigned long)skb->data, skb->len);
400 ring->buf[i].skb = skb;
402 /* setup descriptor fields */
403 desc->data = virt_to_phys(skb->data);
404 desc->ctrl = (skb->len & DESC_PKTLEN_M);
406 /* flush descriptor */
410 if (ring->curr == (ring->dirty + AG71XX_TX_THRES_STOP)) {
411 DBG("%s: tx queue full\n", ag->dev->name);
412 netif_stop_queue(dev);
415 DBG("%s: packet injected into TX queue\n", ag->dev->name);
417 /* enable TX engine */
418 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
420 dev->trans_start = jiffies;
425 dev->stats.tx_dropped++;
431 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
433 struct mii_ioctl_data *data = (struct mii_ioctl_data *) &ifr->ifr_data;
434 struct ag71xx *ag = netdev_priv(dev);
439 if (ag->phy_dev == NULL)
442 spin_lock_irq(&ag->lock);
443 ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
444 spin_unlock_irq(&ag->lock);
449 (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
455 (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
462 if (ag->phy_dev == NULL)
465 return phy_mii_ioctl(ag->phy_dev, data, cmd);
474 static void ag71xx_tx_packets(struct ag71xx *ag)
476 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
477 struct ag71xx_ring *ring = &ag->tx_ring;
480 DBG("%s: processing TX ring\n", ag->dev->name);
482 #ifdef AG71XX_NAPI_TX
487 while (ring->dirty != ring->curr) {
488 unsigned int i = ring->dirty % AG71XX_TX_RING_SIZE;
489 struct ag71xx_desc *desc = &ring->descs[i];
490 struct sk_buff *skb = ring->buf[i].skb;
492 if (!ag71xx_desc_empty(desc))
495 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
497 ag->dev->stats.tx_bytes += skb->len;
498 ag->dev->stats.tx_packets++;
500 dev_kfree_skb_any(skb);
501 ring->buf[i].skb = NULL;
507 DBG("%s: %d packets sent out\n", ag->dev->name, sent);
509 if ((ring->curr - ring->dirty) < AG71XX_TX_THRES_WAKEUP)
510 netif_wake_queue(ag->dev);
514 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
516 struct net_device *dev = ag->dev;
517 struct ag71xx_ring *ring = &ag->rx_ring;
518 #ifndef AG71XX_NAPI_TX
519 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
524 #ifndef AG71XX_NAPI_TX
525 spin_lock_irqsave(&ag->lock, flags);
527 spin_unlock_irqrestore(&ag->lock, flags);
530 DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
531 dev->name, limit, ring->curr, ring->dirty);
533 while (done < limit) {
534 unsigned int i = ring->curr % AG71XX_RX_RING_SIZE;
535 struct ag71xx_desc *desc = &ring->descs[i];
539 if (ag71xx_desc_empty(desc))
542 if ((ring->dirty + AG71XX_RX_RING_SIZE) == ring->curr) {
547 skb = ring->buf[i].skb;
548 pktlen = ag71xx_desc_pktlen(desc);
549 pktlen -= ETH_FCS_LEN;
551 /* TODO: move it into the refill function */
552 dma_cache_wback_inv((unsigned long)skb->data, pktlen);
553 skb_put(skb, pktlen);
556 skb->protocol = eth_type_trans(skb, dev);
557 skb->ip_summed = CHECKSUM_UNNECESSARY;
559 netif_receive_skb(skb);
561 dev->last_rx = jiffies;
562 dev->stats.rx_packets++;
563 dev->stats.rx_bytes += pktlen;
565 ring->buf[i].skb = NULL;
568 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
571 if ((ring->curr - ring->dirty) > (AG71XX_RX_RING_SIZE / 4))
572 ag71xx_ring_rx_refill(ag);
575 ag71xx_ring_rx_refill(ag);
577 DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
578 dev->name, ring->curr, ring->dirty, done);
583 static int ag71xx_poll(struct napi_struct *napi, int limit)
585 struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
586 #ifdef AG71XX_NAPI_TX
587 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
589 struct net_device *dev = ag->dev;
594 #ifdef AG71XX_NAPI_TX
596 ag71xx_tx_packets(ag);
599 DBG("%s: processing RX ring\n", dev->name);
600 done = ag71xx_rx_packets(ag, limit);
602 /* TODO: add OOM handler */
604 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
605 status &= AG71XX_INT_POLL;
607 if ((done < limit) && (!status)) {
608 DBG("%s: disable polling mode, done=%d, status=%x\n",
609 dev->name, done, status);
611 netif_rx_complete(dev, napi);
613 /* enable interrupts */
614 spin_lock_irqsave(&ag->lock, flags);
615 ag71xx_int_enable(ag, AG71XX_INT_POLL);
616 spin_unlock_irqrestore(&ag->lock, flags);
620 if (status & AG71XX_INT_RX_OF) {
621 if (netif_msg_rx_err(ag))
622 printk(KERN_ALERT "%s: rx owerflow, restarting dma\n",
626 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
628 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
631 DBG("%s: stay in polling mode, done=%d, status=%x\n",
632 dev->name, done, status);
636 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
638 struct net_device *dev = dev_id;
639 struct ag71xx *ag = netdev_priv(dev);
642 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
643 status &= ag71xx_rr(ag, AG71XX_REG_INT_ENABLE);
645 if (unlikely(!status))
648 if (unlikely(status & AG71XX_INT_ERR)) {
649 if (status & AG71XX_INT_TX_BE) {
650 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
651 dev_err(&dev->dev, "TX BUS error\n");
653 if (status & AG71XX_INT_RX_BE) {
654 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
655 dev_err(&dev->dev, "RX BUS error\n");
660 if (unlikely(status & AG71XX_INT_TX_UR)) {
661 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_UR);
662 DBG("%s: TX underrun\n", dev->name);
666 #ifndef AG71XX_NAPI_TX
667 if (likely(status & AG71XX_INT_TX_PS))
668 ag71xx_tx_packets(ag);
671 if (likely(status & AG71XX_INT_POLL)) {
672 ag71xx_int_disable(ag, AG71XX_INT_POLL);
673 DBG("%s: enable polling mode\n", dev->name);
674 netif_rx_schedule(dev, &ag->napi);
680 static void ag71xx_set_multicast_list(struct net_device *dev)
685 static int __init ag71xx_probe(struct platform_device *pdev)
687 struct net_device *dev;
688 struct resource *res;
690 struct ag71xx_platform_data *pdata;
693 pdata = pdev->dev.platform_data;
695 dev_err(&pdev->dev, "no platform data specified\n");
700 dev = alloc_etherdev(sizeof(*ag));
702 dev_err(&pdev->dev, "alloc_etherdev failed\n");
707 SET_NETDEV_DEV(dev, &pdev->dev);
709 ag = netdev_priv(dev);
712 ag->mii_bus = &ag71xx_mdio_bus->mii_bus;
713 ag->msg_enable = netif_msg_init(ag71xx_debug,
714 AG71XX_DEFAULT_MSG_ENABLE);
715 spin_lock_init(&ag->lock);
717 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
719 dev_err(&pdev->dev, "no mac_base resource found\n");
724 ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1);
726 dev_err(&pdev->dev, "unable to ioremap mac_base\n");
731 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base2");
733 dev_err(&pdev->dev, "no mac_base2 resource found\n");
735 goto err_unmap_base1;
738 ag->mac_base2 = ioremap_nocache(res->start, res->end - res->start + 1);
740 dev_err(&pdev->dev, "unable to ioremap mac_base2\n");
742 goto err_unmap_base1;
745 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mii_ctrl");
747 dev_err(&pdev->dev, "no mii_ctrl resource found\n");
749 goto err_unmap_base2;
752 ag->mii_ctrl = ioremap_nocache(res->start, res->end - res->start + 1);
754 dev_err(&pdev->dev, "unable to ioremap mii_ctrl\n");
756 goto err_unmap_base2;
759 dev->irq = platform_get_irq(pdev, 0);
760 err = request_irq(dev->irq, ag71xx_interrupt,
761 IRQF_DISABLED | IRQF_SAMPLE_RANDOM,
764 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
765 goto err_unmap_mii_ctrl;
768 dev->base_addr = (unsigned long)ag->mac_base;
769 dev->open = ag71xx_open;
770 dev->stop = ag71xx_stop;
771 dev->hard_start_xmit = ag71xx_hard_start_xmit;
772 dev->set_multicast_list = ag71xx_set_multicast_list;
773 dev->do_ioctl = ag71xx_do_ioctl;
774 dev->ethtool_ops = &ag71xx_ethtool_ops;
776 netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
778 if (is_valid_ether_addr(pdata->mac_addr))
779 memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
781 dev->dev_addr[0] = 0xde;
782 dev->dev_addr[1] = 0xad;
783 get_random_bytes(&dev->dev_addr[2], 3);
784 dev->dev_addr[5] = pdev->id & 0xff;
787 err = register_netdev(dev);
789 dev_err(&pdev->dev, "unable to register net device\n");
793 printk(KERN_INFO "%s: Atheros AG71xx at 0x%08lx, irq %d\n",
794 dev->name, dev->base_addr, dev->irq);
796 ag71xx_dump_regs(ag);
800 ag71xx_dump_regs(ag);
802 /* Reset the mdio bus explicitly */
804 mutex_lock(&ag->mii_bus->mdio_lock);
805 ag->mii_bus->reset(ag->mii_bus);
806 mutex_unlock(&ag->mii_bus->mdio_lock);
809 err = ag71xx_phy_connect(ag);
811 goto err_unregister_netdev;
813 platform_set_drvdata(pdev, dev);
817 err_unregister_netdev:
818 unregister_netdev(dev);
820 free_irq(dev->irq, dev);
822 iounmap(ag->mii_ctrl);
824 iounmap(ag->mac_base2);
826 iounmap(ag->mac_base);
830 platform_set_drvdata(pdev, NULL);
834 static int __exit ag71xx_remove(struct platform_device *pdev)
836 struct net_device *dev = platform_get_drvdata(pdev);
839 struct ag71xx *ag = netdev_priv(dev);
841 ag71xx_phy_disconnect(ag);
842 unregister_netdev(dev);
843 free_irq(dev->irq, dev);
844 iounmap(ag->mii_ctrl);
845 iounmap(ag->mac_base2);
846 iounmap(ag->mac_base);
848 platform_set_drvdata(pdev, NULL);
854 static struct platform_driver ag71xx_driver = {
855 .probe = ag71xx_probe,
856 .remove = __exit_p(ag71xx_remove),
858 .name = AG71XX_DRV_NAME,
862 static int __init ag71xx_module_init(void)
866 ret = ag71xx_mdio_driver_init();
870 ret = platform_driver_register(&ag71xx_driver);
877 ag71xx_mdio_driver_exit();
882 static void __exit ag71xx_module_exit(void)
884 platform_driver_unregister(&ag71xx_driver);
885 ag71xx_mdio_driver_exit();
888 module_init(ag71xx_module_init);
889 module_exit(ag71xx_module_exit);
891 MODULE_VERSION(AG71XX_DRV_VERSION);
892 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
893 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
894 MODULE_LICENSE("GPL v2");
895 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);