2 * Driver for the built-in ethernet switch of the Atheros AR7240 SoC
3 * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
4 * Copyright (c) 2010 Felix Fietkau <nbd@openwrt.org>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
12 #include <linux/etherdevice.h>
13 #include <linux/list.h>
14 #include <linux/netdevice.h>
15 #include <linux/phy.h>
16 #include <linux/mii.h>
17 #include <linux/bitops.h>
18 #include <linux/switch.h>
21 #define BITM(_count) (BIT(_count) - 1)
22 #define BITS(_shift, _count) (BITM(_count) << _shift)
24 #define AR7240_REG_MASK_CTRL 0x00
25 #define AR7240_MASK_CTRL_REVISION_M BITM(8)
26 #define AR7240_MASK_CTRL_VERSION_M BITM(8)
27 #define AR7240_MASK_CTRL_VERSION_S 8
28 #define AR7240_MASK_CTRL_VERSION_AR7240 0x01
29 #define AR7240_MASK_CTRL_VERSION_AR934X 0x02
30 #define AR7240_MASK_CTRL_SOFT_RESET BIT(31)
32 #define AR7240_REG_MAC_ADDR0 0x20
33 #define AR7240_REG_MAC_ADDR1 0x24
35 #define AR7240_REG_FLOOD_MASK 0x2c
36 #define AR7240_FLOOD_MASK_BROAD_TO_CPU BIT(26)
38 #define AR7240_REG_GLOBAL_CTRL 0x30
39 #define AR7240_GLOBAL_CTRL_MTU_M BITM(12)
41 #define AR7240_REG_VTU 0x0040
42 #define AR7240_VTU_OP BITM(3)
43 #define AR7240_VTU_OP_NOOP 0x0
44 #define AR7240_VTU_OP_FLUSH 0x1
45 #define AR7240_VTU_OP_LOAD 0x2
46 #define AR7240_VTU_OP_PURGE 0x3
47 #define AR7240_VTU_OP_REMOVE_PORT 0x4
48 #define AR7240_VTU_ACTIVE BIT(3)
49 #define AR7240_VTU_FULL BIT(4)
50 #define AR7240_VTU_PORT BITS(8, 4)
51 #define AR7240_VTU_PORT_S 8
52 #define AR7240_VTU_VID BITS(16, 12)
53 #define AR7240_VTU_VID_S 16
54 #define AR7240_VTU_PRIO BITS(28, 3)
55 #define AR7240_VTU_PRIO_S 28
56 #define AR7240_VTU_PRIO_EN BIT(31)
58 #define AR7240_REG_VTU_DATA 0x0044
59 #define AR7240_VTUDATA_MEMBER BITS(0, 10)
60 #define AR7240_VTUDATA_VALID BIT(11)
62 #define AR7240_REG_ATU 0x50
63 #define AR7240_ATU_FLUSH_ALL 0x1
65 #define AR7240_REG_AT_CTRL 0x5c
66 #define AR7240_AT_CTRL_AGE_TIME BITS(0, 15)
67 #define AR7240_AT_CTRL_AGE_EN BIT(17)
68 #define AR7240_AT_CTRL_LEARN_CHANGE BIT(18)
69 #define AR7240_AT_CTRL_ARP_EN BIT(20)
71 #define AR7240_REG_TAG_PRIORITY 0x70
73 #define AR7240_REG_SERVICE_TAG 0x74
74 #define AR7240_SERVICE_TAG_M BITM(16)
76 #define AR7240_REG_CPU_PORT 0x78
77 #define AR7240_MIRROR_PORT_S 4
78 #define AR7240_CPU_PORT_EN BIT(8)
80 #define AR7240_REG_MIB_FUNCTION0 0x80
81 #define AR7240_MIB_TIMER_M BITM(16)
82 #define AR7240_MIB_AT_HALF_EN BIT(16)
83 #define AR7240_MIB_BUSY BIT(17)
84 #define AR7240_MIB_FUNC_S 24
85 #define AR7240_MIB_FUNC_NO_OP 0x0
86 #define AR7240_MIB_FUNC_FLUSH 0x1
87 #define AR7240_MIB_FUNC_CAPTURE 0x3
89 #define AR7240_REG_MDIO_CTRL 0x98
90 #define AR7240_MDIO_CTRL_DATA_M BITM(16)
91 #define AR7240_MDIO_CTRL_REG_ADDR_S 16
92 #define AR7240_MDIO_CTRL_PHY_ADDR_S 21
93 #define AR7240_MDIO_CTRL_CMD_WRITE 0
94 #define AR7240_MDIO_CTRL_CMD_READ BIT(27)
95 #define AR7240_MDIO_CTRL_MASTER_EN BIT(30)
96 #define AR7240_MDIO_CTRL_BUSY BIT(31)
98 #define AR7240_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
100 #define AR7240_REG_PORT_STATUS(_port) (AR7240_REG_PORT_BASE((_port)) + 0x00)
101 #define AR7240_PORT_STATUS_SPEED_S 0
102 #define AR7240_PORT_STATUS_SPEED_M BITM(2)
103 #define AR7240_PORT_STATUS_SPEED_10 0
104 #define AR7240_PORT_STATUS_SPEED_100 1
105 #define AR7240_PORT_STATUS_SPEED_1000 2
106 #define AR7240_PORT_STATUS_TXMAC BIT(2)
107 #define AR7240_PORT_STATUS_RXMAC BIT(3)
108 #define AR7240_PORT_STATUS_TXFLOW BIT(4)
109 #define AR7240_PORT_STATUS_RXFLOW BIT(5)
110 #define AR7240_PORT_STATUS_DUPLEX BIT(6)
111 #define AR7240_PORT_STATUS_LINK_UP BIT(8)
112 #define AR7240_PORT_STATUS_LINK_AUTO BIT(9)
113 #define AR7240_PORT_STATUS_LINK_PAUSE BIT(10)
115 #define AR7240_REG_PORT_CTRL(_port) (AR7240_REG_PORT_BASE((_port)) + 0x04)
116 #define AR7240_PORT_CTRL_STATE_M BITM(3)
117 #define AR7240_PORT_CTRL_STATE_DISABLED 0
118 #define AR7240_PORT_CTRL_STATE_BLOCK 1
119 #define AR7240_PORT_CTRL_STATE_LISTEN 2
120 #define AR7240_PORT_CTRL_STATE_LEARN 3
121 #define AR7240_PORT_CTRL_STATE_FORWARD 4
122 #define AR7240_PORT_CTRL_LEARN_LOCK BIT(7)
123 #define AR7240_PORT_CTRL_VLAN_MODE_S 8
124 #define AR7240_PORT_CTRL_VLAN_MODE_KEEP 0
125 #define AR7240_PORT_CTRL_VLAN_MODE_STRIP 1
126 #define AR7240_PORT_CTRL_VLAN_MODE_ADD 2
127 #define AR7240_PORT_CTRL_VLAN_MODE_DOUBLE_TAG 3
128 #define AR7240_PORT_CTRL_IGMP_SNOOP BIT(10)
129 #define AR7240_PORT_CTRL_HEADER BIT(11)
130 #define AR7240_PORT_CTRL_MAC_LOOP BIT(12)
131 #define AR7240_PORT_CTRL_SINGLE_VLAN BIT(13)
132 #define AR7240_PORT_CTRL_LEARN BIT(14)
133 #define AR7240_PORT_CTRL_DOUBLE_TAG BIT(15)
134 #define AR7240_PORT_CTRL_MIRROR_TX BIT(16)
135 #define AR7240_PORT_CTRL_MIRROR_RX BIT(17)
137 #define AR7240_REG_PORT_VLAN(_port) (AR7240_REG_PORT_BASE((_port)) + 0x08)
139 #define AR7240_PORT_VLAN_DEFAULT_ID_S 0
140 #define AR7240_PORT_VLAN_DEST_PORTS_S 16
141 #define AR7240_PORT_VLAN_MODE_S 30
142 #define AR7240_PORT_VLAN_MODE_PORT_ONLY 0
143 #define AR7240_PORT_VLAN_MODE_PORT_FALLBACK 1
144 #define AR7240_PORT_VLAN_MODE_VLAN_ONLY 2
145 #define AR7240_PORT_VLAN_MODE_SECURE 3
148 #define AR7240_REG_STATS_BASE(_port) (0x20000 + (_port) * 0x100)
150 #define AR7240_STATS_RXBROAD 0x00
151 #define AR7240_STATS_RXPAUSE 0x04
152 #define AR7240_STATS_RXMULTI 0x08
153 #define AR7240_STATS_RXFCSERR 0x0c
154 #define AR7240_STATS_RXALIGNERR 0x10
155 #define AR7240_STATS_RXRUNT 0x14
156 #define AR7240_STATS_RXFRAGMENT 0x18
157 #define AR7240_STATS_RX64BYTE 0x1c
158 #define AR7240_STATS_RX128BYTE 0x20
159 #define AR7240_STATS_RX256BYTE 0x24
160 #define AR7240_STATS_RX512BYTE 0x28
161 #define AR7240_STATS_RX1024BYTE 0x2c
162 #define AR7240_STATS_RX1518BYTE 0x30
163 #define AR7240_STATS_RXMAXBYTE 0x34
164 #define AR7240_STATS_RXTOOLONG 0x38
165 #define AR7240_STATS_RXGOODBYTE 0x3c
166 #define AR7240_STATS_RXBADBYTE 0x44
167 #define AR7240_STATS_RXOVERFLOW 0x4c
168 #define AR7240_STATS_FILTERED 0x50
169 #define AR7240_STATS_TXBROAD 0x54
170 #define AR7240_STATS_TXPAUSE 0x58
171 #define AR7240_STATS_TXMULTI 0x5c
172 #define AR7240_STATS_TXUNDERRUN 0x60
173 #define AR7240_STATS_TX64BYTE 0x64
174 #define AR7240_STATS_TX128BYTE 0x68
175 #define AR7240_STATS_TX256BYTE 0x6c
176 #define AR7240_STATS_TX512BYTE 0x70
177 #define AR7240_STATS_TX1024BYTE 0x74
178 #define AR7240_STATS_TX1518BYTE 0x78
179 #define AR7240_STATS_TXMAXBYTE 0x7c
180 #define AR7240_STATS_TXOVERSIZE 0x80
181 #define AR7240_STATS_TXBYTE 0x84
182 #define AR7240_STATS_TXCOLLISION 0x8c
183 #define AR7240_STATS_TXABORTCOL 0x90
184 #define AR7240_STATS_TXMULTICOL 0x94
185 #define AR7240_STATS_TXSINGLECOL 0x98
186 #define AR7240_STATS_TXEXCDEFER 0x9c
187 #define AR7240_STATS_TXDEFER 0xa0
188 #define AR7240_STATS_TXLATECOL 0xa4
190 #define AR7240_PORT_CPU 0
191 #define AR7240_NUM_PORTS 6
192 #define AR7240_NUM_PHYS 5
194 #define AR7240_PHY_ID1 0x004d
195 #define AR7240_PHY_ID2 0xd041
197 #define AR934X_PHY_ID1 0x004d
198 #define AR934X_PHY_ID2 0xd042
200 #define AR7240_MAX_VLANS 16
202 #define sw_to_ar7240(_dev) container_of(_dev, struct ar7240sw, swdev)
205 struct mii_bus *mii_bus;
206 struct ag71xx_switch_platform_data *swdata;
207 struct switch_dev swdev;
211 u16 vlan_id[AR7240_MAX_VLANS];
212 u8 vlan_table[AR7240_MAX_VLANS];
214 u16 pvid[AR7240_NUM_PORTS];
218 struct ar7240sw_hw_stat {
219 char string[ETH_GSTRING_LEN];
224 static DEFINE_MUTEX(reg_mutex);
226 static inline int sw_is_ar7240(struct ar7240sw *as)
228 return as->ver == AR7240_MASK_CTRL_VERSION_AR7240;
231 static inline int sw_is_ar934x(struct ar7240sw *as)
233 return as->ver == AR7240_MASK_CTRL_VERSION_AR934X;
236 static inline u32 ar7240sw_port_mask(struct ar7240sw *as, int port)
241 static inline u32 ar7240sw_port_mask_all(struct ar7240sw *as)
243 return BIT(as->swdev.ports) - 1;
246 static inline u32 ar7240sw_port_mask_but(struct ar7240sw *as, int port)
248 return ar7240sw_port_mask_all(as) & ~BIT(port);
251 static inline u16 mk_phy_addr(u32 reg)
253 return 0x17 & ((reg >> 4) | 0x10);
256 static inline u16 mk_phy_reg(u32 reg)
258 return (reg << 1) & 0x1e;
261 static inline u16 mk_high_addr(u32 reg)
263 return (reg >> 7) & 0x1ff;
266 static u32 __ar7240sw_reg_read(struct mii_bus *mii, u32 reg)
273 reg = (reg & 0xfffffffc) >> 2;
274 phy_addr = mk_phy_addr(reg);
275 phy_reg = mk_phy_reg(reg);
277 local_irq_save(flags);
278 ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg));
279 lo = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg);
280 hi = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg + 1);
281 local_irq_restore(flags);
283 return (hi << 16) | lo;
286 static void __ar7240sw_reg_write(struct mii_bus *mii, u32 reg, u32 val)
292 reg = (reg & 0xfffffffc) >> 2;
293 phy_addr = mk_phy_addr(reg);
294 phy_reg = mk_phy_reg(reg);
296 local_irq_save(flags);
297 ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg));
298 ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg + 1, (val >> 16));
299 ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg, (val & 0xffff));
300 local_irq_restore(flags);
303 static u32 ar7240sw_reg_read(struct mii_bus *mii, u32 reg_addr)
307 mutex_lock(®_mutex);
308 ret = __ar7240sw_reg_read(mii, reg_addr);
309 mutex_unlock(®_mutex);
314 static void ar7240sw_reg_write(struct mii_bus *mii, u32 reg_addr, u32 reg_val)
316 mutex_lock(®_mutex);
317 __ar7240sw_reg_write(mii, reg_addr, reg_val);
318 mutex_unlock(®_mutex);
321 static u32 ar7240sw_reg_rmw(struct mii_bus *mii, u32 reg, u32 mask, u32 val)
325 mutex_lock(®_mutex);
326 t = __ar7240sw_reg_read(mii, reg);
329 __ar7240sw_reg_write(mii, reg, t);
330 mutex_unlock(®_mutex);
335 static void ar7240sw_reg_set(struct mii_bus *mii, u32 reg, u32 val)
339 mutex_lock(®_mutex);
340 t = __ar7240sw_reg_read(mii, reg);
342 __ar7240sw_reg_write(mii, reg, t);
343 mutex_unlock(®_mutex);
346 static int __ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val,
351 for (i = 0; i < timeout; i++) {
354 t = __ar7240sw_reg_read(mii, reg);
355 if ((t & mask) == val)
364 static int ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val,
369 mutex_lock(®_mutex);
370 ret = __ar7240sw_reg_wait(mii, reg, mask, val, timeout);
371 mutex_unlock(®_mutex);
375 u16 ar7240sw_phy_read(struct mii_bus *mii, unsigned phy_addr,
381 if (phy_addr >= AR7240_NUM_PHYS)
384 mutex_lock(®_mutex);
385 t = (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) |
386 (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) |
387 AR7240_MDIO_CTRL_MASTER_EN |
388 AR7240_MDIO_CTRL_BUSY |
389 AR7240_MDIO_CTRL_CMD_READ;
391 __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t);
392 err = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL,
393 AR7240_MDIO_CTRL_BUSY, 0, 5);
395 val = __ar7240sw_reg_read(mii, AR7240_REG_MDIO_CTRL);
396 mutex_unlock(®_mutex);
398 return val & AR7240_MDIO_CTRL_DATA_M;
401 int ar7240sw_phy_write(struct mii_bus *mii, unsigned phy_addr,
402 unsigned reg_addr, u16 reg_val)
407 if (phy_addr >= AR7240_NUM_PHYS)
410 mutex_lock(®_mutex);
411 t = (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) |
412 (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) |
413 AR7240_MDIO_CTRL_MASTER_EN |
414 AR7240_MDIO_CTRL_BUSY |
415 AR7240_MDIO_CTRL_CMD_WRITE |
418 __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t);
419 ret = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL,
420 AR7240_MDIO_CTRL_BUSY, 0, 5);
421 mutex_unlock(®_mutex);
426 static void ar7240sw_disable_port(struct ar7240sw *as, unsigned port)
428 ar7240sw_reg_write(as->mii_bus, AR7240_REG_PORT_CTRL(port),
429 AR7240_PORT_CTRL_STATE_DISABLED);
432 static void ar7240sw_setup(struct ar7240sw *as)
434 struct mii_bus *mii = as->mii_bus;
436 /* Enable CPU port, and disable mirror port */
437 ar7240sw_reg_write(mii, AR7240_REG_CPU_PORT,
439 (15 << AR7240_MIRROR_PORT_S));
441 /* Setup TAG priority mapping */
442 ar7240sw_reg_write(mii, AR7240_REG_TAG_PRIORITY, 0xfa50);
444 /* Enable ARP frame acknowledge, aging, MAC replacing */
445 ar7240sw_reg_write(mii, AR7240_REG_AT_CTRL,
446 0x2b /* 5 min age time */ |
447 AR7240_AT_CTRL_AGE_EN |
448 AR7240_AT_CTRL_ARP_EN |
449 AR7240_AT_CTRL_LEARN_CHANGE);
451 /* Enable Broadcast frames transmitted to the CPU */
452 ar7240sw_reg_set(mii, AR7240_REG_FLOOD_MASK,
453 AR7240_FLOOD_MASK_BROAD_TO_CPU);
456 ar7240sw_reg_rmw(mii, AR7240_REG_GLOBAL_CTRL, AR7240_GLOBAL_CTRL_MTU_M,
459 /* setup Service TAG */
460 ar7240sw_reg_rmw(mii, AR7240_REG_SERVICE_TAG, AR7240_SERVICE_TAG_M, 0);
463 static int ar7240sw_reset(struct ar7240sw *as)
465 struct mii_bus *mii = as->mii_bus;
469 /* Set all ports to disabled state. */
470 for (i = 0; i < AR7240_NUM_PORTS; i++)
471 ar7240sw_disable_port(as, i);
473 /* Wait for transmit queues to drain. */
476 /* Reset the switch. */
477 ar7240sw_reg_write(mii, AR7240_REG_MASK_CTRL,
478 AR7240_MASK_CTRL_SOFT_RESET);
480 ret = ar7240sw_reg_wait(mii, AR7240_REG_MASK_CTRL,
481 AR7240_MASK_CTRL_SOFT_RESET, 0, 1000);
487 static void ar7240sw_setup_port(struct ar7240sw *as, unsigned port, u8 portmask)
489 struct mii_bus *mii = as->mii_bus;
493 ctrl = AR7240_PORT_CTRL_STATE_FORWARD | AR7240_PORT_CTRL_LEARN |
494 AR7240_PORT_CTRL_SINGLE_VLAN;
496 if (port == AR7240_PORT_CPU) {
497 ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port),
498 AR7240_PORT_STATUS_SPEED_1000 |
499 AR7240_PORT_STATUS_TXFLOW |
500 AR7240_PORT_STATUS_RXFLOW |
501 AR7240_PORT_STATUS_TXMAC |
502 AR7240_PORT_STATUS_RXMAC |
503 AR7240_PORT_STATUS_DUPLEX);
505 ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port),
506 AR7240_PORT_STATUS_LINK_AUTO);
509 /* Set the default VID for this port */
511 vlan = as->vlan_id[as->pvid[port]];
512 vlan |= AR7240_PORT_VLAN_MODE_SECURE <<
513 AR7240_PORT_VLAN_MODE_S;
516 vlan |= AR7240_PORT_VLAN_MODE_PORT_ONLY <<
517 AR7240_PORT_VLAN_MODE_S;
520 if (as->vlan && (as->vlan_tagged & BIT(port))) {
521 ctrl |= AR7240_PORT_CTRL_VLAN_MODE_ADD <<
522 AR7240_PORT_CTRL_VLAN_MODE_S;
524 ctrl |= AR7240_PORT_CTRL_VLAN_MODE_STRIP <<
525 AR7240_PORT_CTRL_VLAN_MODE_S;
529 if (port == AR7240_PORT_CPU)
530 portmask = ar7240sw_port_mask_but(as, AR7240_PORT_CPU);
532 portmask = ar7240sw_port_mask(as, AR7240_PORT_CPU);
535 /* allow the port to talk to all other ports, but exclude its
536 * own ID to prevent frames from being reflected back to the
537 * port that they came from */
538 portmask &= ar7240sw_port_mask_but(as, port);
540 /* set default VID and and destination ports for this VLAN */
541 vlan |= (portmask << AR7240_PORT_VLAN_DEST_PORTS_S);
543 ar7240sw_reg_write(mii, AR7240_REG_PORT_CTRL(port), ctrl);
544 ar7240sw_reg_write(mii, AR7240_REG_PORT_VLAN(port), vlan);
547 static int ar7240_set_addr(struct ar7240sw *as, u8 *addr)
549 struct mii_bus *mii = as->mii_bus;
552 t = (addr[4] << 8) | addr[5];
553 ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR0, t);
555 t = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
556 ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR1, t);
562 ar7240_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
563 struct switch_val *val)
565 struct ar7240sw *as = sw_to_ar7240(dev);
566 as->vlan_id[val->port_vlan] = val->value.i;
571 ar7240_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
572 struct switch_val *val)
574 struct ar7240sw *as = sw_to_ar7240(dev);
575 val->value.i = as->vlan_id[val->port_vlan];
580 ar7240_set_pvid(struct switch_dev *dev, int port, int vlan)
582 struct ar7240sw *as = sw_to_ar7240(dev);
584 /* make sure no invalid PVIDs get set */
586 if (vlan >= dev->vlans)
589 as->pvid[port] = vlan;
594 ar7240_get_pvid(struct switch_dev *dev, int port, int *vlan)
596 struct ar7240sw *as = sw_to_ar7240(dev);
597 *vlan = as->pvid[port];
602 ar7240_get_ports(struct switch_dev *dev, struct switch_val *val)
604 struct ar7240sw *as = sw_to_ar7240(dev);
605 u8 ports = as->vlan_table[val->port_vlan];
609 for (i = 0; i < as->swdev.ports; i++) {
610 struct switch_port *p;
612 if (!(ports & (1 << i)))
615 p = &val->value.ports[val->len++];
617 if (as->vlan_tagged & (1 << i))
618 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
626 ar7240_set_ports(struct switch_dev *dev, struct switch_val *val)
628 struct ar7240sw *as = sw_to_ar7240(dev);
629 u8 *vt = &as->vlan_table[val->port_vlan];
633 for (i = 0; i < val->len; i++) {
634 struct switch_port *p = &val->value.ports[i];
636 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED))
637 as->vlan_tagged |= (1 << p->id);
639 as->vlan_tagged &= ~(1 << p->id);
640 as->pvid[p->id] = val->port_vlan;
642 /* make sure that an untagged port does not
643 * appear in other vlans */
644 for (j = 0; j < AR7240_MAX_VLANS; j++) {
645 if (j == val->port_vlan)
647 as->vlan_table[j] &= ~(1 << p->id);
657 ar7240_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
658 struct switch_val *val)
660 struct ar7240sw *as = sw_to_ar7240(dev);
661 as->vlan = !!val->value.i;
666 ar7240_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
667 struct switch_val *val)
669 struct ar7240sw *as = sw_to_ar7240(dev);
670 val->value.i = as->vlan;
675 ar7240_speed_str(u32 status)
679 speed = (status >> AR7240_PORT_STATUS_SPEED_S) &
680 AR7240_PORT_STATUS_SPEED_M;
682 case AR7240_PORT_STATUS_SPEED_10:
684 case AR7240_PORT_STATUS_SPEED_100:
686 case AR7240_PORT_STATUS_SPEED_1000:
694 ar7240_port_get_link(struct switch_dev *dev, const struct switch_attr *attr,
695 struct switch_val *val)
697 struct ar7240sw *as = sw_to_ar7240(dev);
698 struct mii_bus *mii = as->mii_bus;
703 port = val->port_vlan;
705 memset(as->buf, '\0', sizeof(as->buf));
706 status = ar7240sw_reg_read(mii, AR7240_REG_PORT_STATUS(port));
708 if (status & AR7240_PORT_STATUS_LINK_UP) {
709 len = snprintf(as->buf, sizeof(as->buf),
710 "port:%d link:up speed:%s %s-duplex %s%s%s",
712 ar7240_speed_str(status),
713 (status & AR7240_PORT_STATUS_DUPLEX) ?
715 (status & AR7240_PORT_STATUS_TXFLOW) ?
717 (status & AR7240_PORT_STATUS_RXFLOW) ?
719 (status & AR7240_PORT_STATUS_LINK_AUTO) ?
722 len = snprintf(as->buf, sizeof(as->buf),
723 "port:%d link:down", port);
726 val->value.s = as->buf;
733 ar7240_vtu_op(struct ar7240sw *as, u32 op, u32 val)
735 struct mii_bus *mii = as->mii_bus;
737 if (ar7240sw_reg_wait(mii, AR7240_REG_VTU, AR7240_VTU_ACTIVE, 0, 5))
740 if ((op & AR7240_VTU_OP) == AR7240_VTU_OP_LOAD) {
741 val &= AR7240_VTUDATA_MEMBER;
742 val |= AR7240_VTUDATA_VALID;
743 ar7240sw_reg_write(mii, AR7240_REG_VTU_DATA, val);
745 op |= AR7240_VTU_ACTIVE;
746 ar7240sw_reg_write(mii, AR7240_REG_VTU, op);
750 ar7240_hw_apply(struct switch_dev *dev)
752 struct ar7240sw *as = sw_to_ar7240(dev);
753 u8 portmask[AR7240_NUM_PORTS];
756 /* flush all vlan translation unit entries */
757 ar7240_vtu_op(as, AR7240_VTU_OP_FLUSH, 0);
759 memset(portmask, 0, sizeof(portmask));
761 /* calculate the port destination masks and load vlans
762 * into the vlan translation unit */
763 for (j = 0; j < AR7240_MAX_VLANS; j++) {
764 u8 vp = as->vlan_table[j];
769 for (i = 0; i < as->swdev.ports; i++) {
772 portmask[i] |= vp & ~mask;
777 (as->vlan_id[j] << AR7240_VTU_VID_S),
782 * isolate all ports, but connect them to the cpu port */
783 for (i = 0; i < as->swdev.ports; i++) {
784 if (i == AR7240_PORT_CPU)
787 portmask[i] = 1 << AR7240_PORT_CPU;
788 portmask[AR7240_PORT_CPU] |= (1 << i);
792 /* update the port destination mask registers and tag settings */
793 for (i = 0; i < as->swdev.ports; i++)
794 ar7240sw_setup_port(as, i, portmask[i]);
800 ar7240_reset_switch(struct switch_dev *dev)
802 struct ar7240sw *as = sw_to_ar7240(dev);
807 static struct switch_attr ar7240_globals[] = {
809 .type = SWITCH_TYPE_INT,
810 .name = "enable_vlan",
811 .description = "Enable VLAN mode",
812 .set = ar7240_set_vlan,
813 .get = ar7240_get_vlan,
818 static struct switch_attr ar7240_port[] = {
820 .type = SWITCH_TYPE_STRING,
822 .description = "Get port link information",
825 .get = ar7240_port_get_link,
829 static struct switch_attr ar7240_vlan[] = {
831 .type = SWITCH_TYPE_INT,
833 .description = "VLAN ID",
834 .set = ar7240_set_vid,
835 .get = ar7240_get_vid,
840 static const struct switch_dev_ops ar7240_ops = {
842 .attr = ar7240_globals,
843 .n_attr = ARRAY_SIZE(ar7240_globals),
847 .n_attr = ARRAY_SIZE(ar7240_port),
851 .n_attr = ARRAY_SIZE(ar7240_vlan),
853 .get_port_pvid = ar7240_get_pvid,
854 .set_port_pvid = ar7240_set_pvid,
855 .get_vlan_ports = ar7240_get_ports,
856 .set_vlan_ports = ar7240_set_ports,
857 .apply_config = ar7240_hw_apply,
858 .reset_switch = ar7240_reset_switch,
861 static struct ar7240sw *ar7240_probe(struct ag71xx *ag)
863 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
864 struct mii_bus *mii = ag->mii_bus;
866 struct switch_dev *swdev;
872 phy_id1 = ar7240sw_phy_read(mii, 0, MII_PHYSID1);
873 phy_id2 = ar7240sw_phy_read(mii, 0, MII_PHYSID2);
874 if ((phy_id1 != AR7240_PHY_ID1 || phy_id2 != AR7240_PHY_ID2) &&
875 (phy_id1 != AR934X_PHY_ID1 || phy_id2 != AR934X_PHY_ID2)) {
876 pr_err("%s: unknown phy id '%04x:%04x'\n",
877 ag->dev->name, phy_id1, phy_id2);
881 as = kzalloc(sizeof(*as), GFP_KERNEL);
886 as->swdata = pdata->switch_data;
890 ctrl = ar7240sw_reg_read(mii, AR7240_REG_MASK_CTRL);
891 as->ver = (ctrl >> AR7240_MASK_CTRL_VERSION_S) &
892 AR7240_MASK_CTRL_VERSION_M;
894 if (sw_is_ar7240(as)) {
895 swdev->name = "AR7240/AR9330 built-in switch";
896 } else if (sw_is_ar934x(as)) {
897 swdev->name = "AR934X built-in switch";
899 pr_err("%s: unsupported chip, ctrl=%08x\n",
900 ag->dev->name, ctrl);
904 swdev->ports = AR7240_NUM_PORTS - 1;
905 swdev->cpu_port = AR7240_PORT_CPU;
906 swdev->vlans = AR7240_MAX_VLANS;
907 swdev->ops = &ar7240_ops;
909 if (register_switch(&as->swdev, ag->dev) < 0)
912 pr_info("%s: Found an %s\n", ag->dev->name, swdev->name);
914 /* initialize defaults */
915 for (i = 0; i < AR7240_MAX_VLANS; i++)
918 as->vlan_table[0] = ar7240sw_port_mask_all(as);
927 static void link_function(struct work_struct *work) {
928 struct ag71xx *ag = container_of(work, struct ag71xx, link_work.work);
933 for (i = 0; i < 4; i++) {
934 int link = ar7240sw_phy_read(ag->mii_bus, i, MII_BMSR);
935 if(link & BMSR_LSTATUS) {
941 spin_lock_irqsave(&ag->lock, flags);
942 if(status != ag->link) {
944 ag71xx_link_adjust(ag);
946 spin_unlock_irqrestore(&ag->lock, flags);
948 schedule_delayed_work(&ag->link_work, HZ / 2);
951 void ag71xx_ar7240_start(struct ag71xx *ag)
953 struct ar7240sw *as = ag->phy_priv;
957 ag->speed = SPEED_1000;
960 ar7240_set_addr(as, ag->dev->dev_addr);
961 ar7240_hw_apply(&as->swdev);
963 schedule_delayed_work(&ag->link_work, HZ / 10);
966 void ag71xx_ar7240_stop(struct ag71xx *ag)
968 cancel_delayed_work_sync(&ag->link_work);
971 int __devinit ag71xx_ar7240_init(struct ag71xx *ag)
975 as = ar7240_probe(ag);
982 INIT_DELAYED_WORK(&ag->link_work, link_function);
987 void ag71xx_ar7240_cleanup(struct ag71xx *ag)
989 struct ar7240sw *as = ag->phy_priv;
994 unregister_switch(&as->swdev);