2 * Driver for the built-in ethernet switch of the Atheros AR7240 SoC
3 * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
4 * Copyright (c) 2010 Felix Fietkau <nbd@openwrt.org>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
12 #include <linux/etherdevice.h>
13 #include <linux/list.h>
14 #include <linux/netdevice.h>
15 #include <linux/phy.h>
16 #include <linux/mii.h>
17 #include <linux/bitops.h>
18 #include <linux/switch.h>
21 #define BITM(_count) (BIT(_count) - 1)
22 #define BITS(_shift, _count) (BITM(_count) << _shift)
24 #define AR7240_REG_MASK_CTRL 0x00
25 #define AR7240_MASK_CTRL_REVISION_M BITM(8)
26 #define AR7240_MASK_CTRL_VERSION_M BITM(8)
27 #define AR7240_MASK_CTRL_VERSION_S 8
28 #define AR7240_MASK_CTRL_VERSION_AR7240 0x01
29 #define AR7240_MASK_CTRL_VERSION_AR934X 0x02
30 #define AR7240_MASK_CTRL_SOFT_RESET BIT(31)
32 #define AR7240_REG_MAC_ADDR0 0x20
33 #define AR7240_REG_MAC_ADDR1 0x24
35 #define AR7240_REG_FLOOD_MASK 0x2c
36 #define AR7240_FLOOD_MASK_BROAD_TO_CPU BIT(26)
38 #define AR7240_REG_GLOBAL_CTRL 0x30
39 #define AR7240_GLOBAL_CTRL_MTU_M BITM(12)
41 #define AR7240_REG_VTU 0x0040
42 #define AR7240_VTU_OP BITM(3)
43 #define AR7240_VTU_OP_NOOP 0x0
44 #define AR7240_VTU_OP_FLUSH 0x1
45 #define AR7240_VTU_OP_LOAD 0x2
46 #define AR7240_VTU_OP_PURGE 0x3
47 #define AR7240_VTU_OP_REMOVE_PORT 0x4
48 #define AR7240_VTU_ACTIVE BIT(3)
49 #define AR7240_VTU_FULL BIT(4)
50 #define AR7240_VTU_PORT BITS(8, 4)
51 #define AR7240_VTU_PORT_S 8
52 #define AR7240_VTU_VID BITS(16, 12)
53 #define AR7240_VTU_VID_S 16
54 #define AR7240_VTU_PRIO BITS(28, 3)
55 #define AR7240_VTU_PRIO_S 28
56 #define AR7240_VTU_PRIO_EN BIT(31)
58 #define AR7240_REG_VTU_DATA 0x0044
59 #define AR7240_VTUDATA_MEMBER BITS(0, 10)
60 #define AR7240_VTUDATA_VALID BIT(11)
62 #define AR7240_REG_ATU 0x50
63 #define AR7240_ATU_FLUSH_ALL 0x1
65 #define AR7240_REG_AT_CTRL 0x5c
66 #define AR7240_AT_CTRL_AGE_TIME BITS(0, 15)
67 #define AR7240_AT_CTRL_AGE_EN BIT(17)
68 #define AR7240_AT_CTRL_LEARN_CHANGE BIT(18)
69 #define AR7240_AT_CTRL_ARP_EN BIT(20)
71 #define AR7240_REG_TAG_PRIORITY 0x70
73 #define AR7240_REG_SERVICE_TAG 0x74
74 #define AR7240_SERVICE_TAG_M BITM(16)
76 #define AR7240_REG_CPU_PORT 0x78
77 #define AR7240_MIRROR_PORT_S 4
78 #define AR7240_CPU_PORT_EN BIT(8)
80 #define AR7240_REG_MIB_FUNCTION0 0x80
81 #define AR7240_MIB_TIMER_M BITM(16)
82 #define AR7240_MIB_AT_HALF_EN BIT(16)
83 #define AR7240_MIB_BUSY BIT(17)
84 #define AR7240_MIB_FUNC_S 24
85 #define AR7240_MIB_FUNC_NO_OP 0x0
86 #define AR7240_MIB_FUNC_FLUSH 0x1
87 #define AR7240_MIB_FUNC_CAPTURE 0x3
89 #define AR7240_REG_MDIO_CTRL 0x98
90 #define AR7240_MDIO_CTRL_DATA_M BITM(16)
91 #define AR7240_MDIO_CTRL_REG_ADDR_S 16
92 #define AR7240_MDIO_CTRL_PHY_ADDR_S 21
93 #define AR7240_MDIO_CTRL_CMD_WRITE 0
94 #define AR7240_MDIO_CTRL_CMD_READ BIT(27)
95 #define AR7240_MDIO_CTRL_MASTER_EN BIT(30)
96 #define AR7240_MDIO_CTRL_BUSY BIT(31)
98 #define AR7240_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
100 #define AR7240_REG_PORT_STATUS(_port) (AR7240_REG_PORT_BASE((_port)) + 0x00)
101 #define AR7240_PORT_STATUS_SPEED_S 0
102 #define AR7240_PORT_STATUS_SPEED_M BITM(2)
103 #define AR7240_PORT_STATUS_SPEED_10 0
104 #define AR7240_PORT_STATUS_SPEED_100 1
105 #define AR7240_PORT_STATUS_SPEED_1000 2
106 #define AR7240_PORT_STATUS_TXMAC BIT(2)
107 #define AR7240_PORT_STATUS_RXMAC BIT(3)
108 #define AR7240_PORT_STATUS_TXFLOW BIT(4)
109 #define AR7240_PORT_STATUS_RXFLOW BIT(5)
110 #define AR7240_PORT_STATUS_DUPLEX BIT(6)
111 #define AR7240_PORT_STATUS_LINK_UP BIT(8)
112 #define AR7240_PORT_STATUS_LINK_AUTO BIT(9)
113 #define AR7240_PORT_STATUS_LINK_PAUSE BIT(10)
115 #define AR7240_REG_PORT_CTRL(_port) (AR7240_REG_PORT_BASE((_port)) + 0x04)
116 #define AR7240_PORT_CTRL_STATE_M BITM(3)
117 #define AR7240_PORT_CTRL_STATE_DISABLED 0
118 #define AR7240_PORT_CTRL_STATE_BLOCK 1
119 #define AR7240_PORT_CTRL_STATE_LISTEN 2
120 #define AR7240_PORT_CTRL_STATE_LEARN 3
121 #define AR7240_PORT_CTRL_STATE_FORWARD 4
122 #define AR7240_PORT_CTRL_LEARN_LOCK BIT(7)
123 #define AR7240_PORT_CTRL_VLAN_MODE_S 8
124 #define AR7240_PORT_CTRL_VLAN_MODE_KEEP 0
125 #define AR7240_PORT_CTRL_VLAN_MODE_STRIP 1
126 #define AR7240_PORT_CTRL_VLAN_MODE_ADD 2
127 #define AR7240_PORT_CTRL_VLAN_MODE_DOUBLE_TAG 3
128 #define AR7240_PORT_CTRL_IGMP_SNOOP BIT(10)
129 #define AR7240_PORT_CTRL_HEADER BIT(11)
130 #define AR7240_PORT_CTRL_MAC_LOOP BIT(12)
131 #define AR7240_PORT_CTRL_SINGLE_VLAN BIT(13)
132 #define AR7240_PORT_CTRL_LEARN BIT(14)
133 #define AR7240_PORT_CTRL_DOUBLE_TAG BIT(15)
134 #define AR7240_PORT_CTRL_MIRROR_TX BIT(16)
135 #define AR7240_PORT_CTRL_MIRROR_RX BIT(17)
137 #define AR7240_REG_PORT_VLAN(_port) (AR7240_REG_PORT_BASE((_port)) + 0x08)
139 #define AR7240_PORT_VLAN_DEFAULT_ID_S 0
140 #define AR7240_PORT_VLAN_DEST_PORTS_S 16
141 #define AR7240_PORT_VLAN_MODE_S 30
142 #define AR7240_PORT_VLAN_MODE_PORT_ONLY 0
143 #define AR7240_PORT_VLAN_MODE_PORT_FALLBACK 1
144 #define AR7240_PORT_VLAN_MODE_VLAN_ONLY 2
145 #define AR7240_PORT_VLAN_MODE_SECURE 3
148 #define AR7240_REG_STATS_BASE(_port) (0x20000 + (_port) * 0x100)
150 #define AR7240_STATS_RXBROAD 0x00
151 #define AR7240_STATS_RXPAUSE 0x04
152 #define AR7240_STATS_RXMULTI 0x08
153 #define AR7240_STATS_RXFCSERR 0x0c
154 #define AR7240_STATS_RXALIGNERR 0x10
155 #define AR7240_STATS_RXRUNT 0x14
156 #define AR7240_STATS_RXFRAGMENT 0x18
157 #define AR7240_STATS_RX64BYTE 0x1c
158 #define AR7240_STATS_RX128BYTE 0x20
159 #define AR7240_STATS_RX256BYTE 0x24
160 #define AR7240_STATS_RX512BYTE 0x28
161 #define AR7240_STATS_RX1024BYTE 0x2c
162 #define AR7240_STATS_RX1518BYTE 0x30
163 #define AR7240_STATS_RXMAXBYTE 0x34
164 #define AR7240_STATS_RXTOOLONG 0x38
165 #define AR7240_STATS_RXGOODBYTE 0x3c
166 #define AR7240_STATS_RXBADBYTE 0x44
167 #define AR7240_STATS_RXOVERFLOW 0x4c
168 #define AR7240_STATS_FILTERED 0x50
169 #define AR7240_STATS_TXBROAD 0x54
170 #define AR7240_STATS_TXPAUSE 0x58
171 #define AR7240_STATS_TXMULTI 0x5c
172 #define AR7240_STATS_TXUNDERRUN 0x60
173 #define AR7240_STATS_TX64BYTE 0x64
174 #define AR7240_STATS_TX128BYTE 0x68
175 #define AR7240_STATS_TX256BYTE 0x6c
176 #define AR7240_STATS_TX512BYTE 0x70
177 #define AR7240_STATS_TX1024BYTE 0x74
178 #define AR7240_STATS_TX1518BYTE 0x78
179 #define AR7240_STATS_TXMAXBYTE 0x7c
180 #define AR7240_STATS_TXOVERSIZE 0x80
181 #define AR7240_STATS_TXBYTE 0x84
182 #define AR7240_STATS_TXCOLLISION 0x8c
183 #define AR7240_STATS_TXABORTCOL 0x90
184 #define AR7240_STATS_TXMULTICOL 0x94
185 #define AR7240_STATS_TXSINGLECOL 0x98
186 #define AR7240_STATS_TXEXCDEFER 0x9c
187 #define AR7240_STATS_TXDEFER 0xa0
188 #define AR7240_STATS_TXLATECOL 0xa4
190 #define AR7240_PORT_CPU 0
191 #define AR7240_NUM_PORTS 6
192 #define AR7240_NUM_PHYS 5
194 #define AR7240_PHY_ID1 0x004d
195 #define AR7240_PHY_ID2 0xd041
197 #define AR934X_PHY_ID1 0x004d
198 #define AR934X_PHY_ID2 0xd042
200 #define AR7240_MAX_VLANS 16
202 #define AR934X_REG_OPER_MODE0 0x04
203 #define AR934X_OPER_MODE0_MAC_GMII_EN BIT(6)
204 #define AR934X_OPER_MODE0_PHY_MII_EN BIT(10)
206 #define sw_to_ar7240(_dev) container_of(_dev, struct ar7240sw, swdev)
209 struct mii_bus *mii_bus;
210 struct ag71xx_switch_platform_data *swdata;
211 struct switch_dev swdev;
215 u16 vlan_id[AR7240_MAX_VLANS];
216 u8 vlan_table[AR7240_MAX_VLANS];
218 u16 pvid[AR7240_NUM_PORTS];
222 struct ar7240sw_hw_stat {
223 char string[ETH_GSTRING_LEN];
228 static DEFINE_MUTEX(reg_mutex);
230 static inline int sw_is_ar7240(struct ar7240sw *as)
232 return as->ver == AR7240_MASK_CTRL_VERSION_AR7240;
235 static inline int sw_is_ar934x(struct ar7240sw *as)
237 return as->ver == AR7240_MASK_CTRL_VERSION_AR934X;
240 static inline u32 ar7240sw_port_mask(struct ar7240sw *as, int port)
245 static inline u32 ar7240sw_port_mask_all(struct ar7240sw *as)
247 return BIT(as->swdev.ports) - 1;
250 static inline u32 ar7240sw_port_mask_but(struct ar7240sw *as, int port)
252 return ar7240sw_port_mask_all(as) & ~BIT(port);
255 static inline u16 mk_phy_addr(u32 reg)
257 return 0x17 & ((reg >> 4) | 0x10);
260 static inline u16 mk_phy_reg(u32 reg)
262 return (reg << 1) & 0x1e;
265 static inline u16 mk_high_addr(u32 reg)
267 return (reg >> 7) & 0x1ff;
270 static u32 __ar7240sw_reg_read(struct mii_bus *mii, u32 reg)
277 reg = (reg & 0xfffffffc) >> 2;
278 phy_addr = mk_phy_addr(reg);
279 phy_reg = mk_phy_reg(reg);
281 local_irq_save(flags);
282 ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg));
283 lo = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg);
284 hi = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg + 1);
285 local_irq_restore(flags);
287 return (hi << 16) | lo;
290 static void __ar7240sw_reg_write(struct mii_bus *mii, u32 reg, u32 val)
296 reg = (reg & 0xfffffffc) >> 2;
297 phy_addr = mk_phy_addr(reg);
298 phy_reg = mk_phy_reg(reg);
300 local_irq_save(flags);
301 ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg));
302 ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg + 1, (val >> 16));
303 ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg, (val & 0xffff));
304 local_irq_restore(flags);
307 static u32 ar7240sw_reg_read(struct mii_bus *mii, u32 reg_addr)
311 mutex_lock(®_mutex);
312 ret = __ar7240sw_reg_read(mii, reg_addr);
313 mutex_unlock(®_mutex);
318 static void ar7240sw_reg_write(struct mii_bus *mii, u32 reg_addr, u32 reg_val)
320 mutex_lock(®_mutex);
321 __ar7240sw_reg_write(mii, reg_addr, reg_val);
322 mutex_unlock(®_mutex);
325 static u32 ar7240sw_reg_rmw(struct mii_bus *mii, u32 reg, u32 mask, u32 val)
329 mutex_lock(®_mutex);
330 t = __ar7240sw_reg_read(mii, reg);
333 __ar7240sw_reg_write(mii, reg, t);
334 mutex_unlock(®_mutex);
339 static void ar7240sw_reg_set(struct mii_bus *mii, u32 reg, u32 val)
343 mutex_lock(®_mutex);
344 t = __ar7240sw_reg_read(mii, reg);
346 __ar7240sw_reg_write(mii, reg, t);
347 mutex_unlock(®_mutex);
350 static int __ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val,
355 for (i = 0; i < timeout; i++) {
358 t = __ar7240sw_reg_read(mii, reg);
359 if ((t & mask) == val)
368 static int ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val,
373 mutex_lock(®_mutex);
374 ret = __ar7240sw_reg_wait(mii, reg, mask, val, timeout);
375 mutex_unlock(®_mutex);
379 u16 ar7240sw_phy_read(struct mii_bus *mii, unsigned phy_addr,
385 if (phy_addr >= AR7240_NUM_PHYS)
388 mutex_lock(®_mutex);
389 t = (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) |
390 (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) |
391 AR7240_MDIO_CTRL_MASTER_EN |
392 AR7240_MDIO_CTRL_BUSY |
393 AR7240_MDIO_CTRL_CMD_READ;
395 __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t);
396 err = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL,
397 AR7240_MDIO_CTRL_BUSY, 0, 5);
399 val = __ar7240sw_reg_read(mii, AR7240_REG_MDIO_CTRL);
400 mutex_unlock(®_mutex);
402 return val & AR7240_MDIO_CTRL_DATA_M;
405 int ar7240sw_phy_write(struct mii_bus *mii, unsigned phy_addr,
406 unsigned reg_addr, u16 reg_val)
411 if (phy_addr >= AR7240_NUM_PHYS)
414 mutex_lock(®_mutex);
415 t = (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) |
416 (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) |
417 AR7240_MDIO_CTRL_MASTER_EN |
418 AR7240_MDIO_CTRL_BUSY |
419 AR7240_MDIO_CTRL_CMD_WRITE |
422 __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t);
423 ret = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL,
424 AR7240_MDIO_CTRL_BUSY, 0, 5);
425 mutex_unlock(®_mutex);
430 static void ar7240sw_disable_port(struct ar7240sw *as, unsigned port)
432 ar7240sw_reg_write(as->mii_bus, AR7240_REG_PORT_CTRL(port),
433 AR7240_PORT_CTRL_STATE_DISABLED);
436 static void ar7240sw_setup(struct ar7240sw *as)
438 struct mii_bus *mii = as->mii_bus;
440 /* Enable CPU port, and disable mirror port */
441 ar7240sw_reg_write(mii, AR7240_REG_CPU_PORT,
443 (15 << AR7240_MIRROR_PORT_S));
445 /* Setup TAG priority mapping */
446 ar7240sw_reg_write(mii, AR7240_REG_TAG_PRIORITY, 0xfa50);
448 /* Enable ARP frame acknowledge, aging, MAC replacing */
449 ar7240sw_reg_write(mii, AR7240_REG_AT_CTRL,
450 0x2b /* 5 min age time */ |
451 AR7240_AT_CTRL_AGE_EN |
452 AR7240_AT_CTRL_ARP_EN |
453 AR7240_AT_CTRL_LEARN_CHANGE);
455 /* Enable Broadcast frames transmitted to the CPU */
456 ar7240sw_reg_set(mii, AR7240_REG_FLOOD_MASK,
457 AR7240_FLOOD_MASK_BROAD_TO_CPU);
460 ar7240sw_reg_rmw(mii, AR7240_REG_GLOBAL_CTRL, AR7240_GLOBAL_CTRL_MTU_M,
463 /* setup Service TAG */
464 ar7240sw_reg_rmw(mii, AR7240_REG_SERVICE_TAG, AR7240_SERVICE_TAG_M, 0);
467 static int ar7240sw_reset(struct ar7240sw *as)
469 struct mii_bus *mii = as->mii_bus;
473 /* Set all ports to disabled state. */
474 for (i = 0; i < AR7240_NUM_PORTS; i++)
475 ar7240sw_disable_port(as, i);
477 /* Wait for transmit queues to drain. */
480 /* Reset the switch. */
481 ar7240sw_reg_write(mii, AR7240_REG_MASK_CTRL,
482 AR7240_MASK_CTRL_SOFT_RESET);
484 ret = ar7240sw_reg_wait(mii, AR7240_REG_MASK_CTRL,
485 AR7240_MASK_CTRL_SOFT_RESET, 0, 1000);
491 static void ar7240sw_setup_port(struct ar7240sw *as, unsigned port, u8 portmask)
493 struct mii_bus *mii = as->mii_bus;
497 ctrl = AR7240_PORT_CTRL_STATE_FORWARD | AR7240_PORT_CTRL_LEARN |
498 AR7240_PORT_CTRL_SINGLE_VLAN;
500 if (port == AR7240_PORT_CPU) {
501 ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port),
502 AR7240_PORT_STATUS_SPEED_1000 |
503 AR7240_PORT_STATUS_TXFLOW |
504 AR7240_PORT_STATUS_RXFLOW |
505 AR7240_PORT_STATUS_TXMAC |
506 AR7240_PORT_STATUS_RXMAC |
507 AR7240_PORT_STATUS_DUPLEX);
509 ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port),
510 AR7240_PORT_STATUS_LINK_AUTO);
513 /* Set the default VID for this port */
515 vlan = as->vlan_id[as->pvid[port]];
516 vlan |= AR7240_PORT_VLAN_MODE_SECURE <<
517 AR7240_PORT_VLAN_MODE_S;
520 vlan |= AR7240_PORT_VLAN_MODE_PORT_ONLY <<
521 AR7240_PORT_VLAN_MODE_S;
524 if (as->vlan && (as->vlan_tagged & BIT(port))) {
525 ctrl |= AR7240_PORT_CTRL_VLAN_MODE_ADD <<
526 AR7240_PORT_CTRL_VLAN_MODE_S;
528 ctrl |= AR7240_PORT_CTRL_VLAN_MODE_STRIP <<
529 AR7240_PORT_CTRL_VLAN_MODE_S;
533 if (port == AR7240_PORT_CPU)
534 portmask = ar7240sw_port_mask_but(as, AR7240_PORT_CPU);
536 portmask = ar7240sw_port_mask(as, AR7240_PORT_CPU);
539 /* allow the port to talk to all other ports, but exclude its
540 * own ID to prevent frames from being reflected back to the
541 * port that they came from */
542 portmask &= ar7240sw_port_mask_but(as, port);
544 /* set default VID and and destination ports for this VLAN */
545 vlan |= (portmask << AR7240_PORT_VLAN_DEST_PORTS_S);
547 ar7240sw_reg_write(mii, AR7240_REG_PORT_CTRL(port), ctrl);
548 ar7240sw_reg_write(mii, AR7240_REG_PORT_VLAN(port), vlan);
551 static int ar7240_set_addr(struct ar7240sw *as, u8 *addr)
553 struct mii_bus *mii = as->mii_bus;
556 t = (addr[4] << 8) | addr[5];
557 ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR0, t);
559 t = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
560 ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR1, t);
566 ar7240_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
567 struct switch_val *val)
569 struct ar7240sw *as = sw_to_ar7240(dev);
570 as->vlan_id[val->port_vlan] = val->value.i;
575 ar7240_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
576 struct switch_val *val)
578 struct ar7240sw *as = sw_to_ar7240(dev);
579 val->value.i = as->vlan_id[val->port_vlan];
584 ar7240_set_pvid(struct switch_dev *dev, int port, int vlan)
586 struct ar7240sw *as = sw_to_ar7240(dev);
588 /* make sure no invalid PVIDs get set */
590 if (vlan >= dev->vlans)
593 as->pvid[port] = vlan;
598 ar7240_get_pvid(struct switch_dev *dev, int port, int *vlan)
600 struct ar7240sw *as = sw_to_ar7240(dev);
601 *vlan = as->pvid[port];
606 ar7240_get_ports(struct switch_dev *dev, struct switch_val *val)
608 struct ar7240sw *as = sw_to_ar7240(dev);
609 u8 ports = as->vlan_table[val->port_vlan];
613 for (i = 0; i < as->swdev.ports; i++) {
614 struct switch_port *p;
616 if (!(ports & (1 << i)))
619 p = &val->value.ports[val->len++];
621 if (as->vlan_tagged & (1 << i))
622 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
630 ar7240_set_ports(struct switch_dev *dev, struct switch_val *val)
632 struct ar7240sw *as = sw_to_ar7240(dev);
633 u8 *vt = &as->vlan_table[val->port_vlan];
637 for (i = 0; i < val->len; i++) {
638 struct switch_port *p = &val->value.ports[i];
640 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED))
641 as->vlan_tagged |= (1 << p->id);
643 as->vlan_tagged &= ~(1 << p->id);
644 as->pvid[p->id] = val->port_vlan;
646 /* make sure that an untagged port does not
647 * appear in other vlans */
648 for (j = 0; j < AR7240_MAX_VLANS; j++) {
649 if (j == val->port_vlan)
651 as->vlan_table[j] &= ~(1 << p->id);
661 ar7240_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
662 struct switch_val *val)
664 struct ar7240sw *as = sw_to_ar7240(dev);
665 as->vlan = !!val->value.i;
670 ar7240_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
671 struct switch_val *val)
673 struct ar7240sw *as = sw_to_ar7240(dev);
674 val->value.i = as->vlan;
679 ar7240_speed_str(u32 status)
683 speed = (status >> AR7240_PORT_STATUS_SPEED_S) &
684 AR7240_PORT_STATUS_SPEED_M;
686 case AR7240_PORT_STATUS_SPEED_10:
688 case AR7240_PORT_STATUS_SPEED_100:
690 case AR7240_PORT_STATUS_SPEED_1000:
698 ar7240_port_get_link(struct switch_dev *dev, const struct switch_attr *attr,
699 struct switch_val *val)
701 struct ar7240sw *as = sw_to_ar7240(dev);
702 struct mii_bus *mii = as->mii_bus;
707 port = val->port_vlan;
709 memset(as->buf, '\0', sizeof(as->buf));
710 status = ar7240sw_reg_read(mii, AR7240_REG_PORT_STATUS(port));
712 if (status & AR7240_PORT_STATUS_LINK_UP) {
713 len = snprintf(as->buf, sizeof(as->buf),
714 "port:%d link:up speed:%s %s-duplex %s%s%s",
716 ar7240_speed_str(status),
717 (status & AR7240_PORT_STATUS_DUPLEX) ?
719 (status & AR7240_PORT_STATUS_TXFLOW) ?
721 (status & AR7240_PORT_STATUS_RXFLOW) ?
723 (status & AR7240_PORT_STATUS_LINK_AUTO) ?
726 len = snprintf(as->buf, sizeof(as->buf),
727 "port:%d link:down", port);
730 val->value.s = as->buf;
737 ar7240_vtu_op(struct ar7240sw *as, u32 op, u32 val)
739 struct mii_bus *mii = as->mii_bus;
741 if (ar7240sw_reg_wait(mii, AR7240_REG_VTU, AR7240_VTU_ACTIVE, 0, 5))
744 if ((op & AR7240_VTU_OP) == AR7240_VTU_OP_LOAD) {
745 val &= AR7240_VTUDATA_MEMBER;
746 val |= AR7240_VTUDATA_VALID;
747 ar7240sw_reg_write(mii, AR7240_REG_VTU_DATA, val);
749 op |= AR7240_VTU_ACTIVE;
750 ar7240sw_reg_write(mii, AR7240_REG_VTU, op);
754 ar7240_hw_apply(struct switch_dev *dev)
756 struct ar7240sw *as = sw_to_ar7240(dev);
757 u8 portmask[AR7240_NUM_PORTS];
760 /* flush all vlan translation unit entries */
761 ar7240_vtu_op(as, AR7240_VTU_OP_FLUSH, 0);
763 memset(portmask, 0, sizeof(portmask));
765 /* calculate the port destination masks and load vlans
766 * into the vlan translation unit */
767 for (j = 0; j < AR7240_MAX_VLANS; j++) {
768 u8 vp = as->vlan_table[j];
773 for (i = 0; i < as->swdev.ports; i++) {
776 portmask[i] |= vp & ~mask;
781 (as->vlan_id[j] << AR7240_VTU_VID_S),
786 * isolate all ports, but connect them to the cpu port */
787 for (i = 0; i < as->swdev.ports; i++) {
788 if (i == AR7240_PORT_CPU)
791 portmask[i] = 1 << AR7240_PORT_CPU;
792 portmask[AR7240_PORT_CPU] |= (1 << i);
796 /* update the port destination mask registers and tag settings */
797 for (i = 0; i < as->swdev.ports; i++)
798 ar7240sw_setup_port(as, i, portmask[i]);
804 ar7240_reset_switch(struct switch_dev *dev)
806 struct ar7240sw *as = sw_to_ar7240(dev);
811 static struct switch_attr ar7240_globals[] = {
813 .type = SWITCH_TYPE_INT,
814 .name = "enable_vlan",
815 .description = "Enable VLAN mode",
816 .set = ar7240_set_vlan,
817 .get = ar7240_get_vlan,
822 static struct switch_attr ar7240_port[] = {
824 .type = SWITCH_TYPE_STRING,
826 .description = "Get port link information",
829 .get = ar7240_port_get_link,
833 static struct switch_attr ar7240_vlan[] = {
835 .type = SWITCH_TYPE_INT,
837 .description = "VLAN ID",
838 .set = ar7240_set_vid,
839 .get = ar7240_get_vid,
844 static const struct switch_dev_ops ar7240_ops = {
846 .attr = ar7240_globals,
847 .n_attr = ARRAY_SIZE(ar7240_globals),
851 .n_attr = ARRAY_SIZE(ar7240_port),
855 .n_attr = ARRAY_SIZE(ar7240_vlan),
857 .get_port_pvid = ar7240_get_pvid,
858 .set_port_pvid = ar7240_set_pvid,
859 .get_vlan_ports = ar7240_get_ports,
860 .set_vlan_ports = ar7240_set_ports,
861 .apply_config = ar7240_hw_apply,
862 .reset_switch = ar7240_reset_switch,
865 static struct ar7240sw *ar7240_probe(struct ag71xx *ag)
867 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
868 struct mii_bus *mii = ag->mii_bus;
870 struct switch_dev *swdev;
876 phy_id1 = ar7240sw_phy_read(mii, 0, MII_PHYSID1);
877 phy_id2 = ar7240sw_phy_read(mii, 0, MII_PHYSID2);
878 if ((phy_id1 != AR7240_PHY_ID1 || phy_id2 != AR7240_PHY_ID2) &&
879 (phy_id1 != AR934X_PHY_ID1 || phy_id2 != AR934X_PHY_ID2)) {
880 pr_err("%s: unknown phy id '%04x:%04x'\n",
881 ag->dev->name, phy_id1, phy_id2);
885 as = kzalloc(sizeof(*as), GFP_KERNEL);
890 as->swdata = pdata->switch_data;
894 ctrl = ar7240sw_reg_read(mii, AR7240_REG_MASK_CTRL);
895 as->ver = (ctrl >> AR7240_MASK_CTRL_VERSION_S) &
896 AR7240_MASK_CTRL_VERSION_M;
898 if (sw_is_ar7240(as)) {
899 swdev->name = "AR7240/AR9330 built-in switch";
900 } else if (sw_is_ar934x(as)) {
901 struct ag71xx_platform_data *pdata;
903 swdev->name = "AR934X built-in switch";
905 pdata = ag71xx_get_pdata(ag);
906 if (pdata->phy_if_mode == PHY_INTERFACE_MODE_GMII) {
907 ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE0,
908 AR934X_OPER_MODE0_MAC_GMII_EN);
909 } else if (pdata->phy_if_mode == PHY_INTERFACE_MODE_MII) {
910 ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE0,
911 AR934X_OPER_MODE0_PHY_MII_EN);
913 pr_err("%s: invalid PHY interface mode\n",
918 pr_err("%s: unsupported chip, ctrl=%08x\n",
919 ag->dev->name, ctrl);
923 swdev->ports = AR7240_NUM_PORTS - 1;
924 swdev->cpu_port = AR7240_PORT_CPU;
925 swdev->vlans = AR7240_MAX_VLANS;
926 swdev->ops = &ar7240_ops;
928 if (register_switch(&as->swdev, ag->dev) < 0)
931 pr_info("%s: Found an %s\n", ag->dev->name, swdev->name);
933 /* initialize defaults */
934 for (i = 0; i < AR7240_MAX_VLANS; i++)
937 as->vlan_table[0] = ar7240sw_port_mask_all(as);
946 static void link_function(struct work_struct *work) {
947 struct ag71xx *ag = container_of(work, struct ag71xx, link_work.work);
952 for (i = 0; i < 4; i++) {
953 int link = ar7240sw_phy_read(ag->mii_bus, i, MII_BMSR);
954 if(link & BMSR_LSTATUS) {
960 spin_lock_irqsave(&ag->lock, flags);
961 if(status != ag->link) {
963 ag71xx_link_adjust(ag);
965 spin_unlock_irqrestore(&ag->lock, flags);
967 schedule_delayed_work(&ag->link_work, HZ / 2);
970 void ag71xx_ar7240_start(struct ag71xx *ag)
972 struct ar7240sw *as = ag->phy_priv;
976 ag->speed = SPEED_1000;
979 ar7240_set_addr(as, ag->dev->dev_addr);
980 ar7240_hw_apply(&as->swdev);
982 schedule_delayed_work(&ag->link_work, HZ / 10);
985 void ag71xx_ar7240_stop(struct ag71xx *ag)
987 cancel_delayed_work_sync(&ag->link_work);
990 int __devinit ag71xx_ar7240_init(struct ag71xx *ag)
994 as = ar7240_probe(ag);
1001 INIT_DELAYED_WORK(&ag->link_work, link_function);
1006 void ag71xx_ar7240_cleanup(struct ag71xx *ag)
1008 struct ar7240sw *as = ag->phy_priv;
1013 unregister_switch(&as->swdev);
1015 ag->phy_priv = NULL;