2 * Driver for the built-in ethernet switch of the Atheros AR7240 SoC
3 * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
4 * Copyright (c) 2010 Felix Fietkau <nbd@openwrt.org>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
12 #include <linux/etherdevice.h>
13 #include <linux/list.h>
14 #include <linux/netdevice.h>
15 #include <linux/phy.h>
16 #include <linux/mii.h>
17 #include <linux/bitops.h>
18 #include <linux/switch.h>
21 #define BITM(_count) (BIT(_count) - 1)
22 #define BITS(_shift, _count) (BITM(_count) << _shift)
24 #define AR7240_REG_MASK_CTRL 0x00
25 #define AR7240_MASK_CTRL_REVISION_M BITM(8)
26 #define AR7240_MASK_CTRL_VERSION_M BITM(8)
27 #define AR7240_MASK_CTRL_VERSION_S 8
28 #define AR7240_MASK_CTRL_VERSION_AR7240 0x01
29 #define AR7240_MASK_CTRL_VERSION_AR934X 0x02
30 #define AR7240_MASK_CTRL_SOFT_RESET BIT(31)
32 #define AR7240_REG_MAC_ADDR0 0x20
33 #define AR7240_REG_MAC_ADDR1 0x24
35 #define AR7240_REG_FLOOD_MASK 0x2c
36 #define AR7240_FLOOD_MASK_BROAD_TO_CPU BIT(26)
38 #define AR7240_REG_GLOBAL_CTRL 0x30
39 #define AR7240_GLOBAL_CTRL_MTU_M BITM(12)
41 #define AR7240_REG_VTU 0x0040
42 #define AR7240_VTU_OP BITM(3)
43 #define AR7240_VTU_OP_NOOP 0x0
44 #define AR7240_VTU_OP_FLUSH 0x1
45 #define AR7240_VTU_OP_LOAD 0x2
46 #define AR7240_VTU_OP_PURGE 0x3
47 #define AR7240_VTU_OP_REMOVE_PORT 0x4
48 #define AR7240_VTU_ACTIVE BIT(3)
49 #define AR7240_VTU_FULL BIT(4)
50 #define AR7240_VTU_PORT BITS(8, 4)
51 #define AR7240_VTU_PORT_S 8
52 #define AR7240_VTU_VID BITS(16, 12)
53 #define AR7240_VTU_VID_S 16
54 #define AR7240_VTU_PRIO BITS(28, 3)
55 #define AR7240_VTU_PRIO_S 28
56 #define AR7240_VTU_PRIO_EN BIT(31)
58 #define AR7240_REG_VTU_DATA 0x0044
59 #define AR7240_VTUDATA_MEMBER BITS(0, 10)
60 #define AR7240_VTUDATA_VALID BIT(11)
62 #define AR7240_REG_ATU 0x50
63 #define AR7240_ATU_FLUSH_ALL 0x1
65 #define AR7240_REG_AT_CTRL 0x5c
66 #define AR7240_AT_CTRL_AGE_TIME BITS(0, 15)
67 #define AR7240_AT_CTRL_AGE_EN BIT(17)
68 #define AR7240_AT_CTRL_LEARN_CHANGE BIT(18)
69 #define AR7240_AT_CTRL_ARP_EN BIT(20)
71 #define AR7240_REG_TAG_PRIORITY 0x70
73 #define AR7240_REG_SERVICE_TAG 0x74
74 #define AR7240_SERVICE_TAG_M BITM(16)
76 #define AR7240_REG_CPU_PORT 0x78
77 #define AR7240_MIRROR_PORT_S 4
78 #define AR7240_CPU_PORT_EN BIT(8)
80 #define AR7240_REG_MIB_FUNCTION0 0x80
81 #define AR7240_MIB_TIMER_M BITM(16)
82 #define AR7240_MIB_AT_HALF_EN BIT(16)
83 #define AR7240_MIB_BUSY BIT(17)
84 #define AR7240_MIB_FUNC_S 24
85 #define AR7240_MIB_FUNC_NO_OP 0x0
86 #define AR7240_MIB_FUNC_FLUSH 0x1
87 #define AR7240_MIB_FUNC_CAPTURE 0x3
89 #define AR7240_REG_MDIO_CTRL 0x98
90 #define AR7240_MDIO_CTRL_DATA_M BITM(16)
91 #define AR7240_MDIO_CTRL_REG_ADDR_S 16
92 #define AR7240_MDIO_CTRL_PHY_ADDR_S 21
93 #define AR7240_MDIO_CTRL_CMD_WRITE 0
94 #define AR7240_MDIO_CTRL_CMD_READ BIT(27)
95 #define AR7240_MDIO_CTRL_MASTER_EN BIT(30)
96 #define AR7240_MDIO_CTRL_BUSY BIT(31)
98 #define AR7240_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
100 #define AR7240_REG_PORT_STATUS(_port) (AR7240_REG_PORT_BASE((_port)) + 0x00)
101 #define AR7240_PORT_STATUS_SPEED_S 0
102 #define AR7240_PORT_STATUS_SPEED_M BITM(2)
103 #define AR7240_PORT_STATUS_SPEED_10 0
104 #define AR7240_PORT_STATUS_SPEED_100 1
105 #define AR7240_PORT_STATUS_SPEED_1000 2
106 #define AR7240_PORT_STATUS_TXMAC BIT(2)
107 #define AR7240_PORT_STATUS_RXMAC BIT(3)
108 #define AR7240_PORT_STATUS_TXFLOW BIT(4)
109 #define AR7240_PORT_STATUS_RXFLOW BIT(5)
110 #define AR7240_PORT_STATUS_DUPLEX BIT(6)
111 #define AR7240_PORT_STATUS_LINK_UP BIT(8)
112 #define AR7240_PORT_STATUS_LINK_AUTO BIT(9)
113 #define AR7240_PORT_STATUS_LINK_PAUSE BIT(10)
115 #define AR7240_REG_PORT_CTRL(_port) (AR7240_REG_PORT_BASE((_port)) + 0x04)
116 #define AR7240_PORT_CTRL_STATE_M BITM(3)
117 #define AR7240_PORT_CTRL_STATE_DISABLED 0
118 #define AR7240_PORT_CTRL_STATE_BLOCK 1
119 #define AR7240_PORT_CTRL_STATE_LISTEN 2
120 #define AR7240_PORT_CTRL_STATE_LEARN 3
121 #define AR7240_PORT_CTRL_STATE_FORWARD 4
122 #define AR7240_PORT_CTRL_LEARN_LOCK BIT(7)
123 #define AR7240_PORT_CTRL_VLAN_MODE_S 8
124 #define AR7240_PORT_CTRL_VLAN_MODE_KEEP 0
125 #define AR7240_PORT_CTRL_VLAN_MODE_STRIP 1
126 #define AR7240_PORT_CTRL_VLAN_MODE_ADD 2
127 #define AR7240_PORT_CTRL_VLAN_MODE_DOUBLE_TAG 3
128 #define AR7240_PORT_CTRL_IGMP_SNOOP BIT(10)
129 #define AR7240_PORT_CTRL_HEADER BIT(11)
130 #define AR7240_PORT_CTRL_MAC_LOOP BIT(12)
131 #define AR7240_PORT_CTRL_SINGLE_VLAN BIT(13)
132 #define AR7240_PORT_CTRL_LEARN BIT(14)
133 #define AR7240_PORT_CTRL_DOUBLE_TAG BIT(15)
134 #define AR7240_PORT_CTRL_MIRROR_TX BIT(16)
135 #define AR7240_PORT_CTRL_MIRROR_RX BIT(17)
137 #define AR7240_REG_PORT_VLAN(_port) (AR7240_REG_PORT_BASE((_port)) + 0x08)
139 #define AR7240_PORT_VLAN_DEFAULT_ID_S 0
140 #define AR7240_PORT_VLAN_DEST_PORTS_S 16
141 #define AR7240_PORT_VLAN_MODE_S 30
142 #define AR7240_PORT_VLAN_MODE_PORT_ONLY 0
143 #define AR7240_PORT_VLAN_MODE_PORT_FALLBACK 1
144 #define AR7240_PORT_VLAN_MODE_VLAN_ONLY 2
145 #define AR7240_PORT_VLAN_MODE_SECURE 3
148 #define AR7240_REG_STATS_BASE(_port) (0x20000 + (_port) * 0x100)
150 #define AR7240_STATS_RXBROAD 0x00
151 #define AR7240_STATS_RXPAUSE 0x04
152 #define AR7240_STATS_RXMULTI 0x08
153 #define AR7240_STATS_RXFCSERR 0x0c
154 #define AR7240_STATS_RXALIGNERR 0x10
155 #define AR7240_STATS_RXRUNT 0x14
156 #define AR7240_STATS_RXFRAGMENT 0x18
157 #define AR7240_STATS_RX64BYTE 0x1c
158 #define AR7240_STATS_RX128BYTE 0x20
159 #define AR7240_STATS_RX256BYTE 0x24
160 #define AR7240_STATS_RX512BYTE 0x28
161 #define AR7240_STATS_RX1024BYTE 0x2c
162 #define AR7240_STATS_RX1518BYTE 0x30
163 #define AR7240_STATS_RXMAXBYTE 0x34
164 #define AR7240_STATS_RXTOOLONG 0x38
165 #define AR7240_STATS_RXGOODBYTE 0x3c
166 #define AR7240_STATS_RXBADBYTE 0x44
167 #define AR7240_STATS_RXOVERFLOW 0x4c
168 #define AR7240_STATS_FILTERED 0x50
169 #define AR7240_STATS_TXBROAD 0x54
170 #define AR7240_STATS_TXPAUSE 0x58
171 #define AR7240_STATS_TXMULTI 0x5c
172 #define AR7240_STATS_TXUNDERRUN 0x60
173 #define AR7240_STATS_TX64BYTE 0x64
174 #define AR7240_STATS_TX128BYTE 0x68
175 #define AR7240_STATS_TX256BYTE 0x6c
176 #define AR7240_STATS_TX512BYTE 0x70
177 #define AR7240_STATS_TX1024BYTE 0x74
178 #define AR7240_STATS_TX1518BYTE 0x78
179 #define AR7240_STATS_TXMAXBYTE 0x7c
180 #define AR7240_STATS_TXOVERSIZE 0x80
181 #define AR7240_STATS_TXBYTE 0x84
182 #define AR7240_STATS_TXCOLLISION 0x8c
183 #define AR7240_STATS_TXABORTCOL 0x90
184 #define AR7240_STATS_TXMULTICOL 0x94
185 #define AR7240_STATS_TXSINGLECOL 0x98
186 #define AR7240_STATS_TXEXCDEFER 0x9c
187 #define AR7240_STATS_TXDEFER 0xa0
188 #define AR7240_STATS_TXLATECOL 0xa4
190 #define AR7240_PORT_CPU 0
191 #define AR7240_NUM_PORTS 6
192 #define AR7240_NUM_PHYS 5
194 #define AR7240_PHY_ID1 0x004d
195 #define AR7240_PHY_ID2 0xd041
197 #define AR934X_PHY_ID1 0x004d
198 #define AR934X_PHY_ID2 0xd042
200 #define AR7240_MAX_VLANS 16
202 #define AR934X_REG_OPER_MODE0 0x04
203 #define AR934X_OPER_MODE0_MAC_GMII_EN BIT(6)
204 #define AR934X_OPER_MODE0_PHY_MII_EN BIT(10)
206 #define AR934X_REG_OPER_MODE1 0x08
207 #define AR934X_REG_OPER_MODE1_PHY4_MII_EN BIT(28)
209 #define sw_to_ar7240(_dev) container_of(_dev, struct ar7240sw, swdev)
212 struct mii_bus *mii_bus;
213 struct ag71xx_switch_platform_data *swdata;
214 struct switch_dev swdev;
218 u16 vlan_id[AR7240_MAX_VLANS];
219 u8 vlan_table[AR7240_MAX_VLANS];
221 u16 pvid[AR7240_NUM_PORTS];
225 struct ar7240sw_hw_stat {
226 char string[ETH_GSTRING_LEN];
231 static DEFINE_MUTEX(reg_mutex);
233 static inline int sw_is_ar7240(struct ar7240sw *as)
235 return as->ver == AR7240_MASK_CTRL_VERSION_AR7240;
238 static inline int sw_is_ar934x(struct ar7240sw *as)
240 return as->ver == AR7240_MASK_CTRL_VERSION_AR934X;
243 static inline u32 ar7240sw_port_mask(struct ar7240sw *as, int port)
248 static inline u32 ar7240sw_port_mask_all(struct ar7240sw *as)
250 return BIT(as->swdev.ports) - 1;
253 static inline u32 ar7240sw_port_mask_but(struct ar7240sw *as, int port)
255 return ar7240sw_port_mask_all(as) & ~BIT(port);
258 static inline u16 mk_phy_addr(u32 reg)
260 return 0x17 & ((reg >> 4) | 0x10);
263 static inline u16 mk_phy_reg(u32 reg)
265 return (reg << 1) & 0x1e;
268 static inline u16 mk_high_addr(u32 reg)
270 return (reg >> 7) & 0x1ff;
273 static u32 __ar7240sw_reg_read(struct mii_bus *mii, u32 reg)
280 reg = (reg & 0xfffffffc) >> 2;
281 phy_addr = mk_phy_addr(reg);
282 phy_reg = mk_phy_reg(reg);
284 local_irq_save(flags);
285 ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg));
286 lo = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg);
287 hi = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg + 1);
288 local_irq_restore(flags);
290 return (hi << 16) | lo;
293 static void __ar7240sw_reg_write(struct mii_bus *mii, u32 reg, u32 val)
299 reg = (reg & 0xfffffffc) >> 2;
300 phy_addr = mk_phy_addr(reg);
301 phy_reg = mk_phy_reg(reg);
303 local_irq_save(flags);
304 ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg));
305 ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg + 1, (val >> 16));
306 ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg, (val & 0xffff));
307 local_irq_restore(flags);
310 static u32 ar7240sw_reg_read(struct mii_bus *mii, u32 reg_addr)
314 mutex_lock(®_mutex);
315 ret = __ar7240sw_reg_read(mii, reg_addr);
316 mutex_unlock(®_mutex);
321 static void ar7240sw_reg_write(struct mii_bus *mii, u32 reg_addr, u32 reg_val)
323 mutex_lock(®_mutex);
324 __ar7240sw_reg_write(mii, reg_addr, reg_val);
325 mutex_unlock(®_mutex);
328 static u32 ar7240sw_reg_rmw(struct mii_bus *mii, u32 reg, u32 mask, u32 val)
332 mutex_lock(®_mutex);
333 t = __ar7240sw_reg_read(mii, reg);
336 __ar7240sw_reg_write(mii, reg, t);
337 mutex_unlock(®_mutex);
342 static void ar7240sw_reg_set(struct mii_bus *mii, u32 reg, u32 val)
346 mutex_lock(®_mutex);
347 t = __ar7240sw_reg_read(mii, reg);
349 __ar7240sw_reg_write(mii, reg, t);
350 mutex_unlock(®_mutex);
353 static int __ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val,
358 for (i = 0; i < timeout; i++) {
361 t = __ar7240sw_reg_read(mii, reg);
362 if ((t & mask) == val)
371 static int ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val,
376 mutex_lock(®_mutex);
377 ret = __ar7240sw_reg_wait(mii, reg, mask, val, timeout);
378 mutex_unlock(®_mutex);
382 u16 ar7240sw_phy_read(struct mii_bus *mii, unsigned phy_addr,
388 if (phy_addr >= AR7240_NUM_PHYS)
391 mutex_lock(®_mutex);
392 t = (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) |
393 (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) |
394 AR7240_MDIO_CTRL_MASTER_EN |
395 AR7240_MDIO_CTRL_BUSY |
396 AR7240_MDIO_CTRL_CMD_READ;
398 __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t);
399 err = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL,
400 AR7240_MDIO_CTRL_BUSY, 0, 5);
402 val = __ar7240sw_reg_read(mii, AR7240_REG_MDIO_CTRL);
403 mutex_unlock(®_mutex);
405 return val & AR7240_MDIO_CTRL_DATA_M;
408 int ar7240sw_phy_write(struct mii_bus *mii, unsigned phy_addr,
409 unsigned reg_addr, u16 reg_val)
414 if (phy_addr >= AR7240_NUM_PHYS)
417 mutex_lock(®_mutex);
418 t = (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) |
419 (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) |
420 AR7240_MDIO_CTRL_MASTER_EN |
421 AR7240_MDIO_CTRL_BUSY |
422 AR7240_MDIO_CTRL_CMD_WRITE |
425 __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t);
426 ret = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL,
427 AR7240_MDIO_CTRL_BUSY, 0, 5);
428 mutex_unlock(®_mutex);
433 static void ar7240sw_disable_port(struct ar7240sw *as, unsigned port)
435 ar7240sw_reg_write(as->mii_bus, AR7240_REG_PORT_CTRL(port),
436 AR7240_PORT_CTRL_STATE_DISABLED);
439 static void ar7240sw_setup(struct ar7240sw *as)
441 struct mii_bus *mii = as->mii_bus;
443 /* Enable CPU port, and disable mirror port */
444 ar7240sw_reg_write(mii, AR7240_REG_CPU_PORT,
446 (15 << AR7240_MIRROR_PORT_S));
448 /* Setup TAG priority mapping */
449 ar7240sw_reg_write(mii, AR7240_REG_TAG_PRIORITY, 0xfa50);
451 /* Enable ARP frame acknowledge, aging, MAC replacing */
452 ar7240sw_reg_write(mii, AR7240_REG_AT_CTRL,
453 0x2b /* 5 min age time */ |
454 AR7240_AT_CTRL_AGE_EN |
455 AR7240_AT_CTRL_ARP_EN |
456 AR7240_AT_CTRL_LEARN_CHANGE);
458 /* Enable Broadcast frames transmitted to the CPU */
459 ar7240sw_reg_set(mii, AR7240_REG_FLOOD_MASK,
460 AR7240_FLOOD_MASK_BROAD_TO_CPU);
463 ar7240sw_reg_rmw(mii, AR7240_REG_GLOBAL_CTRL, AR7240_GLOBAL_CTRL_MTU_M,
466 /* setup Service TAG */
467 ar7240sw_reg_rmw(mii, AR7240_REG_SERVICE_TAG, AR7240_SERVICE_TAG_M, 0);
470 static int ar7240sw_reset(struct ar7240sw *as)
472 struct mii_bus *mii = as->mii_bus;
476 /* Set all ports to disabled state. */
477 for (i = 0; i < AR7240_NUM_PORTS; i++)
478 ar7240sw_disable_port(as, i);
480 /* Wait for transmit queues to drain. */
483 /* Reset the switch. */
484 ar7240sw_reg_write(mii, AR7240_REG_MASK_CTRL,
485 AR7240_MASK_CTRL_SOFT_RESET);
487 ret = ar7240sw_reg_wait(mii, AR7240_REG_MASK_CTRL,
488 AR7240_MASK_CTRL_SOFT_RESET, 0, 1000);
494 static void ar7240sw_setup_port(struct ar7240sw *as, unsigned port, u8 portmask)
496 struct mii_bus *mii = as->mii_bus;
500 ctrl = AR7240_PORT_CTRL_STATE_FORWARD | AR7240_PORT_CTRL_LEARN |
501 AR7240_PORT_CTRL_SINGLE_VLAN;
503 if (port == AR7240_PORT_CPU) {
504 ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port),
505 AR7240_PORT_STATUS_SPEED_1000 |
506 AR7240_PORT_STATUS_TXFLOW |
507 AR7240_PORT_STATUS_RXFLOW |
508 AR7240_PORT_STATUS_TXMAC |
509 AR7240_PORT_STATUS_RXMAC |
510 AR7240_PORT_STATUS_DUPLEX);
512 ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port),
513 AR7240_PORT_STATUS_LINK_AUTO);
516 /* Set the default VID for this port */
518 vlan = as->vlan_id[as->pvid[port]];
519 vlan |= AR7240_PORT_VLAN_MODE_SECURE <<
520 AR7240_PORT_VLAN_MODE_S;
523 vlan |= AR7240_PORT_VLAN_MODE_PORT_ONLY <<
524 AR7240_PORT_VLAN_MODE_S;
527 if (as->vlan && (as->vlan_tagged & BIT(port))) {
528 ctrl |= AR7240_PORT_CTRL_VLAN_MODE_ADD <<
529 AR7240_PORT_CTRL_VLAN_MODE_S;
531 ctrl |= AR7240_PORT_CTRL_VLAN_MODE_STRIP <<
532 AR7240_PORT_CTRL_VLAN_MODE_S;
536 if (port == AR7240_PORT_CPU)
537 portmask = ar7240sw_port_mask_but(as, AR7240_PORT_CPU);
539 portmask = ar7240sw_port_mask(as, AR7240_PORT_CPU);
542 /* allow the port to talk to all other ports, but exclude its
543 * own ID to prevent frames from being reflected back to the
544 * port that they came from */
545 portmask &= ar7240sw_port_mask_but(as, port);
547 /* set default VID and and destination ports for this VLAN */
548 vlan |= (portmask << AR7240_PORT_VLAN_DEST_PORTS_S);
550 ar7240sw_reg_write(mii, AR7240_REG_PORT_CTRL(port), ctrl);
551 ar7240sw_reg_write(mii, AR7240_REG_PORT_VLAN(port), vlan);
554 static int ar7240_set_addr(struct ar7240sw *as, u8 *addr)
556 struct mii_bus *mii = as->mii_bus;
559 t = (addr[4] << 8) | addr[5];
560 ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR0, t);
562 t = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
563 ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR1, t);
569 ar7240_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
570 struct switch_val *val)
572 struct ar7240sw *as = sw_to_ar7240(dev);
573 as->vlan_id[val->port_vlan] = val->value.i;
578 ar7240_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
579 struct switch_val *val)
581 struct ar7240sw *as = sw_to_ar7240(dev);
582 val->value.i = as->vlan_id[val->port_vlan];
587 ar7240_set_pvid(struct switch_dev *dev, int port, int vlan)
589 struct ar7240sw *as = sw_to_ar7240(dev);
591 /* make sure no invalid PVIDs get set */
593 if (vlan >= dev->vlans)
596 as->pvid[port] = vlan;
601 ar7240_get_pvid(struct switch_dev *dev, int port, int *vlan)
603 struct ar7240sw *as = sw_to_ar7240(dev);
604 *vlan = as->pvid[port];
609 ar7240_get_ports(struct switch_dev *dev, struct switch_val *val)
611 struct ar7240sw *as = sw_to_ar7240(dev);
612 u8 ports = as->vlan_table[val->port_vlan];
616 for (i = 0; i < as->swdev.ports; i++) {
617 struct switch_port *p;
619 if (!(ports & (1 << i)))
622 p = &val->value.ports[val->len++];
624 if (as->vlan_tagged & (1 << i))
625 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
633 ar7240_set_ports(struct switch_dev *dev, struct switch_val *val)
635 struct ar7240sw *as = sw_to_ar7240(dev);
636 u8 *vt = &as->vlan_table[val->port_vlan];
640 for (i = 0; i < val->len; i++) {
641 struct switch_port *p = &val->value.ports[i];
643 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED))
644 as->vlan_tagged |= (1 << p->id);
646 as->vlan_tagged &= ~(1 << p->id);
647 as->pvid[p->id] = val->port_vlan;
649 /* make sure that an untagged port does not
650 * appear in other vlans */
651 for (j = 0; j < AR7240_MAX_VLANS; j++) {
652 if (j == val->port_vlan)
654 as->vlan_table[j] &= ~(1 << p->id);
664 ar7240_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
665 struct switch_val *val)
667 struct ar7240sw *as = sw_to_ar7240(dev);
668 as->vlan = !!val->value.i;
673 ar7240_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
674 struct switch_val *val)
676 struct ar7240sw *as = sw_to_ar7240(dev);
677 val->value.i = as->vlan;
682 ar7240_speed_str(u32 status)
686 speed = (status >> AR7240_PORT_STATUS_SPEED_S) &
687 AR7240_PORT_STATUS_SPEED_M;
689 case AR7240_PORT_STATUS_SPEED_10:
691 case AR7240_PORT_STATUS_SPEED_100:
693 case AR7240_PORT_STATUS_SPEED_1000:
701 ar7240_port_get_link(struct switch_dev *dev, const struct switch_attr *attr,
702 struct switch_val *val)
704 struct ar7240sw *as = sw_to_ar7240(dev);
705 struct mii_bus *mii = as->mii_bus;
710 port = val->port_vlan;
712 memset(as->buf, '\0', sizeof(as->buf));
713 status = ar7240sw_reg_read(mii, AR7240_REG_PORT_STATUS(port));
715 if (status & AR7240_PORT_STATUS_LINK_UP) {
716 len = snprintf(as->buf, sizeof(as->buf),
717 "port:%d link:up speed:%s %s-duplex %s%s%s",
719 ar7240_speed_str(status),
720 (status & AR7240_PORT_STATUS_DUPLEX) ?
722 (status & AR7240_PORT_STATUS_TXFLOW) ?
724 (status & AR7240_PORT_STATUS_RXFLOW) ?
726 (status & AR7240_PORT_STATUS_LINK_AUTO) ?
729 len = snprintf(as->buf, sizeof(as->buf),
730 "port:%d link:down", port);
733 val->value.s = as->buf;
740 ar7240_vtu_op(struct ar7240sw *as, u32 op, u32 val)
742 struct mii_bus *mii = as->mii_bus;
744 if (ar7240sw_reg_wait(mii, AR7240_REG_VTU, AR7240_VTU_ACTIVE, 0, 5))
747 if ((op & AR7240_VTU_OP) == AR7240_VTU_OP_LOAD) {
748 val &= AR7240_VTUDATA_MEMBER;
749 val |= AR7240_VTUDATA_VALID;
750 ar7240sw_reg_write(mii, AR7240_REG_VTU_DATA, val);
752 op |= AR7240_VTU_ACTIVE;
753 ar7240sw_reg_write(mii, AR7240_REG_VTU, op);
757 ar7240_hw_apply(struct switch_dev *dev)
759 struct ar7240sw *as = sw_to_ar7240(dev);
760 u8 portmask[AR7240_NUM_PORTS];
763 /* flush all vlan translation unit entries */
764 ar7240_vtu_op(as, AR7240_VTU_OP_FLUSH, 0);
766 memset(portmask, 0, sizeof(portmask));
768 /* calculate the port destination masks and load vlans
769 * into the vlan translation unit */
770 for (j = 0; j < AR7240_MAX_VLANS; j++) {
771 u8 vp = as->vlan_table[j];
776 for (i = 0; i < as->swdev.ports; i++) {
779 portmask[i] |= vp & ~mask;
784 (as->vlan_id[j] << AR7240_VTU_VID_S),
789 * isolate all ports, but connect them to the cpu port */
790 for (i = 0; i < as->swdev.ports; i++) {
791 if (i == AR7240_PORT_CPU)
794 portmask[i] = 1 << AR7240_PORT_CPU;
795 portmask[AR7240_PORT_CPU] |= (1 << i);
799 /* update the port destination mask registers and tag settings */
800 for (i = 0; i < as->swdev.ports; i++)
801 ar7240sw_setup_port(as, i, portmask[i]);
807 ar7240_reset_switch(struct switch_dev *dev)
809 struct ar7240sw *as = sw_to_ar7240(dev);
814 static struct switch_attr ar7240_globals[] = {
816 .type = SWITCH_TYPE_INT,
817 .name = "enable_vlan",
818 .description = "Enable VLAN mode",
819 .set = ar7240_set_vlan,
820 .get = ar7240_get_vlan,
825 static struct switch_attr ar7240_port[] = {
827 .type = SWITCH_TYPE_STRING,
829 .description = "Get port link information",
832 .get = ar7240_port_get_link,
836 static struct switch_attr ar7240_vlan[] = {
838 .type = SWITCH_TYPE_INT,
840 .description = "VLAN ID",
841 .set = ar7240_set_vid,
842 .get = ar7240_get_vid,
847 static const struct switch_dev_ops ar7240_ops = {
849 .attr = ar7240_globals,
850 .n_attr = ARRAY_SIZE(ar7240_globals),
854 .n_attr = ARRAY_SIZE(ar7240_port),
858 .n_attr = ARRAY_SIZE(ar7240_vlan),
860 .get_port_pvid = ar7240_get_pvid,
861 .set_port_pvid = ar7240_set_pvid,
862 .get_vlan_ports = ar7240_get_ports,
863 .set_vlan_ports = ar7240_set_ports,
864 .apply_config = ar7240_hw_apply,
865 .reset_switch = ar7240_reset_switch,
868 static struct ar7240sw *ar7240_probe(struct ag71xx *ag)
870 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
871 struct mii_bus *mii = ag->mii_bus;
873 struct switch_dev *swdev;
879 phy_id1 = ar7240sw_phy_read(mii, 0, MII_PHYSID1);
880 phy_id2 = ar7240sw_phy_read(mii, 0, MII_PHYSID2);
881 if ((phy_id1 != AR7240_PHY_ID1 || phy_id2 != AR7240_PHY_ID2) &&
882 (phy_id1 != AR934X_PHY_ID1 || phy_id2 != AR934X_PHY_ID2)) {
883 pr_err("%s: unknown phy id '%04x:%04x'\n",
884 ag->dev->name, phy_id1, phy_id2);
888 as = kzalloc(sizeof(*as), GFP_KERNEL);
893 as->swdata = pdata->switch_data;
897 ctrl = ar7240sw_reg_read(mii, AR7240_REG_MASK_CTRL);
898 as->ver = (ctrl >> AR7240_MASK_CTRL_VERSION_S) &
899 AR7240_MASK_CTRL_VERSION_M;
901 if (sw_is_ar7240(as)) {
902 swdev->name = "AR7240/AR9330 built-in switch";
903 } else if (sw_is_ar934x(as)) {
904 swdev->name = "AR934X built-in switch";
906 if (pdata->phy_if_mode == PHY_INTERFACE_MODE_GMII) {
907 ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE0,
908 AR934X_OPER_MODE0_MAC_GMII_EN);
909 } else if (pdata->phy_if_mode == PHY_INTERFACE_MODE_MII) {
910 ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE0,
911 AR934X_OPER_MODE0_PHY_MII_EN);
913 pr_err("%s: invalid PHY interface mode\n",
918 if (as->swdata->phy4_mii_en)
919 ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE1,
920 AR934X_REG_OPER_MODE1_PHY4_MII_EN);
922 pr_err("%s: unsupported chip, ctrl=%08x\n",
923 ag->dev->name, ctrl);
927 swdev->ports = AR7240_NUM_PORTS - 1;
928 swdev->cpu_port = AR7240_PORT_CPU;
929 swdev->vlans = AR7240_MAX_VLANS;
930 swdev->ops = &ar7240_ops;
932 if (register_switch(&as->swdev, ag->dev) < 0)
935 pr_info("%s: Found an %s\n", ag->dev->name, swdev->name);
937 /* initialize defaults */
938 for (i = 0; i < AR7240_MAX_VLANS; i++)
941 as->vlan_table[0] = ar7240sw_port_mask_all(as);
950 static void link_function(struct work_struct *work) {
951 struct ag71xx *ag = container_of(work, struct ag71xx, link_work.work);
956 for (i = 0; i < 4; i++) {
957 int link = ar7240sw_phy_read(ag->mii_bus, i, MII_BMSR);
958 if(link & BMSR_LSTATUS) {
964 spin_lock_irqsave(&ag->lock, flags);
965 if(status != ag->link) {
967 ag71xx_link_adjust(ag);
969 spin_unlock_irqrestore(&ag->lock, flags);
971 schedule_delayed_work(&ag->link_work, HZ / 2);
974 void ag71xx_ar7240_start(struct ag71xx *ag)
976 struct ar7240sw *as = ag->phy_priv;
980 ag->speed = SPEED_1000;
983 ar7240_set_addr(as, ag->dev->dev_addr);
984 ar7240_hw_apply(&as->swdev);
986 schedule_delayed_work(&ag->link_work, HZ / 10);
989 void ag71xx_ar7240_stop(struct ag71xx *ag)
991 cancel_delayed_work_sync(&ag->link_work);
994 int __devinit ag71xx_ar7240_init(struct ag71xx *ag)
998 as = ar7240_probe(ag);
1005 INIT_DELAYED_WORK(&ag->link_work, link_function);
1010 void ag71xx_ar7240_cleanup(struct ag71xx *ag)
1012 struct ar7240sw *as = ag->phy_priv;
1017 unregister_switch(&as->swdev);
1019 ag->phy_priv = NULL;