2 * Atheros AR71xx built-in ethernet mac driver
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 * Based on Atheros' AG7100 driver
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
17 #include <linux/kernel.h>
18 #include <linux/version.h>
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/types.h>
22 #include <linux/random.h>
23 #include <linux/spinlock.h>
24 #include <linux/interrupt.h>
25 #include <linux/platform_device.h>
26 #include <linux/ethtool.h>
27 #include <linux/etherdevice.h>
28 #include <linux/if_vlan.h>
29 #include <linux/phy.h>
30 #include <linux/skbuff.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/workqueue.h>
34 #include <linux/bitops.h>
36 #include <asm/mach-ar71xx/ar71xx.h>
37 #include <asm/mach-ar71xx/platform.h>
39 #define AG71XX_DRV_NAME "ag71xx"
40 #define AG71XX_DRV_VERSION "0.5.35"
42 #define AG71XX_NAPI_WEIGHT 64
43 #define AG71XX_OOM_REFILL (1 + HZ/10)
45 #define AG71XX_INT_ERR (AG71XX_INT_RX_BE | AG71XX_INT_TX_BE)
46 #define AG71XX_INT_TX (AG71XX_INT_TX_PS)
47 #define AG71XX_INT_RX (AG71XX_INT_RX_PR | AG71XX_INT_RX_OF)
49 #define AG71XX_INT_POLL (AG71XX_INT_RX | AG71XX_INT_TX)
50 #define AG71XX_INT_INIT (AG71XX_INT_ERR | AG71XX_INT_POLL)
52 #define AG71XX_TX_MTU_LEN 1540
53 #define AG71XX_RX_PKT_RESERVE 64
54 #define AG71XX_RX_PKT_SIZE \
55 (AG71XX_RX_PKT_RESERVE + ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
57 #define AG71XX_TX_RING_SIZE_DEFAULT 64
58 #define AG71XX_RX_RING_SIZE_DEFAULT 128
60 #define AG71XX_TX_RING_SIZE_MAX 256
61 #define AG71XX_RX_RING_SIZE_MAX 256
63 #ifdef CONFIG_AG71XX_DEBUG
64 #define DBG(fmt, args...) printk(KERN_DEBUG fmt, ## args)
66 #define DBG(fmt, args...) do {} while (0)
69 #define ag71xx_assert(_cond) \
73 printk("%s,%d: assertion failed\n", __FILE__, __LINE__); \
80 #define DESC_EMPTY BIT(31)
81 #define DESC_MORE BIT(24)
82 #define DESC_PKTLEN_M 0xfff
85 } __attribute__((aligned(4)));
89 struct ag71xx_desc *desc;
91 unsigned long timestamp;
95 struct ag71xx_buf *buf;
98 unsigned int desc_size;
105 struct mii_bus *mii_bus;
106 int mii_irq[PHY_MAX_ADDR];
107 void __iomem *mdio_base;
108 struct ag71xx_mdio_platform_data *pdata;
111 struct ag71xx_int_stats {
121 struct ag71xx_napi_stats {
122 unsigned long napi_calls;
123 unsigned long rx_count;
124 unsigned long rx_packets;
125 unsigned long rx_packets_max;
126 unsigned long tx_count;
127 unsigned long tx_packets;
128 unsigned long tx_packets_max;
130 unsigned long rx[AG71XX_NAPI_WEIGHT + 1];
131 unsigned long tx[AG71XX_NAPI_WEIGHT + 1];
134 struct ag71xx_debug {
135 struct dentry *debugfs_dir;
137 struct ag71xx_int_stats int_stats;
138 struct ag71xx_napi_stats napi_stats;
142 void __iomem *mac_base;
143 void __iomem *mii_ctrl;
146 struct platform_device *pdev;
147 struct net_device *dev;
148 struct napi_struct napi;
151 struct ag71xx_desc *stop_desc;
152 dma_addr_t stop_desc_dma;
154 struct ag71xx_ring rx_ring;
155 struct ag71xx_ring tx_ring;
157 struct mii_bus *mii_bus;
158 struct phy_device *phy_dev;
165 struct work_struct restart_work;
166 struct delayed_work link_work;
167 struct timer_list oom_timer;
169 #ifdef CONFIG_AG71XX_DEBUG_FS
170 struct ag71xx_debug debug;
174 extern struct ethtool_ops ag71xx_ethtool_ops;
175 void ag71xx_link_adjust(struct ag71xx *ag);
177 int ag71xx_mdio_driver_init(void) __init;
178 void ag71xx_mdio_driver_exit(void);
180 int ag71xx_phy_connect(struct ag71xx *ag);
181 void ag71xx_phy_disconnect(struct ag71xx *ag);
182 void ag71xx_phy_start(struct ag71xx *ag);
183 void ag71xx_phy_stop(struct ag71xx *ag);
185 static inline struct ag71xx_platform_data *ag71xx_get_pdata(struct ag71xx *ag)
187 return ag->pdev->dev.platform_data;
190 static inline int ag71xx_desc_empty(struct ag71xx_desc *desc)
192 return (desc->ctrl & DESC_EMPTY) != 0;
195 static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc)
197 return desc->ctrl & DESC_PKTLEN_M;
200 /* Register offsets */
201 #define AG71XX_REG_MAC_CFG1 0x0000
202 #define AG71XX_REG_MAC_CFG2 0x0004
203 #define AG71XX_REG_MAC_IPG 0x0008
204 #define AG71XX_REG_MAC_HDX 0x000c
205 #define AG71XX_REG_MAC_MFL 0x0010
206 #define AG71XX_REG_MII_CFG 0x0020
207 #define AG71XX_REG_MII_CMD 0x0024
208 #define AG71XX_REG_MII_ADDR 0x0028
209 #define AG71XX_REG_MII_CTRL 0x002c
210 #define AG71XX_REG_MII_STATUS 0x0030
211 #define AG71XX_REG_MII_IND 0x0034
212 #define AG71XX_REG_MAC_IFCTL 0x0038
213 #define AG71XX_REG_MAC_ADDR1 0x0040
214 #define AG71XX_REG_MAC_ADDR2 0x0044
215 #define AG71XX_REG_FIFO_CFG0 0x0048
216 #define AG71XX_REG_FIFO_CFG1 0x004c
217 #define AG71XX_REG_FIFO_CFG2 0x0050
218 #define AG71XX_REG_FIFO_CFG3 0x0054
219 #define AG71XX_REG_FIFO_CFG4 0x0058
220 #define AG71XX_REG_FIFO_CFG5 0x005c
221 #define AG71XX_REG_FIFO_RAM0 0x0060
222 #define AG71XX_REG_FIFO_RAM1 0x0064
223 #define AG71XX_REG_FIFO_RAM2 0x0068
224 #define AG71XX_REG_FIFO_RAM3 0x006c
225 #define AG71XX_REG_FIFO_RAM4 0x0070
226 #define AG71XX_REG_FIFO_RAM5 0x0074
227 #define AG71XX_REG_FIFO_RAM6 0x0078
228 #define AG71XX_REG_FIFO_RAM7 0x007c
230 #define AG71XX_REG_TX_CTRL 0x0180
231 #define AG71XX_REG_TX_DESC 0x0184
232 #define AG71XX_REG_TX_STATUS 0x0188
233 #define AG71XX_REG_RX_CTRL 0x018c
234 #define AG71XX_REG_RX_DESC 0x0190
235 #define AG71XX_REG_RX_STATUS 0x0194
236 #define AG71XX_REG_INT_ENABLE 0x0198
237 #define AG71XX_REG_INT_STATUS 0x019c
239 #define AG71XX_REG_FIFO_DEPTH 0x01a8
240 #define AG71XX_REG_RX_SM 0x01b0
241 #define AG71XX_REG_TX_SM 0x01b4
243 #define MAC_CFG1_TXE BIT(0) /* Tx Enable */
244 #define MAC_CFG1_STX BIT(1) /* Synchronize Tx Enable */
245 #define MAC_CFG1_RXE BIT(2) /* Rx Enable */
246 #define MAC_CFG1_SRX BIT(3) /* Synchronize Rx Enable */
247 #define MAC_CFG1_TFC BIT(4) /* Tx Flow Control Enable */
248 #define MAC_CFG1_RFC BIT(5) /* Rx Flow Control Enable */
249 #define MAC_CFG1_LB BIT(8) /* Loopback mode */
250 #define MAC_CFG1_SR BIT(31) /* Soft Reset */
252 #define MAC_CFG2_FDX BIT(0)
253 #define MAC_CFG2_CRC_EN BIT(1)
254 #define MAC_CFG2_PAD_CRC_EN BIT(2)
255 #define MAC_CFG2_LEN_CHECK BIT(4)
256 #define MAC_CFG2_HUGE_FRAME_EN BIT(5)
257 #define MAC_CFG2_IF_1000 BIT(9)
258 #define MAC_CFG2_IF_10_100 BIT(8)
260 #define FIFO_CFG0_WTM BIT(0) /* Watermark Module */
261 #define FIFO_CFG0_RXS BIT(1) /* Rx System Module */
262 #define FIFO_CFG0_RXF BIT(2) /* Rx Fabric Module */
263 #define FIFO_CFG0_TXS BIT(3) /* Tx System Module */
264 #define FIFO_CFG0_TXF BIT(4) /* Tx Fabric Module */
265 #define FIFO_CFG0_ALL (FIFO_CFG0_WTM | FIFO_CFG0_RXS | FIFO_CFG0_RXF \
266 | FIFO_CFG0_TXS | FIFO_CFG0_TXF)
268 #define FIFO_CFG0_ENABLE_SHIFT 8
270 #define FIFO_CFG4_DE BIT(0) /* Drop Event */
271 #define FIFO_CFG4_DV BIT(1) /* RX_DV Event */
272 #define FIFO_CFG4_FC BIT(2) /* False Carrier */
273 #define FIFO_CFG4_CE BIT(3) /* Code Error */
274 #define FIFO_CFG4_CR BIT(4) /* CRC error */
275 #define FIFO_CFG4_LM BIT(5) /* Length Mismatch */
276 #define FIFO_CFG4_LO BIT(6) /* Length out of range */
277 #define FIFO_CFG4_OK BIT(7) /* Packet is OK */
278 #define FIFO_CFG4_MC BIT(8) /* Multicast Packet */
279 #define FIFO_CFG4_BC BIT(9) /* Broadcast Packet */
280 #define FIFO_CFG4_DR BIT(10) /* Dribble */
281 #define FIFO_CFG4_LE BIT(11) /* Long Event */
282 #define FIFO_CFG4_CF BIT(12) /* Control Frame */
283 #define FIFO_CFG4_PF BIT(13) /* Pause Frame */
284 #define FIFO_CFG4_UO BIT(14) /* Unsupported Opcode */
285 #define FIFO_CFG4_VT BIT(15) /* VLAN tag detected */
286 #define FIFO_CFG4_FT BIT(16) /* Frame Truncated */
287 #define FIFO_CFG4_UC BIT(17) /* Unicast Packet */
289 #define FIFO_CFG5_DE BIT(0) /* Drop Event */
290 #define FIFO_CFG5_DV BIT(1) /* RX_DV Event */
291 #define FIFO_CFG5_FC BIT(2) /* False Carrier */
292 #define FIFO_CFG5_CE BIT(3) /* Code Error */
293 #define FIFO_CFG5_LM BIT(4) /* Length Mismatch */
294 #define FIFO_CFG5_LO BIT(5) /* Length Out of Range */
295 #define FIFO_CFG5_OK BIT(6) /* Packet is OK */
296 #define FIFO_CFG5_MC BIT(7) /* Multicast Packet */
297 #define FIFO_CFG5_BC BIT(8) /* Broadcast Packet */
298 #define FIFO_CFG5_DR BIT(9) /* Dribble */
299 #define FIFO_CFG5_CF BIT(10) /* Control Frame */
300 #define FIFO_CFG5_PF BIT(11) /* Pause Frame */
301 #define FIFO_CFG5_UO BIT(12) /* Unsupported Opcode */
302 #define FIFO_CFG5_VT BIT(13) /* VLAN tag detected */
303 #define FIFO_CFG5_LE BIT(14) /* Long Event */
304 #define FIFO_CFG5_FT BIT(15) /* Frame Truncated */
305 #define FIFO_CFG5_16 BIT(16) /* unknown */
306 #define FIFO_CFG5_17 BIT(17) /* unknown */
307 #define FIFO_CFG5_SF BIT(18) /* Short Frame */
308 #define FIFO_CFG5_BM BIT(19) /* Byte Mode */
310 #define AG71XX_INT_TX_PS BIT(0)
311 #define AG71XX_INT_TX_UR BIT(1)
312 #define AG71XX_INT_TX_BE BIT(3)
313 #define AG71XX_INT_RX_PR BIT(4)
314 #define AG71XX_INT_RX_OF BIT(6)
315 #define AG71XX_INT_RX_BE BIT(7)
317 #define MAC_IFCTL_SPEED BIT(16)
319 #define MII_CFG_CLK_DIV_4 0
320 #define MII_CFG_CLK_DIV_6 2
321 #define MII_CFG_CLK_DIV_8 3
322 #define MII_CFG_CLK_DIV_10 4
323 #define MII_CFG_CLK_DIV_14 5
324 #define MII_CFG_CLK_DIV_20 6
325 #define MII_CFG_CLK_DIV_28 7
326 #define MII_CFG_RESET BIT(31)
328 #define MII_CMD_WRITE 0x0
329 #define MII_CMD_READ 0x1
330 #define MII_ADDR_SHIFT 8
331 #define MII_IND_BUSY BIT(0)
332 #define MII_IND_INVALID BIT(2)
334 #define TX_CTRL_TXE BIT(0) /* Tx Enable */
336 #define TX_STATUS_PS BIT(0) /* Packet Sent */
337 #define TX_STATUS_UR BIT(1) /* Tx Underrun */
338 #define TX_STATUS_BE BIT(3) /* Bus Error */
340 #define RX_CTRL_RXE BIT(0) /* Rx Enable */
342 #define RX_STATUS_PR BIT(0) /* Packet Received */
343 #define RX_STATUS_OF BIT(2) /* Rx Overflow */
344 #define RX_STATUS_BE BIT(3) /* Bus Error */
346 #define MII_CTRL_SPEED_SHIFT 4
347 #define MII_CTRL_SPEED_MASK 3
348 #define MII_CTRL_SPEED_10 0
349 #define MII_CTRL_SPEED_100 1
350 #define MII_CTRL_SPEED_1000 2
352 static inline void ag71xx_check_reg_offset(struct ag71xx *ag, unsigned reg)
355 case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
356 case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_TX_SM:
357 case AG71XX_REG_MII_CFG:
365 static inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value)
367 ag71xx_check_reg_offset(ag, reg);
369 __raw_writel(value, ag->mac_base + reg);
371 (void) __raw_readl(ag->mac_base + reg);
374 static inline u32 ag71xx_rr(struct ag71xx *ag, unsigned reg)
376 ag71xx_check_reg_offset(ag, reg);
378 return __raw_readl(ag->mac_base + reg);
381 static inline void ag71xx_sb(struct ag71xx *ag, unsigned reg, u32 mask)
385 ag71xx_check_reg_offset(ag, reg);
387 r = ag->mac_base + reg;
388 __raw_writel(__raw_readl(r) | mask, r);
390 (void)__raw_readl(r);
393 static inline void ag71xx_cb(struct ag71xx *ag, unsigned reg, u32 mask)
397 ag71xx_check_reg_offset(ag, reg);
399 r = ag->mac_base + reg;
400 __raw_writel(__raw_readl(r) & ~mask, r);
402 (void) __raw_readl(r);
405 static inline void ag71xx_int_enable(struct ag71xx *ag, u32 ints)
407 ag71xx_sb(ag, AG71XX_REG_INT_ENABLE, ints);
410 static inline void ag71xx_int_disable(struct ag71xx *ag, u32 ints)
412 ag71xx_cb(ag, AG71XX_REG_INT_ENABLE, ints);
415 static inline void ag71xx_mii_ctrl_wr(struct ag71xx *ag, u32 value)
417 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
419 if (pdata->is_ar724x)
422 __raw_writel(value, ag->mii_ctrl);
425 __raw_readl(ag->mii_ctrl);
428 static inline u32 ag71xx_mii_ctrl_rr(struct ag71xx *ag)
430 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
432 if (pdata->is_ar724x)
435 return __raw_readl(ag->mii_ctrl);
438 static inline void ag71xx_mii_ctrl_set_speed(struct ag71xx *ag,
443 t = ag71xx_mii_ctrl_rr(ag);
444 t &= ~(MII_CTRL_SPEED_MASK << MII_CTRL_SPEED_SHIFT);
445 t |= (speed & MII_CTRL_SPEED_MASK) << MII_CTRL_SPEED_SHIFT;
446 ag71xx_mii_ctrl_wr(ag, t);
449 #ifdef CONFIG_AG71XX_AR8216_SUPPORT
450 void ag71xx_add_ar8216_header(struct ag71xx *ag, struct sk_buff *skb);
451 int ag71xx_remove_ar8216_header(struct ag71xx *ag, struct sk_buff *skb,
453 static inline int ag71xx_has_ar8216(struct ag71xx *ag)
455 return ag71xx_get_pdata(ag)->has_ar8216;
458 static inline void ag71xx_add_ar8216_header(struct ag71xx *ag,
463 static inline int ag71xx_remove_ar8216_header(struct ag71xx *ag,
469 static inline int ag71xx_has_ar8216(struct ag71xx *ag)
475 #ifdef CONFIG_AG71XX_DEBUG_FS
476 int ag71xx_debugfs_root_init(void);
477 void ag71xx_debugfs_root_exit(void);
478 int ag71xx_debugfs_init(struct ag71xx *ag);
479 void ag71xx_debugfs_exit(struct ag71xx *ag);
480 void ag71xx_debugfs_update_int_stats(struct ag71xx *ag, u32 status);
481 void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag, int rx, int tx);
483 static inline int ag71xx_debugfs_root_init(void) { return 0; }
484 static inline void ag71xx_debugfs_root_exit(void) {}
485 static inline int ag71xx_debugfs_init(struct ag71xx *ag) { return 0; }
486 static inline void ag71xx_debugfs_exit(struct ag71xx *ag) {}
487 static inline void ag71xx_debugfs_update_int_stats(struct ag71xx *ag,
489 static inline void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag,
491 #endif /* CONFIG_AG71XX_DEBUG_FS */
493 void ag71xx_ar7240_start(struct ag71xx *ag);
494 void ag71xx_ar7240_stop(struct ag71xx *ag);
495 int ag71xx_ar7240_init(struct ag71xx *ag);
496 void ag71xx_ar7240_cleanup(struct ag71xx *ag);
498 int ag71xx_mdio_mii_read(struct ag71xx_mdio *am, int addr, int reg);
499 void ag71xx_mdio_mii_write(struct ag71xx_mdio *am, int addr, int reg, u16 val);
501 u16 ar7240sw_phy_read(struct mii_bus *mii, unsigned phy_addr,
503 int ar7240sw_phy_write(struct mii_bus *mii, unsigned phy_addr,
504 unsigned reg_addr, u16 reg_val);
506 #endif /* _AG71XX_H */