2 * Driver for the built-in NAND controller of the Atheros AR934x SoCs
4 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
13 #include <linux/module.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/mtd/mtd.h>
16 #include <linux/mtd/nand.h>
17 #include <linux/mtd/partitions.h>
18 #include <linux/platform_device.h>
19 #include <linux/delay.h>
20 #include <linux/slab.h>
22 #include <linux/platform/ar934x_nfc.h>
24 #define AR934X_NFC_REG_CMD 0x00
25 #define AR934X_NFC_REG_CTRL 0x04
26 #define AR934X_NFC_REG_STATUS 0x08
27 #define AR934X_NFC_REG_INT_MASK 0x0c
28 #define AR934X_NFC_REG_INT_STATUS 0x10
29 #define AR934X_NFC_REG_ECC_CTRL 0x14
30 #define AR934X_NFC_REG_ECC_OFFSET 0x18
31 #define AR934X_NFC_REG_ADDR0_0 0x1c
32 #define AR934X_NFC_REG_ADDR0_1 0x24
33 #define AR934X_NFC_REG_ADDR1_0 0x20
34 #define AR934X_NFC_REG_ADDR1_1 0x28
35 #define AR934X_NFC_REG_SPARE_SIZE 0x30
36 #define AR934X_NFC_REG_PROTECT 0x38
37 #define AR934X_NFC_REG_LOOKUP_EN 0x40
38 #define AR934X_NFC_REG_LOOKUP(_x) (0x44 + (_i) * 4)
39 #define AR934X_NFC_REG_DMA_ADDR 0x64
40 #define AR934X_NFC_REG_DMA_COUNT 0x68
41 #define AR934X_NFC_REG_DMA_CTRL 0x6c
42 #define AR934X_NFC_REG_MEM_CTRL 0x80
43 #define AR934X_NFC_REG_DATA_SIZE 0x84
44 #define AR934X_NFC_REG_READ_STATUS 0x88
45 #define AR934X_NFC_REG_TIME_SEQ 0x8c
46 #define AR934X_NFC_REG_TIMINGS_ASYN 0x90
47 #define AR934X_NFC_REG_TIMINGS_SYN 0x94
48 #define AR934X_NFC_REG_FIFO_DATA 0x98
49 #define AR934X_NFC_REG_TIME_MODE 0x9c
50 #define AR934X_NFC_REG_DMA_ADDR_OFFS 0xa0
51 #define AR934X_NFC_REG_FIFO_INIT 0xb0
52 #define AR934X_NFC_REG_GEN_SEQ_CTRL 0xb4
54 #define AR934X_NFC_CMD_CMD_SEQ_S 0
55 #define AR934X_NFC_CMD_CMD_SEQ_M 0x3f
56 #define AR934X_NFC_CMD_SEQ_1C 0x00
57 #define AR934X_NFC_CMD_SEQ_ERASE 0x0e
58 #define AR934X_NFC_CMD_SEQ_12 0x0c
59 #define AR934X_NFC_CMD_SEQ_1C1AXR 0x21
60 #define AR934X_NFC_CMD_SEQ_S 0x24
61 #define AR934X_NFC_CMD_SEQ_1C3AXR 0x27
62 #define AR934X_NFC_CMD_SEQ_1C5A1CXR 0x2a
63 #define AR934X_NFC_CMD_SEQ_18 0x32
64 #define AR934X_NFC_CMD_INPUT_SEL_SIU 0
65 #define AR934X_NFC_CMD_INPUT_SEL_DMA BIT(6)
66 #define AR934X_NFC_CMD_ADDR_SEL_0 0
67 #define AR934X_NFC_CMD_ADDR_SEL_1 BIT(7)
68 #define AR934X_NFC_CMD_CMD0_S 8
69 #define AR934X_NFC_CMD_CMD0_M 0xff
70 #define AR934X_NFC_CMD_CMD1_S 16
71 #define AR934X_NFC_CMD_CMD1_M 0xff
72 #define AR934X_NFC_CMD_CMD2_S 24
73 #define AR934X_NFC_CMD_CMD2_M 0xff
75 #define AR934X_NFC_CTRL_ADDR_CYCLE0_M 0x7
76 #define AR934X_NFC_CTRL_ADDR_CYCLE0_S 0
77 #define AR934X_NFC_CTRL_SPARE_EN BIT(3)
78 #define AR934X_NFC_CTRL_INT_EN BIT(4)
79 #define AR934X_NFC_CTRL_ECC_EN BIT(5)
80 #define AR934X_NFC_CTRL_BLOCK_SIZE_S 6
81 #define AR934X_NFC_CTRL_BLOCK_SIZE_M 0x3
82 #define AR934X_NFC_CTRL_BLOCK_SIZE_32 0
83 #define AR934X_NFC_CTRL_BLOCK_SIZE_64 1
84 #define AR934X_NFC_CTRL_BLOCK_SIZE_128 2
85 #define AR934X_NFC_CTRL_BLOCK_SIZE_256 3
86 #define AR934X_NFC_CTRL_PAGE_SIZE_S 8
87 #define AR934X_NFC_CTRL_PAGE_SIZE_M 0x7
88 #define AR934X_NFC_CTRL_PAGE_SIZE_256 0
89 #define AR934X_NFC_CTRL_PAGE_SIZE_512 1
90 #define AR934X_NFC_CTRL_PAGE_SIZE_1024 2
91 #define AR934X_NFC_CTRL_PAGE_SIZE_2048 3
92 #define AR934X_NFC_CTRL_PAGE_SIZE_4096 4
93 #define AR934X_NFC_CTRL_PAGE_SIZE_8192 5
94 #define AR934X_NFC_CTRL_PAGE_SIZE_16384 6
95 #define AR934X_NFC_CTRL_CUSTOM_SIZE_EN BIT(11)
96 #define AR934X_NFC_CTRL_IO_WIDTH_8BITS 0
97 #define AR934X_NFC_CTRL_IO_WIDTH_16BITS BIT(12)
98 #define AR934X_NFC_CTRL_LOOKUP_EN BIT(13)
99 #define AR934X_NFC_CTRL_PROT_EN BIT(14)
100 #define AR934X_NFC_CTRL_WORK_MODE_ASYNC 0
101 #define AR934X_NFC_CTRL_WORK_MODE_SYNC BIT(15)
102 #define AR934X_NFC_CTRL_ADDR0_AUTO_INC BIT(16)
103 #define AR934X_NFC_CTRL_ADDR1_AUTO_INC BIT(17)
104 #define AR934X_NFC_CTRL_ADDR_CYCLE1_M 0x7
105 #define AR934X_NFC_CTRL_ADDR_CYCLE1_S 18
106 #define AR934X_NFC_CTRL_SMALL_PAGE BIT(21)
108 #define AR934X_NFC_DMA_CTRL_DMA_START BIT(7)
109 #define AR934X_NFC_DMA_CTRL_DMA_DIR_WRITE 0
110 #define AR934X_NFC_DMA_CTRL_DMA_DIR_READ BIT(6)
111 #define AR934X_NFC_DMA_CTRL_DMA_MODE_SG BIT(5)
112 #define AR934X_NFC_DMA_CTRL_DMA_BURST_S 2
113 #define AR934X_NFC_DMA_CTRL_DMA_BURST_0 0
114 #define AR934X_NFC_DMA_CTRL_DMA_BURST_1 1
115 #define AR934X_NFC_DMA_CTRL_DMA_BURST_2 2
116 #define AR934X_NFC_DMA_CTRL_DMA_BURST_3 3
117 #define AR934X_NFC_DMA_CTRL_DMA_BURST_4 4
118 #define AR934X_NFC_DMA_CTRL_DMA_BURST_5 5
119 #define AR934X_NFC_DMA_CTRL_ERR_FLAG BIT(1)
120 #define AR934X_NFC_DMA_CTRL_DMA_READY BIT(0)
122 #define AR934X_NFC_INT_DEV_RDY(_x) BIT(4 + (_x))
123 #define AR934X_NFC_INT_CMD_END BIT(1)
125 /* default timing values */
126 #define AR934X_NFC_TIME_SEQ_DEFAULT 0x7fff
127 #define AR934X_NFC_TIMINGS_ASYN_DEFAULT 0x22
128 #define AR934X_NFC_TIMINGS_SYN_DEFAULT 0xf
130 #define AR934X_NFC_ID_BUF_SIZE 8
131 #define AR934X_NFC_DEV_READY_TIMEOUT 25 /* msecs */
132 #define AR934X_NFC_DMA_READY_TIMEOUT 25 /* msecs */
133 #define AR934X_NFC_DONE_TIMEOUT 1000
135 #define AR934X_NFC_USE_IRQ true
136 #define AR934X_NFC_IRQ_MASK AR934X_NFC_INT_DEV_RDY(0)
138 #define AR934X_NFC_GENSEQ_SMALL_PAGE_READ 0x30043
140 #undef AR934X_NFC_DEBUG_DATA
141 #undef AR934X_NFC_DEBUG
145 static inline __attribute__ ((format (printf, 2, 3)))
146 void _nfc_dbg(struct ar934x_nfc *nfc, const char *fmt, ...)
150 #ifdef AR934X_NFC_DEBUG
151 #define nfc_dbg(_nfc, fmt, ...) \
152 dev_info((_nfc)->parent, fmt, ##__VA_ARGS__)
154 #define nfc_dbg(_nfc, fmt, ...) \
155 _nfc_dbg((_nfc), fmt, ##__VA_ARGS__)
156 #endif /* AR934X_NFC_DEBUG */
158 #ifdef AR934X_NFC_DEBUG_DATA
160 nfc_debug_data(const char *label, void *data, int len)
162 print_hex_dump(KERN_WARNING, label, DUMP_PREFIX_OFFSET, 16, 1,
167 nfc_debug_data(const char *label, void *data, int len) {}
168 #endif /* AR934X_NFC_DEBUG_DATA */
172 struct nand_chip nand_chip;
173 struct device *parent;
175 void (*select_chip)(int chip_no);
177 wait_queue_head_t irq_waitq;
179 bool spurious_irq_expected;
184 unsigned int addr_count0;
185 unsigned int addr_count1;
189 unsigned int buf_size;
192 int erase1_page_addr;
194 int rndout_page_addr;
202 static void ar934x_nfc_restart(struct ar934x_nfc *nfc);
205 ar934x_nfc_wr(struct ar934x_nfc *nfc, unsigned reg, u32 val)
207 __raw_writel(val, nfc->base + reg);
211 ar934x_nfc_rr(struct ar934x_nfc *nfc, unsigned reg)
213 return __raw_readl(nfc->base + reg);
216 static inline struct ar934x_nfc_platform_data *
217 ar934x_nfc_get_platform_data(struct ar934x_nfc *nfc)
219 return nfc->parent->platform_data;
223 ar934x_nfc *mtd_to_ar934x_nfc(struct mtd_info *mtd)
225 return container_of(mtd, struct ar934x_nfc, mtd);
228 static inline bool ar934x_nfc_use_irq(struct ar934x_nfc *nfc)
230 return AR934X_NFC_USE_IRQ;
233 static inline void ar934x_nfc_write_cmd_reg(struct ar934x_nfc *nfc, u32 cmd_reg)
237 ar934x_nfc_wr(nfc, AR934X_NFC_REG_CMD, cmd_reg);
239 ar934x_nfc_rr(nfc, AR934X_NFC_REG_CMD);
243 __ar934x_nfc_dev_ready(struct ar934x_nfc *nfc)
247 status = ar934x_nfc_rr(nfc, AR934X_NFC_REG_STATUS);
248 return (status & 0xff) == 0xff;
252 __ar934x_nfc_is_dma_ready(struct ar934x_nfc *nfc)
256 status = ar934x_nfc_rr(nfc, AR934X_NFC_REG_DMA_CTRL);
257 return (status & AR934X_NFC_DMA_CTRL_DMA_READY) != 0;
261 ar934x_nfc_wait_dev_ready(struct ar934x_nfc *nfc)
263 unsigned long timeout;
265 timeout = jiffies + msecs_to_jiffies(AR934X_NFC_DEV_READY_TIMEOUT);
267 if (__ar934x_nfc_dev_ready(nfc))
269 } while time_before(jiffies, timeout);
271 nfc_dbg(nfc, "timeout waiting for device ready, status:%08x int:%08x\n",
272 ar934x_nfc_rr(nfc, AR934X_NFC_REG_STATUS),
273 ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_STATUS));
278 ar934x_nfc_wait_dma_ready(struct ar934x_nfc *nfc)
280 unsigned long timeout;
282 timeout = jiffies + msecs_to_jiffies(AR934X_NFC_DMA_READY_TIMEOUT);
284 if (__ar934x_nfc_is_dma_ready(nfc))
286 } while time_before(jiffies, timeout);
288 nfc_dbg(nfc, "timeout waiting for DMA ready, dma_ctrl:%08x\n",
289 ar934x_nfc_rr(nfc, AR934X_NFC_REG_DMA_CTRL));
294 ar934x_nfc_wait_irq(struct ar934x_nfc *nfc)
299 timeout = wait_event_timeout(nfc->irq_waitq,
300 (nfc->irq_status & AR934X_NFC_IRQ_MASK) != 0,
301 msecs_to_jiffies(AR934X_NFC_DEV_READY_TIMEOUT));
305 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_MASK, 0);
306 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
308 ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_STATUS);
311 "timeout waiting for interrupt, status:%08x\n",
321 ar934x_nfc_wait_done(struct ar934x_nfc *nfc)
325 if (ar934x_nfc_use_irq(nfc))
326 ret = ar934x_nfc_wait_irq(nfc);
328 ret = ar934x_nfc_wait_dev_ready(nfc);
333 return ar934x_nfc_wait_dma_ready(nfc);
337 ar934x_nfc_alloc_buf(struct ar934x_nfc *nfc, unsigned size)
339 nfc->buf = dma_alloc_coherent(nfc->parent, size,
340 &nfc->buf_dma, GFP_KERNEL);
341 if (nfc->buf == NULL) {
342 dev_err(nfc->parent, "no memory for DMA buffer\n");
346 nfc->buf_size = size;
347 nfc_dbg(nfc, "buf:%p size:%u\n", nfc->buf, nfc->buf_size);
353 ar934x_nfc_free_buf(struct ar934x_nfc *nfc)
355 dma_free_coherent(nfc->parent, nfc->buf_size, nfc->buf, nfc->buf_dma);
359 ar934x_nfc_get_addr(struct ar934x_nfc *nfc, int column, int page_addr,
360 u32 *addr0, u32 *addr1)
369 a0 = (page_addr & 0xffff) << 16;
370 a1 = (page_addr >> 16) & 0xf;
371 } else if (page_addr != -1) {
372 /* SEQIN, READ0, etc.. */
374 /* TODO: handle 16bit bus width */
375 if (nfc->small_page) {
377 a0 |= (page_addr & 0xff) << 8;
378 a0 |= ((page_addr >> 8) & 0xff) << 16;
379 a0 |= ((page_addr >> 16) & 0xff) << 24;
381 a0 = column & 0x0FFF;
382 a0 |= (page_addr & 0xffff) << 16;
384 if (nfc->addr_count0 > 4)
385 a1 = (page_addr >> 16) & 0xf;
394 ar934x_nfc_send_cmd(struct ar934x_nfc *nfc, unsigned command)
398 cmd_reg = AR934X_NFC_CMD_INPUT_SEL_SIU | AR934X_NFC_CMD_ADDR_SEL_0 |
399 AR934X_NFC_CMD_SEQ_1C;
400 cmd_reg |= (command & AR934X_NFC_CMD_CMD0_M) << AR934X_NFC_CMD_CMD0_S;
402 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
403 ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, nfc->ctrl_reg);
405 ar934x_nfc_write_cmd_reg(nfc, cmd_reg);
406 ar934x_nfc_wait_dev_ready(nfc);
410 ar934x_nfc_do_rw_command(struct ar934x_nfc *nfc, int column, int page_addr,
411 int len, u32 cmd_reg, u32 ctrl_reg, bool write)
421 if (WARN_ON(len > nfc->buf_size))
422 dev_err(nfc->parent, "len=%d > buf_size=%d", len, nfc->buf_size);
425 dma_ctrl = AR934X_NFC_DMA_CTRL_DMA_DIR_WRITE;
428 dma_ctrl = AR934X_NFC_DMA_CTRL_DMA_DIR_READ;
429 dir = DMA_FROM_DEVICE;
432 ar934x_nfc_get_addr(nfc, column, page_addr, &addr0, &addr1);
434 dma_ctrl |= AR934X_NFC_DMA_CTRL_DMA_START |
435 (AR934X_NFC_DMA_CTRL_DMA_BURST_3 <<
436 AR934X_NFC_DMA_CTRL_DMA_BURST_S);
438 cmd_reg |= AR934X_NFC_CMD_INPUT_SEL_DMA | AR934X_NFC_CMD_ADDR_SEL_0;
439 ctrl_reg |= AR934X_NFC_CTRL_INT_EN;
441 nfc_dbg(nfc, "%s a0:%08x a1:%08x len:%x cmd:%08x dma:%08x ctrl:%08x\n",
442 (write) ? "write" : "read",
443 addr0, addr1, len, cmd_reg, dma_ctrl, ctrl_reg);
446 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
447 ar934x_nfc_wr(nfc, AR934X_NFC_REG_ADDR0_0, addr0);
448 ar934x_nfc_wr(nfc, AR934X_NFC_REG_ADDR0_1, addr1);
449 ar934x_nfc_wr(nfc, AR934X_NFC_REG_DMA_ADDR, nfc->buf_dma);
450 ar934x_nfc_wr(nfc, AR934X_NFC_REG_DMA_COUNT, len);
451 ar934x_nfc_wr(nfc, AR934X_NFC_REG_DATA_SIZE, len);
452 ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, ctrl_reg);
453 ar934x_nfc_wr(nfc, AR934X_NFC_REG_DMA_CTRL, dma_ctrl);
455 if (ar934x_nfc_use_irq(nfc)) {
456 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_MASK, AR934X_NFC_IRQ_MASK);
458 ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_MASK);
461 ar934x_nfc_write_cmd_reg(nfc, cmd_reg);
462 err = ar934x_nfc_wait_done(nfc);
464 dev_dbg(nfc->parent, "%s operation stuck at page %d\n",
465 (write) ? "write" : "read", page_addr);
467 ar934x_nfc_restart(nfc);
471 dev_err(nfc->parent, "%s operation failed on page %d\n",
472 (write) ? "write" : "read", page_addr);
477 ar934x_nfc_send_readid(struct ar934x_nfc *nfc, unsigned command)
481 nfc_dbg(nfc, "readid, cmd:%02x\n", command);
483 cmd_reg = AR934X_NFC_CMD_SEQ_1C1AXR;
484 cmd_reg |= (command & AR934X_NFC_CMD_CMD0_M) << AR934X_NFC_CMD_CMD0_S;
486 ar934x_nfc_do_rw_command(nfc, -1, -1, AR934X_NFC_ID_BUF_SIZE, cmd_reg,
487 nfc->ctrl_reg, false);
489 nfc_debug_data("[id] ", nfc->buf, AR934X_NFC_ID_BUF_SIZE);
493 ar934x_nfc_send_read(struct ar934x_nfc *nfc, unsigned command, int column,
494 int page_addr, int len, bool oob)
498 nfc_dbg(nfc, "read, column=%d page=%d len=%d oob:%d\n",
499 column, page_addr, len, oob);
501 cmd_reg = (command & AR934X_NFC_CMD_CMD0_M) << AR934X_NFC_CMD_CMD0_S;
503 if (nfc->small_page) {
504 cmd_reg |= AR934X_NFC_CMD_SEQ_18;
506 cmd_reg |= NAND_CMD_READSTART << AR934X_NFC_CMD_CMD1_S;
507 cmd_reg |= AR934X_NFC_CMD_SEQ_1C5A1CXR;
510 ar934x_nfc_do_rw_command(nfc, column, page_addr, len,
511 cmd_reg, nfc->ctrl_reg, false);
513 nfc_debug_data("[data] ", nfc->buf, len);
517 ar934x_nfc_send_erase(struct ar934x_nfc *nfc, unsigned command, int column,
524 ar934x_nfc_get_addr(nfc, column, page_addr, &addr0, &addr1);
526 ctrl_reg = nfc->ctrl_reg;
527 if (nfc->small_page) {
528 /* override number of address cycles for the erase command */
529 ctrl_reg &= ~(AR934X_NFC_CTRL_ADDR_CYCLE0_M <<
530 AR934X_NFC_CTRL_ADDR_CYCLE0_S);
531 ctrl_reg &= ~(AR934X_NFC_CTRL_ADDR_CYCLE1_M <<
532 AR934X_NFC_CTRL_ADDR_CYCLE1_S);
533 ctrl_reg &= ~(AR934X_NFC_CTRL_SMALL_PAGE);
534 ctrl_reg |= (nfc->addr_count0 + 1) <<
535 AR934X_NFC_CTRL_ADDR_CYCLE0_S;
538 cmd_reg = NAND_CMD_ERASE1 << AR934X_NFC_CMD_CMD0_S;
539 cmd_reg |= command << AR934X_NFC_CMD_CMD1_S;
540 cmd_reg |= AR934X_NFC_CMD_SEQ_ERASE;
542 nfc_dbg(nfc, "erase page %d, a0:%08x a1:%08x cmd:%08x ctrl:%08x\n",
543 page_addr, addr0, addr1, cmd_reg, ctrl_reg);
545 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
546 ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, ctrl_reg);
547 ar934x_nfc_wr(nfc, AR934X_NFC_REG_ADDR0_0, addr0);
548 ar934x_nfc_wr(nfc, AR934X_NFC_REG_ADDR0_1, addr1);
550 ar934x_nfc_write_cmd_reg(nfc, cmd_reg);
551 ar934x_nfc_wait_dev_ready(nfc);
555 ar934x_nfc_send_write(struct ar934x_nfc *nfc, unsigned command, int column,
556 int page_addr, int len)
560 nfc_dbg(nfc, "write, column=%d page=%d len=%d\n",
561 column, page_addr, len);
563 nfc_debug_data("[data] ", nfc->buf, len);
565 cmd_reg = NAND_CMD_SEQIN << AR934X_NFC_CMD_CMD0_S;
566 cmd_reg |= command << AR934X_NFC_CMD_CMD1_S;
567 cmd_reg |= AR934X_NFC_CMD_SEQ_12;
569 ar934x_nfc_do_rw_command(nfc, column, page_addr, len,
570 cmd_reg, nfc->ctrl_reg, true);
574 ar934x_nfc_read_status(struct ar934x_nfc *nfc)
579 cmd_reg = NAND_CMD_STATUS << AR934X_NFC_CMD_CMD0_S;
580 cmd_reg |= AR934X_NFC_CMD_SEQ_S;
582 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
583 ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, nfc->ctrl_reg);
585 ar934x_nfc_write_cmd_reg(nfc, cmd_reg);
586 ar934x_nfc_wait_dev_ready(nfc);
588 status = ar934x_nfc_rr(nfc, AR934X_NFC_REG_READ_STATUS);
590 nfc_dbg(nfc, "read status, cmd:%08x status:%02x\n",
591 cmd_reg, (status & 0xff));
593 nfc->buf[0 ^ 3] = status;
597 ar934x_nfc_cmdfunc(struct mtd_info *mtd, unsigned int command, int column,
600 struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
602 if (command != NAND_CMD_PAGEPROG)
607 ar934x_nfc_send_cmd(nfc, command);
610 case NAND_CMD_READID:
611 ar934x_nfc_send_readid(nfc, command);
616 if (nfc->small_page) {
617 ar934x_nfc_send_read(nfc, command, column, page_addr,
618 mtd->writesize + mtd->oobsize,
621 ar934x_nfc_send_read(nfc, command, 0, page_addr,
622 mtd->writesize + mtd->oobsize,
624 nfc->buf_index = column;
625 nfc->rndout_page_addr = page_addr;
626 nfc->rndout_read_cmd = command;
630 case NAND_CMD_READOOB:
631 if (nfc->small_page) {
632 ar934x_nfc_send_read(nfc, NAND_CMD_READOOB,
637 ar934x_nfc_send_read(nfc, NAND_CMD_READ0,
639 mtd->writesize + mtd->oobsize,
641 nfc->buf_index = mtd->writesize;
645 case NAND_CMD_RNDOUT:
646 /* emulate subpage read */
647 ar934x_nfc_send_read(nfc, nfc->rndout_read_cmd, column,
648 nfc->rndout_page_addr,
649 mtd->writesize, false);
652 case NAND_CMD_ERASE1:
653 nfc->erase1_page_addr = page_addr;
656 case NAND_CMD_ERASE2:
657 ar934x_nfc_send_erase(nfc, command, -1, nfc->erase1_page_addr);
660 case NAND_CMD_STATUS:
661 ar934x_nfc_read_status(nfc);
665 if (nfc->small_page) {
666 /* output read command */
667 if (column >= mtd->writesize) {
668 column -= mtd->writesize;
669 nfc->seqin_read_cmd = NAND_CMD_READOOB;
670 } else if (column < 256) {
671 nfc->seqin_read_cmd = NAND_CMD_READ0;
674 nfc->seqin_read_cmd = NAND_CMD_READ1;
677 nfc->seqin_read_cmd = NAND_CMD_READ0;
679 nfc->seqin_column = column;
680 nfc->seqin_page_addr = page_addr;
683 case NAND_CMD_PAGEPROG:
685 ar934x_nfc_send_cmd(nfc, nfc->seqin_read_cmd);
687 ar934x_nfc_send_write(nfc, command, nfc->seqin_column,
688 nfc->seqin_page_addr,
694 "unsupported command: %x, column:%d page_addr=%d\n",
695 command, column, page_addr);
701 ar934x_nfc_dev_ready(struct mtd_info *mtd)
703 struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
705 return __ar934x_nfc_dev_ready(nfc);
709 ar934x_nfc_select_chip(struct mtd_info *mtd, int chip_no)
711 struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
713 if (nfc->select_chip)
714 nfc->select_chip(chip_no);
718 ar934x_nfc_read_byte(struct mtd_info *mtd)
720 struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
721 unsigned int buf_index;
724 WARN_ON(nfc->buf_index >= nfc->buf_size);
726 buf_index = nfc->buf_index ^ 3;
727 data = nfc->buf[buf_index];
734 ar934x_nfc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
736 struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
739 WARN_ON(nfc->buf_index + len > nfc->buf_size);
741 for (i = 0; i < len; i++) {
742 nfc->buf[nfc->buf_index ^ 3] = buf[i];
748 ar934x_nfc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
750 struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
754 WARN_ON(nfc->buf_index + len > nfc->buf_size);
756 buf_index = nfc->buf_index;
758 for (i = 0; i < len; i++) {
759 buf[i] = nfc->buf[buf_index ^ 3];
763 nfc->buf_index = buf_index;
767 ar934x_nfc_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
771 for (i = 0; i < len; i++)
772 if (buf[i] != ar934x_nfc_read_byte(mtd))
779 ar934x_nfc_hw_init(struct ar934x_nfc *nfc)
781 struct ar934x_nfc_platform_data *pdata;
783 pdata = ar934x_nfc_get_platform_data(nfc);
784 if (pdata->hw_reset) {
785 pdata->hw_reset(true);
786 pdata->hw_reset(false);
791 * TODO: make it configurable via platform data
793 ar934x_nfc_wr(nfc, AR934X_NFC_REG_TIME_SEQ,
794 AR934X_NFC_TIME_SEQ_DEFAULT);
795 ar934x_nfc_wr(nfc, AR934X_NFC_REG_TIMINGS_ASYN,
796 AR934X_NFC_TIMINGS_ASYN_DEFAULT);
797 ar934x_nfc_wr(nfc, AR934X_NFC_REG_TIMINGS_SYN,
798 AR934X_NFC_TIMINGS_SYN_DEFAULT);
800 /* disable WP on all chips, and select chip 0 */
801 ar934x_nfc_wr(nfc, AR934X_NFC_REG_MEM_CTRL, 0xff00);
803 ar934x_nfc_wr(nfc, AR934X_NFC_REG_DMA_ADDR_OFFS, 0);
805 /* initialize Control register */
806 nfc->ctrl_reg = AR934X_NFC_CTRL_CUSTOM_SIZE_EN;
807 ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, nfc->ctrl_reg);
809 if (nfc->small_page) {
810 /* Setup generic sequence register for small page reads. */
811 ar934x_nfc_wr(nfc, AR934X_NFC_REG_GEN_SEQ_CTRL,
812 AR934X_NFC_GENSEQ_SMALL_PAGE_READ);
817 ar934x_nfc_restart(struct ar934x_nfc *nfc)
821 if (nfc->select_chip)
822 nfc->select_chip(-1);
824 ctrl_reg = nfc->ctrl_reg;
825 ar934x_nfc_hw_init(nfc);
826 nfc->ctrl_reg = ctrl_reg;
828 if (nfc->select_chip)
831 ar934x_nfc_send_cmd(nfc, NAND_CMD_RESET);
835 ar934x_nfc_irq_handler(int irq, void *data)
837 struct ar934x_nfc *nfc = data;
840 status = ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_STATUS);
842 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
844 ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_STATUS);
846 status &= ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_MASK);
848 nfc_dbg(nfc, "got IRQ, status:%08x\n", status);
850 nfc->irq_status = status;
851 nfc->spurious_irq_expected = true;
852 wake_up(&nfc->irq_waitq);
854 if (nfc->spurious_irq_expected) {
855 nfc->spurious_irq_expected = false;
857 dev_warn(nfc->parent, "spurious interrupt\n");
865 ar934x_nfc_init_tail(struct mtd_info *mtd)
867 struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
868 struct nand_chip *chip = &nfc->nand_chip;
873 switch (mtd->oobsize) {
877 ar934x_nfc_wr(nfc, AR934X_NFC_REG_SPARE_SIZE, mtd->oobsize);
881 dev_err(nfc->parent, "unsupported OOB size: %d bytes\n",
886 ctrl = AR934X_NFC_CTRL_CUSTOM_SIZE_EN;
888 switch (mtd->erasesize / mtd->writesize) {
890 t = AR934X_NFC_CTRL_BLOCK_SIZE_32;
894 t = AR934X_NFC_CTRL_BLOCK_SIZE_64;
898 t = AR934X_NFC_CTRL_BLOCK_SIZE_128;
902 t = AR934X_NFC_CTRL_BLOCK_SIZE_256;
906 dev_err(nfc->parent, "unsupported block size: %u\n",
907 mtd->erasesize / mtd->writesize);
911 ctrl |= t << AR934X_NFC_CTRL_BLOCK_SIZE_S;
913 switch (mtd->writesize) {
916 t = AR934X_NFC_CTRL_PAGE_SIZE_256;
921 t = AR934X_NFC_CTRL_PAGE_SIZE_512;
925 t = AR934X_NFC_CTRL_PAGE_SIZE_1024;
929 t = AR934X_NFC_CTRL_PAGE_SIZE_2048;
933 t = AR934X_NFC_CTRL_PAGE_SIZE_4096;
937 t = AR934X_NFC_CTRL_PAGE_SIZE_8192;
941 t = AR934X_NFC_CTRL_PAGE_SIZE_16384;
945 dev_err(nfc->parent, "unsupported write size: %d bytes\n",
950 ctrl |= t << AR934X_NFC_CTRL_PAGE_SIZE_S;
952 if (nfc->small_page) {
953 ctrl |= AR934X_NFC_CTRL_SMALL_PAGE;
955 if (chip->chipsize > (32 << 20)) {
956 nfc->addr_count0 = 4;
957 nfc->addr_count1 = 3;
958 } else if (chip->chipsize > (2 << 16)) {
959 nfc->addr_count0 = 3;
960 nfc->addr_count1 = 2;
962 nfc->addr_count0 = 2;
963 nfc->addr_count1 = 1;
966 if (chip->chipsize > (128 << 20)) {
967 nfc->addr_count0 = 5;
968 nfc->addr_count1 = 3;
969 } else if (chip->chipsize > (8 << 16)) {
970 nfc->addr_count0 = 4;
971 nfc->addr_count1 = 2;
973 nfc->addr_count0 = 3;
974 nfc->addr_count1 = 1;
978 ctrl |= nfc->addr_count0 << AR934X_NFC_CTRL_ADDR_CYCLE0_S;
979 ctrl |= nfc->addr_count1 << AR934X_NFC_CTRL_ADDR_CYCLE1_S;
981 nfc->ctrl_reg = ctrl;
982 ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, nfc->ctrl_reg);
984 ar934x_nfc_free_buf(nfc);
985 err = ar934x_nfc_alloc_buf(nfc, mtd->writesize + mtd->oobsize);
991 ar934x_nfc_probe(struct platform_device *pdev)
993 static const char *part_probes[] = { "cmdlinepart", NULL, };
994 struct ar934x_nfc_platform_data *pdata;
995 struct ar934x_nfc *nfc;
996 struct resource *res;
997 struct mtd_info *mtd;
998 struct nand_chip *nand;
999 struct mtd_part_parser_data ppdata;
1002 pdata = pdev->dev.platform_data;
1003 if (pdata == NULL) {
1004 dev_err(&pdev->dev, "no platform data defined\n");
1008 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1010 dev_err(&pdev->dev, "failed to get I/O memory\n");
1014 nfc = kzalloc(sizeof(struct ar934x_nfc), GFP_KERNEL);
1016 dev_err(&pdev->dev, "failed to allocate driver data\n");
1020 nfc->base = ioremap(res->start, resource_size(res));
1021 if (nfc->base == NULL) {
1022 dev_err(&pdev->dev, "failed to remap I/O memory\n");
1027 nfc->irq = platform_get_irq(pdev, 0);
1029 dev_err(&pdev->dev, "no IRQ resource specified\n");
1034 init_waitqueue_head(&nfc->irq_waitq);
1035 ret = request_irq(nfc->irq, ar934x_nfc_irq_handler, IRQF_DISABLED,
1036 dev_name(&pdev->dev), nfc);
1038 dev_err(&pdev->dev, "requast_irq failed, err:%d\n", ret);
1042 nfc->parent = &pdev->dev;
1043 nfc->select_chip = pdata->select_chip;
1045 nand = &nfc->nand_chip;
1049 mtd->owner = THIS_MODULE;
1051 mtd->name = pdata->name;
1053 mtd->name = dev_name(&pdev->dev);
1055 nand->options = NAND_NO_AUTOINCR;
1056 nand->chip_delay = 25;
1057 nand->ecc.mode = NAND_ECC_SOFT;
1059 nand->dev_ready = ar934x_nfc_dev_ready;
1060 nand->cmdfunc = ar934x_nfc_cmdfunc;
1061 nand->read_byte = ar934x_nfc_read_byte;
1062 nand->write_buf = ar934x_nfc_write_buf;
1063 nand->read_buf = ar934x_nfc_read_buf;
1064 nand->verify_buf = ar934x_nfc_verify_buf;
1065 nand->select_chip = ar934x_nfc_select_chip;
1067 ret = ar934x_nfc_alloc_buf(nfc, AR934X_NFC_ID_BUF_SIZE);
1071 platform_set_drvdata(pdev, nfc);
1073 ar934x_nfc_hw_init(nfc);
1075 ret = nand_scan_ident(mtd, 1, NULL);
1077 dev_err(&pdev->dev, "nand_scan_ident failed, err:%d\n", ret);
1081 ret = ar934x_nfc_init_tail(mtd);
1083 dev_err(&pdev->dev, "init tail failed, err:%d\n", ret);
1087 if (pdata->scan_fixup) {
1088 ret = pdata->scan_fixup(mtd);
1093 ret = nand_scan_tail(mtd);
1095 dev_err(&pdev->dev, "scan tail failed, err:%d\n", ret);
1099 memset(&ppdata, '\0', sizeof(ppdata));
1100 ret = mtd_device_parse_register(mtd, part_probes, &ppdata,
1101 pdata->parts, pdata->nr_parts);
1103 dev_err(&pdev->dev, "unable to register mtd, err:%d\n", ret);
1110 ar934x_nfc_free_buf(nfc);
1112 free_irq(nfc->irq, nfc);
1117 platform_set_drvdata(pdev, NULL);
1121 static int __devexit
1122 ar934x_nfc_remove(struct platform_device *pdev)
1124 struct ar934x_nfc *nfc;
1126 nfc = platform_get_drvdata(pdev);
1128 nand_release(&nfc->mtd);
1129 ar934x_nfc_free_buf(nfc);
1130 free_irq(nfc->irq, nfc);
1138 static struct platform_driver ar934x_nfc_driver = {
1139 .probe = ar934x_nfc_probe,
1140 .remove = __devexit_p(ar934x_nfc_remove),
1142 .name = AR934X_NFC_DRIVER_NAME,
1143 .owner = THIS_MODULE,
1147 module_platform_driver(ar934x_nfc_driver);
1149 MODULE_LICENSE("GPL v2");
1150 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1151 MODULE_DESCRIPTION("Atheros AR934x NAND Flash Controller driver");
1152 MODULE_ALIAS("platform:" AR934X_NFC_DRIVER_NAME);