2 * Atheros AR724x PCI host controller driver
4 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
6 * Parts of this file are based on Atheros' 2.6.15 BSP
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published
10 * by the Free Software Foundation.
13 #include <linux/resource.h>
14 #include <linux/types.h>
15 #include <linux/delay.h>
16 #include <linux/bitops.h>
17 #include <linux/pci.h>
18 #include <linux/pci_regs.h>
19 #include <linux/interrupt.h>
21 #include <asm/mach-ar71xx/ar71xx.h>
22 #include <asm/mach-ar71xx/pci.h>
26 #define DBG(fmt, args...) printk(KERN_INFO fmt, ## args)
28 #define DBG(fmt, args...)
31 static void __iomem *ar724x_pci_localcfg_base;
32 static void __iomem *ar724x_pci_devcfg_base;
33 static void __iomem *ar724x_pci_ctrl_base;
34 static int ar724x_pci_fixup_enable;
36 static DEFINE_SPINLOCK(ar724x_pci_lock);
38 static inline void ar724x_pci_wr(unsigned reg, u32 val)
40 __raw_writel(val, ar724x_pci_ctrl_base + reg);
41 (void) __raw_readl(ar724x_pci_ctrl_base + reg);
44 static inline void ar724x_pci_wr_nf(unsigned reg, u32 val)
46 __raw_writel(val, ar724x_pci_ctrl_base + reg);
49 static inline u32 ar724x_pci_rr(unsigned reg)
51 return __raw_readl(ar724x_pci_ctrl_base + reg);
54 static void ar724x_pci_read(void __iomem *base, int where, int size, u32 *value)
59 spin_lock_irqsave(&ar724x_pci_lock, flags);
60 data = __raw_readl(base + (where & ~3));
78 spin_unlock_irqrestore(&ar724x_pci_lock, flags);
81 static void ar724x_pci_write(void __iomem *base, int where, int size, u32 value)
87 spin_lock_irqsave(&ar724x_pci_lock, flags);
88 data = __raw_readl(base + (where & ~3));
92 s = ((where & 3) << 3);
94 data |= ((value & 0xFF) << s);
97 s = ((where & 2) << 3);
98 data &= ~(0xFFFF << s);
99 data |= ((value & 0xFFFF) << s);
106 __raw_writel(data, base + (where & ~3));
108 (void)__raw_readl(base + (where & ~3));
109 spin_unlock_irqrestore(&ar724x_pci_lock, flags);
112 static int ar724x_pci_read_config(struct pci_bus *bus, unsigned int devfn,
113 int where, int size, u32 *value)
116 if (bus->number != 0 || devfn != 0)
117 return PCIBIOS_DEVICE_NOT_FOUND;
119 ar724x_pci_read(ar724x_pci_devcfg_base, where, size, value);
121 DBG("PCI: read config: %02x:%02x.%01x/%02x:%01d, value=%08x\n",
122 bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
123 where, size, *value);
126 * WAR for BAR issue - We are unable to access the PCI device space
127 * if we set the BAR with proper base address
129 if ((where == 0x10) && (size == 4))
130 ar724x_pci_write(ar724x_pci_devcfg_base, where, size, 0xffff);
132 return PCIBIOS_SUCCESSFUL;
135 static int ar724x_pci_write_config(struct pci_bus *bus, unsigned int devfn,
136 int where, int size, u32 value)
138 if (bus->number != 0 || devfn != 0)
139 return PCIBIOS_DEVICE_NOT_FOUND;
141 DBG("PCI: write config: %02x:%02x.%01x/%02x:%01d, value=%08x\n",
142 bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
145 ar724x_pci_write(ar724x_pci_devcfg_base, where, size, value);
147 return PCIBIOS_SUCCESSFUL;
150 static void ar724x_pci_fixup(struct pci_dev *dev)
154 if (!ar724x_pci_fixup_enable)
157 if (dev->bus->number != 0 || dev->devfn != 0)
160 /* setup COMMAND register */
161 pci_read_config_word(dev, PCI_COMMAND, &cmd);
162 cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
163 PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY | PCI_COMMAND_SERR |
164 PCI_COMMAND_FAST_BACK;
166 pci_write_config_word(dev, PCI_COMMAND, cmd);
168 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ar724x_pci_fixup);
170 int __init ar724x_pcibios_map_irq(const struct pci_dev *dev, uint8_t slot,
176 for (i = 0; i < ar71xx_pci_nr_irqs; i++) {
177 struct ar71xx_pci_irq *entry;
178 entry = &ar71xx_pci_irq_map[i];
180 if (entry->slot == slot && entry->pin == pin) {
187 printk(KERN_ALERT "PCI: no irq found for pin%u@%s\n",
188 pin, pci_name((struct pci_dev *)dev));
190 printk(KERN_INFO "PCI: mapping irq %d to pin%u@%s\n",
191 irq, pin, pci_name((struct pci_dev *)dev));
196 static struct pci_ops ar724x_pci_ops = {
197 .read = ar724x_pci_read_config,
198 .write = ar724x_pci_write_config,
201 static struct resource ar724x_pci_io_resource = {
202 .name = "PCI IO space",
205 .flags = IORESOURCE_IO,
208 static struct resource ar724x_pci_mem_resource = {
209 .name = "PCI memory space",
210 .start = AR71XX_PCI_MEM_BASE,
211 .end = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1,
212 .flags = IORESOURCE_MEM
215 static struct pci_controller ar724x_pci_controller = {
216 .pci_ops = &ar724x_pci_ops,
217 .mem_resource = &ar724x_pci_mem_resource,
218 .io_resource = &ar724x_pci_io_resource,
221 static void __init ar724x_pci_reset(void)
223 ar71xx_device_stop(AR724X_RESET_PCIE);
224 ar71xx_device_stop(AR724X_RESET_PCIE_PHY);
225 ar71xx_device_stop(AR724X_RESET_PCIE_PHY_SERIAL);
228 ar71xx_device_start(AR724X_RESET_PCIE_PHY_SERIAL);
230 ar71xx_device_start(AR724X_RESET_PCIE_PHY);
231 ar71xx_device_start(AR724X_RESET_PCIE);
234 static int __init ar724x_pci_setup(void)
238 /* setup COMMAND register */
239 t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE |
240 PCI_COMMAND_PARITY|PCI_COMMAND_SERR|PCI_COMMAND_FAST_BACK;
242 ar724x_pci_write(ar724x_pci_localcfg_base, PCI_COMMAND, 4, t);
243 ar724x_pci_write(ar724x_pci_localcfg_base, 0x20, 4, 0x1ff01000);
244 ar724x_pci_write(ar724x_pci_localcfg_base, 0x24, 4, 0x1ff01000);
246 t = ar724x_pci_rr(AR724X_PCI_REG_RESET);
249 ar724x_pci_wr_nf(AR724X_PCI_REG_RESET, 0);
251 ar724x_pci_wr_nf(AR724X_PCI_REG_RESET, 4);
255 ar724x_pci_wr(AR724X_PCI_REG_APP, AR724X_PCI_APP_LTSSM_ENABLE);
258 t = ar724x_pci_rr(AR724X_PCI_REG_APP);
259 if ((t & AR724X_PCI_APP_LTSSM_ENABLE) == 0x0) {
260 printk(KERN_WARNING "PCI: no PCIe module found\n");
267 static void ar724x_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
271 pending = ar724x_pci_rr(AR724X_PCI_REG_INT_STATUS) &
272 ar724x_pci_rr(AR724X_PCI_REG_INT_MASK);
274 if (pending & AR724X_PCI_INT_DEV0)
275 generic_handle_irq(AR71XX_PCI_IRQ_DEV0);
278 spurious_interrupt();
281 static void ar724x_pci_irq_unmask(unsigned int irq)
284 case AR71XX_PCI_IRQ_DEV0:
285 irq -= AR71XX_PCI_IRQ_BASE;
286 ar724x_pci_wr(AR724X_PCI_REG_INT_MASK,
287 ar724x_pci_rr(AR724X_PCI_REG_INT_MASK) |
288 AR724X_PCI_INT_DEV0);
290 ar724x_pci_rr(AR724X_PCI_REG_INT_MASK);
294 static void ar724x_pci_irq_mask(unsigned int irq)
297 case AR71XX_PCI_IRQ_DEV0:
298 irq -= AR71XX_PCI_IRQ_BASE;
299 ar724x_pci_wr(AR724X_PCI_REG_INT_MASK,
300 ar724x_pci_rr(AR724X_PCI_REG_INT_MASK) &
301 ~AR724X_PCI_INT_DEV0);
303 ar724x_pci_rr(AR724X_PCI_REG_INT_MASK);
305 ar724x_pci_wr(AR724X_PCI_REG_INT_STATUS,
306 ar724x_pci_rr(AR724X_PCI_REG_INT_STATUS) |
307 AR724X_PCI_INT_DEV0);
309 ar724x_pci_rr(AR724X_PCI_REG_INT_STATUS);
313 static struct irq_chip ar724x_pci_irq_chip = {
314 .name = "AR724X PCI ",
315 .mask = ar724x_pci_irq_mask,
316 .unmask = ar724x_pci_irq_unmask,
317 .mask_ack = ar724x_pci_irq_mask,
320 static void __init ar724x_pci_irq_init(void)
325 t = ar71xx_reset_rr(AR724X_RESET_REG_RESET_MODULE);
326 if (t & (AR724X_RESET_PCIE | AR724X_RESET_PCIE_PHY |
327 AR724X_RESET_PCIE_PHY_SERIAL)) {
331 ar724x_pci_wr(AR724X_PCI_REG_INT_MASK, 0);
332 ar724x_pci_wr(AR724X_PCI_REG_INT_STATUS, 0);
334 for (i = AR71XX_PCI_IRQ_BASE;
335 i < AR71XX_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) {
336 irq_desc[i].status = IRQ_DISABLED;
337 set_irq_chip_and_handler(i, &ar724x_pci_irq_chip,
341 set_irq_chained_handler(AR71XX_CPU_IRQ_IP2, ar724x_pci_irq_handler);
344 int __init ar724x_pcibios_init(void)
348 ar724x_pci_localcfg_base = ioremap_nocache(AR724X_PCI_CRP_BASE,
349 AR724X_PCI_CRP_SIZE);
350 if (ar724x_pci_localcfg_base == NULL)
353 ar724x_pci_devcfg_base = ioremap_nocache(AR724X_PCI_CFG_BASE,
354 AR724X_PCI_CFG_SIZE);
355 if (ar724x_pci_devcfg_base == NULL)
356 goto err_unmap_localcfg;
358 ar724x_pci_ctrl_base = ioremap_nocache(AR724X_PCI_CTRL_BASE,
359 AR724X_PCI_CTRL_SIZE);
360 if (ar724x_pci_ctrl_base == NULL)
361 goto err_unmap_devcfg;
364 ret = ar724x_pci_setup();
368 ar724x_pci_fixup_enable = 1;
369 ar724x_pci_irq_init();
370 register_pci_controller(&ar724x_pci_controller);
375 iounmap(ar724x_pci_ctrl_base);
377 iounmap(ar724x_pci_devcfg_base);
379 iounmap(ar724x_pci_localcfg_base);