target/linux/ar71xx/files/arch/mips/ath79/mach-wrt400n.c

   1 /*
   2  *  Linksys WRT400N board support
   3  *
   4  *  Copyright (C) 2009-2012 Gabor Juhos <juhosg@openwrt.org>
   5  *  Copyright (C) 2009 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  *  This program is free software; you can redistribute it and/or modify it
   8  *  under the terms of the GNU General Public License version 2 as published
   9  *  by the Free Software Foundation.
  10  */
  11
  12 #include <linux/mtd/mtd.h>
  13 #include <linux/mtd/partitions.h>
  14
  15 #include <asm/mach-ath79/ath79.h>
  16
  17 #include "dev-ap9x-pci.h"
  18 #include "dev-eth.h"
  19 #include "dev-gpio-buttons.h"
  20 #include "dev-leds-gpio.h"
  21 #include "dev-m25p80.h"
  22 #include "machtypes.h"
  23
  24 #define WRT400N_GPIO_LED_POWER          1
  25 #define WRT400N_GPIO_LED_WPS_BLUE       4
  26 #define WRT400N_GPIO_LED_WPS_AMBER      5
  27 #define WRT400N_GPIO_LED_WLAN           6
  28
  29 #define WRT400N_GPIO_BTN_RESET          8
  30 #define WRT400N_GPIO_BTN_WLSEC          3
  31
  32 #define WRT400N_KEYS_POLL_INTERVAL      20      /* msecs */
  33 #define WRT400N_KEYS_DEBOUNE_INTERVAL   (3 * WRT400N_KEYS_POLL_INTERVAL)
  34
  35 #define WRT400N_MAC_ADDR_OFFSET         0x120c
  36 #define WRT400N_CALDATA0_OFFSET         0x1000
  37 #define WRT400N_CALDATA1_OFFSET         0x5000
  38
  39 static struct mtd_partition wrt400n_partitions[] = {
  40         {
  41                 .name           = "uboot",
  42                 .offset         = 0,
  43                 .size           = 0x030000,
  44                 .mask_flags     = MTD_WRITEABLE,
  45         }, {
  46                 .name           = "env",
  47                 .offset         = 0x030000,
  48                 .size           = 0x010000,
  49                 .mask_flags     = MTD_WRITEABLE,
  50         }, {
  51                 .name           = "firmware",
  52                 .offset         = 0x040000,
  53                 .size           = 0x770000,
  54         }, {
  55                 .name           = "nvram",
  56                 .offset         = 0x7b0000,
  57                 .size           = 0x010000,
  58                 .mask_flags     = MTD_WRITEABLE,
  59         }, {
  60                 .name           = "factory",
  61                 .offset         = 0x7c0000,
  62                 .size           = 0x010000,
  63                 .mask_flags     = MTD_WRITEABLE,
  64         }, {
  65                 .name           = "language",
  66                 .offset         = 0x7d0000,
  67                 .size           = 0x020000,
  68                 .mask_flags     = MTD_WRITEABLE,
  69         }, {
  70                 .name           = "caldata",
  71                 .offset         = 0x7f0000,
  72                 .size           = 0x010000,
  73                 .mask_flags     = MTD_WRITEABLE,
  74         }
  75 };
  76
  77 static struct flash_platform_data wrt400n_flash_data = {
  78         .parts          = wrt400n_partitions,
  79         .nr_parts       = ARRAY_SIZE(wrt400n_partitions),
  80 };
  81
  82 static struct gpio_led wrt400n_leds_gpio[] __initdata = {
  83         {
  84                 .name           = "wrt400n:blue:wps",
  85                 .gpio           = WRT400N_GPIO_LED_WPS_BLUE,
  86                 .active_low     = 1,
  87         }, {
  88                 .name           = "wrt400n:amber:wps",
  89                 .gpio           = WRT400N_GPIO_LED_WPS_AMBER,
  90                 .active_low     = 1,
  91         }, {
  92                 .name           = "wrt400n:blue:wlan",
  93                 .gpio           = WRT400N_GPIO_LED_WLAN,
  94                 .active_low     = 1,
  95         }, {
  96                 .name           = "wrt400n:blue:power",
  97                 .gpio           = WRT400N_GPIO_LED_POWER,
  98                 .active_low     = 0,
  99                 .default_trigger = "default-on",
 100         }
 101 };
 102
 103 static struct gpio_keys_button wrt400n_gpio_keys[] __initdata = {
 104         {
 105                 .desc           = "reset",
 106                 .type           = EV_KEY,
 107                 .code           = KEY_RESTART,
 108                 .debounce_interval = WRT400N_KEYS_DEBOUNE_INTERVAL,
 109                 .gpio           = WRT400N_GPIO_BTN_RESET,
 110                 .active_low     = 1,
 111         }, {
 112                 .desc           = "wlsec",
 113                 .type           = EV_KEY,
 114                 .code           = KEY_WPS_BUTTON,
 115                 .debounce_interval = WRT400N_KEYS_DEBOUNE_INTERVAL,
 116                 .gpio           = WRT400N_GPIO_BTN_WLSEC,
 117                 .active_low     = 1,
 118         }
 119 };
 120
 121 static void __init wrt400n_setup(void)
 122 {
 123         u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
 124         u8 *mac = art + WRT400N_MAC_ADDR_OFFSET;
 125
 126         ath79_register_mdio(0, 0x0);
 127
 128         ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1);
 129         ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
 130         ath79_eth0_data.speed = SPEED_100;
 131         ath79_eth0_data.duplex = DUPLEX_FULL;
 132
 133         ath79_init_mac(ath79_eth1_data.mac_addr, mac, 2);
 134         ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
 135         ath79_eth1_data.phy_mask = 0x10;
 136
 137         ath79_register_eth(0);
 138         ath79_register_eth(1);
 139
 140         ath79_register_m25p80(&wrt400n_flash_data);
 141
 142         ath79_register_leds_gpio(-1, ARRAY_SIZE(wrt400n_leds_gpio),
 143                                  wrt400n_leds_gpio);
 144
 145         ath79_register_gpio_keys_polled(-1, WRT400N_KEYS_POLL_INTERVAL,
 146                                         ARRAY_SIZE(wrt400n_gpio_keys),
 147                                         wrt400n_gpio_keys);
 148
 149         ap94_pci_init(art + WRT400N_CALDATA0_OFFSET, NULL,
 150                       art + WRT400N_CALDATA1_OFFSET, NULL);
 151 }
 152
 153 MIPS_MACHINE(ATH79_MACH_WRT400N, "WRT400N", "Linksys WRT400N", wrt400n_setup);