2 * MikroTik RouterBOARD 4xx series support
4 * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
12 #include <linux/platform_device.h>
13 #include <linux/irq.h>
14 #include <linux/mdio-gpio.h>
15 #include <linux/mmc/host.h>
16 #include <linux/spi/spi.h>
17 #include <linux/spi/flash.h>
18 #include <linux/spi/mmc_spi.h>
19 #include <linux/mtd/mtd.h>
20 #include <linux/mtd/partitions.h>
22 #include <asm/mach-ath79/ar71xx_regs.h>
23 #include <asm/mach-ath79/ath79.h>
24 #include <asm/mach-ath79/rb4xx_cpld.h>
28 #include "dev-gpio-buttons.h"
29 #include "dev-leds-gpio.h"
31 #include "machtypes.h"
34 #define RB4XX_GPIO_USER_LED 4
35 #define RB4XX_GPIO_RESET_SWITCH 7
37 #define RB4XX_GPIO_CPLD_BASE 32
38 #define RB4XX_GPIO_CPLD_LED1 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED1)
39 #define RB4XX_GPIO_CPLD_LED2 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED2)
40 #define RB4XX_GPIO_CPLD_LED3 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED3)
41 #define RB4XX_GPIO_CPLD_LED4 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED4)
42 #define RB4XX_GPIO_CPLD_LED5 (RB4XX_GPIO_CPLD_BASE + CPLD_GPIO_nLED5)
44 #define RB4XX_KEYS_POLL_INTERVAL 20 /* msecs */
45 #define RB4XX_KEYS_DEBOUNCE_INTERVAL (3 * RB4XX_KEYS_POLL_INTERVAL)
47 static struct gpio_led rb4xx_leds_gpio[] __initdata = {
49 .name = "rb4xx:yellow:user",
50 .gpio = RB4XX_GPIO_USER_LED,
53 .name = "rb4xx:green:led1",
54 .gpio = RB4XX_GPIO_CPLD_LED1,
57 .name = "rb4xx:green:led2",
58 .gpio = RB4XX_GPIO_CPLD_LED2,
61 .name = "rb4xx:green:led3",
62 .gpio = RB4XX_GPIO_CPLD_LED3,
65 .name = "rb4xx:green:led4",
66 .gpio = RB4XX_GPIO_CPLD_LED4,
69 .name = "rb4xx:green:led5",
70 .gpio = RB4XX_GPIO_CPLD_LED5,
75 static struct gpio_keys_button rb4xx_gpio_keys[] __initdata = {
77 .desc = "reset_switch",
80 .debounce_interval = RB4XX_KEYS_DEBOUNCE_INTERVAL,
81 .gpio = RB4XX_GPIO_RESET_SWITCH,
86 static struct platform_device rb4xx_nand_device = {
91 static struct ath79_pci_irq rb4xx_pci_irqs[] __initdata = {
95 .irq = ATH79_PCI_IRQ(2),
99 .irq = ATH79_PCI_IRQ(0),
103 .irq = ATH79_PCI_IRQ(1),
107 .irq = ATH79_PCI_IRQ(1),
111 .irq = ATH79_PCI_IRQ(2),
115 static struct mtd_partition rb4xx_partitions[] = {
117 .name = "routerboot",
120 .mask_flags = MTD_WRITEABLE,
122 .name = "hard_config",
125 .mask_flags = MTD_WRITEABLE,
130 .mask_flags = MTD_WRITEABLE,
132 .name = "soft_config",
138 static struct flash_platform_data rb4xx_flash_data = {
140 .parts = rb4xx_partitions,
141 .nr_parts = ARRAY_SIZE(rb4xx_partitions),
144 static struct rb4xx_cpld_platform_data rb4xx_cpld_data = {
145 .gpio_base = RB4XX_GPIO_CPLD_BASE,
148 static struct mmc_spi_platform_data rb4xx_mmc_data = {
149 .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
152 static struct spi_board_info rb4xx_spi_info[] = {
156 .max_speed_hz = 25000000,
157 .modalias = "m25p80",
158 .platform_data = &rb4xx_flash_data,
162 .max_speed_hz = 25000000,
163 .modalias = "spi-rb4xx-cpld",
164 .platform_data = &rb4xx_cpld_data,
168 static struct spi_board_info rb4xx_microsd_info[] = {
172 .max_speed_hz = 25000000,
173 .modalias = "mmc_spi",
174 .platform_data = &rb4xx_mmc_data,
179 static struct resource rb4xx_spi_resources[] = {
181 .start = AR71XX_SPI_BASE,
182 .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1,
183 .flags = IORESOURCE_MEM,
187 static struct platform_device rb4xx_spi_device = {
190 .resource = rb4xx_spi_resources,
191 .num_resources = ARRAY_SIZE(rb4xx_spi_resources),
194 static void __init rb4xx_generic_setup(void)
196 ath79_gpio_function_enable(AR71XX_GPIO_FUNC_SPI_CS1_EN |
197 AR71XX_GPIO_FUNC_SPI_CS2_EN);
199 ath79_register_leds_gpio(-1, ARRAY_SIZE(rb4xx_leds_gpio),
202 ath79_register_gpio_keys_polled(-1, RB4XX_KEYS_POLL_INTERVAL,
203 ARRAY_SIZE(rb4xx_gpio_keys),
206 spi_register_board_info(rb4xx_spi_info, ARRAY_SIZE(rb4xx_spi_info));
207 platform_device_register(&rb4xx_spi_device);
208 platform_device_register(&rb4xx_nand_device);
211 static void __init rb411_setup(void)
213 rb4xx_generic_setup();
214 spi_register_board_info(rb4xx_microsd_info,
215 ARRAY_SIZE(rb4xx_microsd_info));
217 ath79_register_mdio(0, 0xfffffffc);
219 ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
220 ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
221 ath79_eth0_data.phy_mask = 0x00000003;
223 ath79_register_eth(0);
225 ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs);
226 ath79_register_pci();
229 MIPS_MACHINE(ATH79_MACH_RB_411, "411", "MikroTik RouterBOARD 411/A/AH",
232 static void __init rb411u_setup(void)
235 ath79_register_usb();
238 MIPS_MACHINE(ATH79_MACH_RB_411U, "411U", "MikroTik RouterBOARD 411U",
241 #define RB433_LAN_PHYMASK BIT(0)
242 #define RB433_WAN_PHYMASK BIT(4)
243 #define RB433_MDIO_PHYMASK (RB433_LAN_PHYMASK | RB433_WAN_PHYMASK)
245 static void __init rb433_setup(void)
247 rb4xx_generic_setup();
248 spi_register_board_info(rb4xx_microsd_info,
249 ARRAY_SIZE(rb4xx_microsd_info));
251 ath79_register_mdio(0, ~RB433_MDIO_PHYMASK);
253 ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 1);
254 ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
255 ath79_eth0_data.phy_mask = RB433_LAN_PHYMASK;
257 ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 0);
258 ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
259 ath79_eth1_data.phy_mask = RB433_WAN_PHYMASK;
261 ath79_register_eth(1);
262 ath79_register_eth(0);
264 ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs);
265 ath79_register_pci();
268 MIPS_MACHINE(ATH79_MACH_RB_433, "433", "MikroTik RouterBOARD 433/AH",
271 static void __init rb433u_setup(void)
274 ath79_register_usb();
277 MIPS_MACHINE(ATH79_MACH_RB_433U, "433U", "MikroTik RouterBOARD 433UAH",
280 #define RB450_LAN_PHYMASK BIT(0)
281 #define RB450_WAN_PHYMASK BIT(4)
282 #define RB450_MDIO_PHYMASK (RB450_LAN_PHYMASK | RB450_WAN_PHYMASK)
284 static void __init rb450_generic_setup(int gige)
286 rb4xx_generic_setup();
287 ath79_register_mdio(0, ~RB450_MDIO_PHYMASK);
289 ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 1);
290 ath79_eth0_data.phy_if_mode = (gige) ?
291 PHY_INTERFACE_MODE_RGMII : PHY_INTERFACE_MODE_MII;
292 ath79_eth0_data.phy_mask = RB450_LAN_PHYMASK;
294 ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 0);
295 ath79_eth1_data.phy_if_mode = (gige) ?
296 PHY_INTERFACE_MODE_RGMII : PHY_INTERFACE_MODE_RMII;
297 ath79_eth1_data.phy_mask = RB450_WAN_PHYMASK;
299 ath79_register_eth(1);
300 ath79_register_eth(0);
303 static void __init rb450_setup(void)
305 rb450_generic_setup(0);
308 MIPS_MACHINE(ATH79_MACH_RB_450, "450", "MikroTik RouterBOARD 450",
311 static void __init rb450g_setup(void)
313 rb450_generic_setup(1);
314 spi_register_board_info(rb4xx_microsd_info,
315 ARRAY_SIZE(rb4xx_microsd_info));
318 MIPS_MACHINE(ATH79_MACH_RB_450G, "450G", "MikroTik RouterBOARD 450G",
321 static void __init rb493_setup(void)
323 rb4xx_generic_setup();
325 ath79_register_mdio(0, 0x3fffff00);
327 ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
328 ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
329 ath79_eth0_data.speed = SPEED_100;
330 ath79_eth0_data.duplex = DUPLEX_FULL;
332 ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1);
333 ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
334 ath79_eth1_data.phy_mask = 0x00000001;
336 ath79_register_eth(0);
337 ath79_register_eth(1);
339 ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs);
340 ath79_register_pci();
343 MIPS_MACHINE(ATH79_MACH_RB_493, "493", "MikroTik RouterBOARD 493/AH",
346 #define RB493G_GPIO_MDIO_MDC 7
347 #define RB493G_GPIO_MDIO_DATA 8
349 #define RB493G_MDIO_PHYMASK BIT(0)
351 static struct mdio_gpio_platform_data rb493g_mdio_data = {
352 .mdc = RB493G_GPIO_MDIO_MDC,
353 .mdio = RB493G_GPIO_MDIO_DATA,
355 .phy_mask = ~RB493G_MDIO_PHYMASK,
358 static struct platform_device rb493g_mdio_device = {
362 .platform_data = &rb493g_mdio_data,
366 static void __init rb493g_setup(void)
368 ath79_gpio_function_enable(AR71XX_GPIO_FUNC_SPI_CS1_EN |
369 AR71XX_GPIO_FUNC_SPI_CS2_EN);
371 ath79_register_leds_gpio(-1, ARRAY_SIZE(rb4xx_leds_gpio),
374 spi_register_board_info(rb4xx_spi_info, ARRAY_SIZE(rb4xx_spi_info));
375 platform_device_register(&rb4xx_spi_device);
376 platform_device_register(&rb4xx_nand_device);
378 ath79_register_mdio(0, ~RB493G_MDIO_PHYMASK);
380 ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
381 ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
382 ath79_eth0_data.phy_mask = RB493G_MDIO_PHYMASK;
383 ath79_eth0_data.speed = SPEED_1000;
384 ath79_eth0_data.duplex = DUPLEX_FULL;
386 ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1);
387 ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
388 ath79_eth1_data.mii_bus_dev = &rb493g_mdio_device.dev;
389 ath79_eth1_data.phy_mask = RB493G_MDIO_PHYMASK;
390 ath79_eth1_data.speed = SPEED_1000;
391 ath79_eth1_data.duplex = DUPLEX_FULL;
393 platform_device_register(&rb493g_mdio_device);
395 ath79_register_eth(1);
396 ath79_register_eth(0);
398 ath79_register_usb();
400 ath79_pci_set_irq_map(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs);
401 ath79_register_pci();
404 MIPS_MACHINE(ATH79_MACH_RB_493G, "493G", "MikroTik RouterBOARD 493G",