target/linux/ar71xx/files/arch/mips/ath79/mach-om5pacv2.c

   1 /*
   2  *  OpenMesh OM5P-ACv2 support
   3  *
   4  *  Copyright (C) 2013 Marek Lindner <marek@open-mesh.com>
   5  *  Copyright (C) 2014-2016 Sven Eckelmann <sven@open-mesh.com>
   6  *  Copyright (C) 2015 Open-Mesh - Jim Collar <jim.collar@eqware.net>
   7  *
   8  *  This program is free software; you can redistribute it and/or modify it
   9  *  under the terms of the GNU General Public License version 2 as published
  10  *  by the Free Software Foundation.
  11  */
  12
  13 #include <linux/gpio.h>
  14 #include <linux/mtd/mtd.h>
  15 #include <linux/mtd/partitions.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/i2c.h>
  18 #include <linux/i2c-algo-bit.h>
  19 #include <linux/i2c-gpio.h>
  20 #include <linux/platform_data/phy-at803x.h>
  21
  22 #include <asm/mach-ath79/ar71xx_regs.h>
  23 #include <asm/mach-ath79/ath79.h>
  24
  25 #include "common.h"
  26 #include "dev-ap9x-pci.h"
  27 #include "dev-eth.h"
  28 #include "dev-gpio-buttons.h"
  29 #include "dev-leds-gpio.h"
  30 #include "dev-m25p80.h"
  31 #include "dev-wmac.h"
  32 #include "machtypes.h"
  33 #include "pci.h"
  34
  35 #define OM5PACV2_GPIO_LED_POWER 14
  36 #define OM5PACV2_GPIO_LED_GREEN 13
  37 #define OM5PACV2_GPIO_LED_RED   23
  38 #define OM5PACV2_GPIO_LED_YELLOW        15
  39 #define OM5PACV2_GPIO_BTN_RESET 1
  40 #define OM5PACV2_GPIO_I2C_SCL   18
  41 #define OM5PACV2_GPIO_I2C_SDA   19
  42 #define OM5PACV2_GPIO_PA_DCDC   2
  43 #define OM5PACV2_GPIO_PA_HIGH   16
  44
  45 #define OM5PACV2_KEYS_POLL_INTERVAL     20      /* msecs */
  46 #define OM5PACV2_KEYS_DEBOUNCE_INTERVAL (3 * OM5PACV2_KEYS_POLL_INTERVAL)
  47
  48 #define OM5PACV2_WMAC_CALDATA_OFFSET    0x1000
  49
  50 static struct gpio_led om5pacv2_leds_gpio[] __initdata = {
  51         {
  52                 .name           = "om5pac:blue:power",
  53                 .gpio           = OM5PACV2_GPIO_LED_POWER,
  54                 .active_low     = 1,
  55         }, {
  56                 .name           = "om5pac:red:wifi",
  57                 .gpio           = OM5PACV2_GPIO_LED_RED,
  58                 .active_low     = 1,
  59         }, {
  60                 .name           = "om5pac:yellow:wifi",
  61                 .gpio           = OM5PACV2_GPIO_LED_YELLOW,
  62                 .active_low     = 1,
  63         }, {
  64                 .name           = "om5pac:green:wifi",
  65                 .gpio           = OM5PACV2_GPIO_LED_GREEN,
  66                 .active_low     = 1,
  67         }
  68 };
  69
  70 static struct gpio_keys_button om5pacv2_gpio_keys[] __initdata = {
  71         {
  72                 .desc           = "reset",
  73                 .type           = EV_KEY,
  74                 .code           = KEY_RESTART,
  75                 .debounce_interval = OM5PACV2_KEYS_DEBOUNCE_INTERVAL,
  76                 .gpio           = OM5PACV2_GPIO_BTN_RESET,
  77                 .active_low     = 1,
  78         }
  79 };
  80
  81 static struct i2c_gpio_platform_data om5pacv2_i2c_device_platdata = {
  82         .sda_pin                = OM5PACV2_GPIO_I2C_SDA,
  83         .scl_pin                = OM5PACV2_GPIO_I2C_SCL,
  84         .udelay                 = 10,
  85         .sda_is_open_drain      = 1,
  86         .scl_is_open_drain      = 1,
  87 };
  88
  89 static struct platform_device om5pacv2_i2c_device = {
  90         .name           = "i2c-gpio",
  91         .id             = 0,
  92         .dev            = {
  93                 .platform_data  = &om5pacv2_i2c_device_platdata,
  94         },
  95 };
  96
  97 static struct i2c_board_info om5pacv2_i2c_devs[] __initdata = {
  98         {
  99                 I2C_BOARD_INFO("tmp423", 0x4e),
 100         },
 101 };
 102
 103 static struct flash_platform_data om5pacv2_flash_data = {
 104         .type = "mx25l12805d",
 105 };
 106
 107 static struct at803x_platform_data om5pacv2_an_at803x_data = {
 108         .disable_smarteee = 1,
 109         .enable_rgmii_rx_delay = 1,
 110         .enable_rgmii_tx_delay = 1,
 111 };
 112
 113 static struct at803x_platform_data om5pacv2_an_at8031_data = {
 114         .disable_smarteee = 1,
 115         .enable_rgmii_rx_delay = 1,
 116         .enable_rgmii_tx_delay = 1,
 117 };
 118
 119 static struct mdio_board_info om5pacv2_an_mdio0_info[] = {
 120         {
 121                 .bus_id = "ag71xx-mdio.0",
 122                 .mdio_addr = 4,
 123                 .platform_data = &om5pacv2_an_at803x_data,
 124         },
 125         {
 126                 .bus_id = "ag71xx-mdio.1",
 127                 .mdio_addr = 1,
 128                 .platform_data = &om5pacv2_an_at8031_data,
 129         },
 130 };
 131
 132 static void __init om5p_acv2_setup_qca955x_eth_cfg(u32 mask,
 133                                                    unsigned int rxd,
 134                                                    unsigned int rxdv,
 135                                                    unsigned int txd,
 136                                                    unsigned int txe)
 137 {
 138         void __iomem *base;
 139         u32 t;
 140
 141         base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
 142
 143         t = mask;
 144         t |= rxd << QCA955X_ETH_CFG_RXD_DELAY_SHIFT;
 145         t |= rxdv << QCA955X_ETH_CFG_RDV_DELAY_SHIFT;
 146         t |= txd << QCA955X_ETH_CFG_TXD_DELAY_SHIFT;
 147         t |= txe << QCA955X_ETH_CFG_TXE_DELAY_SHIFT;
 148
 149         __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
 150
 151         iounmap(base);
 152 }
 153
 154 static void __init om5p_acv2_setup(void)
 155 {
 156         u8 *art = (u8 *)KSEG1ADDR(0x1fff0000);
 157         u8 mac[6];
 158
 159         /* power amplifier high power, 4.2V at RFFM4203/4503 instead of 3.3 */
 160         ath79_gpio_function_enable(QCA955X_GPIO_FUNC_JTAG_DISABLE);
 161         ath79_gpio_output_select(OM5PACV2_GPIO_PA_DCDC, QCA955X_GPIO_OUT_GPIO);
 162         ath79_gpio_output_select(OM5PACV2_GPIO_PA_HIGH, QCA955X_GPIO_OUT_GPIO);
 163         gpio_request_one(OM5PACV2_GPIO_PA_DCDC, GPIOF_OUT_INIT_HIGH,
 164                          "PA DC/DC");
 165         gpio_request_one(OM5PACV2_GPIO_PA_HIGH, GPIOF_OUT_INIT_HIGH, "PA HIGH");
 166
 167         /* temperature sensor */
 168         platform_device_register(&om5pacv2_i2c_device);
 169         i2c_register_board_info(0, om5pacv2_i2c_devs,
 170                                 ARRAY_SIZE(om5pacv2_i2c_devs));
 171
 172         ath79_register_m25p80(&om5pacv2_flash_data);
 173         ath79_register_leds_gpio(-1, ARRAY_SIZE(om5pacv2_leds_gpio),
 174                                  om5pacv2_leds_gpio);
 175         ath79_register_gpio_keys_polled(-1, OM5PACV2_KEYS_POLL_INTERVAL,
 176                                         ARRAY_SIZE(om5pacv2_gpio_keys),
 177                                         om5pacv2_gpio_keys);
 178
 179         ath79_init_mac(mac, art, 0x02);
 180         ath79_register_wmac(art + OM5PACV2_WMAC_CALDATA_OFFSET, mac);
 181
 182         om5p_acv2_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 2, 2, 0, 0);
 183         ath79_register_mdio(0, 0x0);
 184         ath79_register_mdio(1, 0x0);
 185
 186         mdiobus_register_board_info(om5pacv2_an_mdio0_info,
 187                                     ARRAY_SIZE(om5pacv2_an_mdio0_info));
 188
 189         ath79_init_mac(ath79_eth0_data.mac_addr, art, 0x00);
 190         ath79_init_mac(ath79_eth1_data.mac_addr, art, 0x01);
 191
 192         /* GMAC0 is connected to the PHY4 */
 193         ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
 194         ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
 195         ath79_eth0_data.phy_mask = BIT(4);
 196         ath79_eth0_pll_data.pll_1000 = 0x82000101;
 197         ath79_eth0_pll_data.pll_100 = 0x80000101;
 198         ath79_eth0_pll_data.pll_10 = 0x80001313;
 199         ath79_register_eth(0);
 200
 201         /* GMAC1 is connected to MDIO1 in SGMII mode */
 202         ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
 203         ath79_eth1_data.mii_bus_dev = &ath79_mdio1_device.dev;
 204         ath79_eth1_data.phy_mask = BIT(1);
 205         ath79_eth1_pll_data.pll_1000 = 0x03000101;
 206         ath79_eth1_pll_data.pll_100 = 0x80000101;
 207         ath79_eth1_pll_data.pll_10 = 0x80001313;
 208         ath79_eth1_data.speed = SPEED_1000;
 209         ath79_eth1_data.duplex = DUPLEX_FULL;
 210         ath79_register_eth(1);
 211
 212         ath79_register_pci();
 213 }
 214
 215 MIPS_MACHINE(ATH79_MACH_OM5P_ACv2, "OM5P-ACv2", "OpenMesh OM5P ACv2", om5p_acv2_setup);