4 * Copyright (c) 2012 Qualcomm Atheros
5 * Copyright (c) 2012-2013 Marek Lindner <marek@open-mesh.com>
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 #include <linux/platform_device.h>
22 #include <linux/ar8216_platform.h>
23 #include <linux/ath9k_platform.h>
25 #include <asm/mach-ath79/ar71xx_regs.h>
26 #include <linux/platform_data/phy-at803x.h>
29 #include "dev-ap9x-pci.h"
30 #include "dev-gpio-buttons.h"
32 #include "dev-leds-gpio.h"
33 #include "dev-m25p80.h"
35 #include "machtypes.h"
38 #define MR900_GPIO_LED_LAN 12
39 #define MR900_GPIO_LED_WLAN_2G 13
40 #define MR900_GPIO_LED_STATUS_GREEN 19
41 #define MR900_GPIO_LED_STATUS_RED 21
42 #define MR900_GPIO_LED_POWER 22
43 #define MR900_GPIO_LED_WLAN_5G 23
45 #define MR900_GPIO_BTN_RESET 17
47 #define MR900_KEYS_POLL_INTERVAL 20 /* msecs */
48 #define MR900_KEYS_DEBOUNCE_INTERVAL (3 * MR900_KEYS_POLL_INTERVAL)
50 #define MR900_MAC0_OFFSET 0
51 #define MR900_WMAC_CALDATA_OFFSET 0x1000
52 #define MR900_PCIE_CALDATA_OFFSET 0x5000
54 static struct gpio_led mr900_leds_gpio[] __initdata = {
56 .name = "mr900:blue:power",
57 .gpio = MR900_GPIO_LED_POWER,
61 .name = "mr900:blue:wan",
62 .gpio = MR900_GPIO_LED_LAN,
66 .name = "mr900:blue:wlan24",
67 .gpio = MR900_GPIO_LED_WLAN_2G,
71 .name = "mr900:blue:wlan58",
72 .gpio = MR900_GPIO_LED_WLAN_5G,
76 .name = "mr900:green:status",
77 .gpio = MR900_GPIO_LED_STATUS_GREEN,
81 .name = "mr900:red:status",
82 .gpio = MR900_GPIO_LED_STATUS_RED,
87 static struct gpio_keys_button mr900_gpio_keys[] __initdata = {
89 .desc = "Reset button",
92 .debounce_interval = MR900_KEYS_DEBOUNCE_INTERVAL,
93 .gpio = MR900_GPIO_BTN_RESET,
98 static struct at803x_platform_data mr900_at803x_data = {
99 .disable_smarteee = 1,
100 .enable_rgmii_rx_delay = 1,
101 .enable_rgmii_tx_delay = 0,
102 .fixup_rgmii_tx_delay = 1,
105 static struct mdio_board_info mr900_mdio0_info[] = {
107 .bus_id = "ag71xx-mdio.0",
109 .platform_data = &mr900_at803x_data,
113 static void __init mr900_setup_qca955x_eth_cfg(u32 mask,
122 base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
125 t |= rxd << QCA955X_ETH_CFG_RXD_DELAY_SHIFT;
126 t |= rxdv << QCA955X_ETH_CFG_RDV_DELAY_SHIFT;
127 t |= txd << QCA955X_ETH_CFG_TXD_DELAY_SHIFT;
128 t |= txe << QCA955X_ETH_CFG_TXE_DELAY_SHIFT;
130 __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
135 static void __init mr900_setup(void)
137 u8 *art = (u8 *)KSEG1ADDR(0x1fff0000);
138 u8 mac[6], pcie_mac[6];
139 struct ath9k_platform_data *pdata;
141 ath79_eth0_pll_data.pll_1000 = 0xae000000;
142 ath79_eth0_pll_data.pll_100 = 0xa0000101;
143 ath79_eth0_pll_data.pll_10 = 0xa0001313;
145 ath79_register_m25p80(NULL);
147 ath79_register_leds_gpio(-1, ARRAY_SIZE(mr900_leds_gpio),
149 ath79_register_gpio_keys_polled(-1, MR900_KEYS_POLL_INTERVAL,
150 ARRAY_SIZE(mr900_gpio_keys),
153 ath79_init_mac(mac, art + MR900_MAC0_OFFSET, 1);
154 ath79_register_wmac(art + MR900_WMAC_CALDATA_OFFSET, mac);
155 ath79_init_mac(pcie_mac, art + MR900_MAC0_OFFSET, 16);
156 ap91_pci_init(art + MR900_PCIE_CALDATA_OFFSET, pcie_mac);
157 pdata = ap9x_pci_get_wmac_data(0);
159 pr_err("mr900: unable to get address of wlan data\n");
162 pdata->use_eeprom = true;
164 mr900_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
165 ath79_register_mdio(0, 0x0);
167 mdiobus_register_board_info(mr900_mdio0_info,
168 ARRAY_SIZE(mr900_mdio0_info));
170 ath79_init_mac(ath79_eth0_data.mac_addr, art + MR900_MAC0_OFFSET, 0);
172 /* GMAC0 is connected to the RMGII interface */
173 ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
174 ath79_eth0_data.phy_mask = BIT(5);
175 ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
177 ath79_register_eth(0);
180 MIPS_MACHINE(ATH79_MACH_MR900, "MR900", "OpenMesh MR900", mr900_setup);
181 MIPS_MACHINE(ATH79_MACH_MR900v2, "MR900v2", "OpenMesh MR900v2", mr900_setup);