target/linux/ar71xx/files/arch/mips/ath79/mach-domywifi-dw33d.c

   1 /*
   2  * DomyWifi DW33D support
   3  *
   4  * Copyright (c) 2012 Qualcomm Atheros
   5  * Copyright (c) 2012-2013 Gabor Juhos <juhosg@openwrt.org>
   6  *
   7  * Permission to use, copy, modify, and/or distribute this software for any
   8  * purpose with or without fee is hereby granted, provided that the above
   9  * copyright notice and this permission notice appear in all copies.
  10  *
  11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18  *
  19  */
  20
  21 #include <linux/version.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/ar8216_platform.h>
  24 #include <linux/mtd/mtd.h>
  25 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,14,0)
  26 #include <linux/mtd/nand.h>
  27 #else
  28 #include <linux/mtd/rawnand.h>
  29 #endif
  30 #include <linux/platform/ar934x_nfc.h>
  31
  32 #include <asm/mach-ath79/ar71xx_regs.h>
  33
  34 #include "common.h"
  35 #include "pci.h"
  36 #include "dev-ap9x-pci.h"
  37 #include "dev-gpio-buttons.h"
  38 #include "dev-eth.h"
  39 #include "dev-leds-gpio.h"
  40 #include "dev-m25p80.h"
  41 #include "dev-nfc.h"
  42 #include "dev-usb.h"
  43 #include "dev-wmac.h"
  44 #include "machtypes.h"
  45
  46 #define DW33D_GPIO_LED_MMC              4
  47 #define DW33D_GPIO_LED_WLAN_2G          13
  48 #define DW33D_GPIO_LED_STATUS           14
  49 #define DW33D_GPIO_LED_USB              15
  50 #define DW33D_GPIO_LED_INTERNET         22
  51
  52 #define DW33D_GPIO_BTN_RESET            17
  53
  54 #define DW33D_KEYS_POLL_INTERVAL        20      /* msecs */
  55 #define DW33D_KEYS_DEBOUNCE_INTERVAL    (3 * DW33D_KEYS_POLL_INTERVAL)
  56
  57 #define DW33D_MAC0_OFFSET               0
  58 #define DW33D_MAC1_OFFSET               6
  59 #define DW33D_WMAC_OFFSET               12
  60 #define DW33D_WMAC_CALDATA_OFFSET       0x1000
  61 #define DW33D_PCIE_CALDATA_OFFSET       0x5000
  62
  63 static struct gpio_led dw33d_leds_gpio[] __initdata = {
  64         {
  65                 .name           = "dw33d:blue:status",
  66                 .gpio           = DW33D_GPIO_LED_STATUS,
  67                 .active_low     = 1,
  68         },
  69         {
  70                 .name           = "dw33d:blue:mmc",
  71                 .gpio           = DW33D_GPIO_LED_MMC,
  72                 .active_low     = 1,
  73         },
  74         {
  75                 .name           = "dw33d:blue:usb",
  76                 .gpio           = DW33D_GPIO_LED_USB,
  77                 .active_low     = 1,
  78         },
  79         {
  80                 .name           = "dw33d:blue:wlan-2g",
  81                 .gpio           = DW33D_GPIO_LED_WLAN_2G,
  82                 .active_low     = 1,
  83         },
  84         {
  85                 .name           = "dw33d:blue:internet",
  86                 .gpio           = DW33D_GPIO_LED_INTERNET,
  87                 .active_low     = 1,
  88         }
  89 };
  90
  91 static struct gpio_keys_button dw33d_gpio_keys[] __initdata = {
  92         {
  93                 .desc           = "Reset button",
  94                 .type           = EV_KEY,
  95                 .code           = KEY_RESTART,
  96                 .debounce_interval = DW33D_KEYS_DEBOUNCE_INTERVAL,
  97                 .gpio           = DW33D_GPIO_BTN_RESET,
  98                 .active_low     = 1,
  99         }
 100 };
 101
 102 /* GMAC6 of the QCA8337 switch is connected to the QCA9558 SoC via SGMII */
 103 static struct ar8327_pad_cfg dw33d_qca8337_pad6_cfg = {
 104         .mode = AR8327_PAD_MAC_SGMII,
 105         .sgmii_delay_en = true,
 106 };
 107
 108 /* GMAC0 of the QCA8337 switch is connected to the QCA9558 SoC via RGMII */
 109 static struct ar8327_pad_cfg dw33d_qca8337_pad0_cfg = {
 110         .mode = AR8327_PAD_MAC_RGMII,
 111         .txclk_delay_en = true,
 112         .rxclk_delay_en = true,
 113         .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
 114         .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
 115 };
 116
 117 static struct ar8327_platform_data dw33d_qca8337_data = {
 118         .pad0_cfg = &dw33d_qca8337_pad0_cfg,
 119         .pad6_cfg = &dw33d_qca8337_pad6_cfg,
 120         .port0_cfg = {
 121                 .force_link = 1,
 122                 .speed = AR8327_PORT_SPEED_1000,
 123                 .duplex = 1,
 124                 .txpause = 1,
 125                 .rxpause = 1,
 126         },
 127         .port6_cfg = {
 128                 .force_link = 1,
 129                 .speed = AR8327_PORT_SPEED_1000,
 130                 .duplex = 1,
 131                 .txpause = 1,
 132                 .rxpause = 1,
 133         },
 134 };
 135
 136 static struct mdio_board_info dw33d_mdio0_info[] = {
 137         {
 138                 .bus_id = "ag71xx-mdio.0",
 139                 .mdio_addr = 0,
 140                 .platform_data = &dw33d_qca8337_data,
 141         },
 142 };
 143
 144 static void __init dw33d_setup(void)
 145 {
 146         u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
 147
 148         ath79_register_m25p80(NULL);
 149
 150         ath79_register_leds_gpio(-1, ARRAY_SIZE(dw33d_leds_gpio),
 151                                  dw33d_leds_gpio);
 152         ath79_register_gpio_keys_polled(-1, DW33D_KEYS_POLL_INTERVAL,
 153                                         ARRAY_SIZE(dw33d_gpio_keys),
 154                                         dw33d_gpio_keys);
 155
 156         ath79_register_usb();
 157         ath79_nfc_set_ecc_mode(AR934X_NFC_ECC_HW);
 158         ath79_register_nfc();
 159         ath79_register_pci();
 160
 161         ath79_register_wmac(art + DW33D_WMAC_CALDATA_OFFSET, art + DW33D_WMAC_OFFSET);
 162
 163         ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
 164
 165         ath79_register_mdio(0, 0x0);
 166
 167         ath79_init_mac(ath79_eth0_data.mac_addr, art + DW33D_MAC0_OFFSET, 0);
 168         ath79_init_mac(ath79_eth1_data.mac_addr, art + DW33D_MAC1_OFFSET, 0);
 169
 170         mdiobus_register_board_info(dw33d_mdio0_info,
 171                                     ARRAY_SIZE(dw33d_mdio0_info));
 172
 173         /* GMAC0 is connected to the RMGII interface */
 174         ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
 175         ath79_eth0_data.phy_mask = BIT(0);
 176         ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
 177         ath79_eth0_pll_data.pll_1000 = 0x56000000;
 178
 179         ath79_register_eth(0);
 180
 181         /* GMAC1 is connected tot eh SGMII interface */
 182         ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
 183         ath79_eth1_data.speed = SPEED_1000;
 184         ath79_eth1_data.duplex = DUPLEX_FULL;
 185         ath79_eth1_pll_data.pll_1000 = 0x03000101;
 186
 187         ath79_register_eth(1);
 188 }
 189
 190 MIPS_MACHINE(ATH79_MACH_DOMYWIFI_DW33D, "DW33D",
 191              "DomyWifi DW33D",
 192              dw33d_setup);