2 * D-Link DAP-2695 rev. A1 support
4 * Copyright (c) 2012 Qualcomm Atheros
5 * Copyright (c) 2012-2013 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (c) 2016 Stijn Tintel <stijn@linux-ipv6.be>
8 * Permission to use, copy, modify, and/or distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies.
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
22 #include <linux/mtd/mtd.h>
23 #include <linux/mtd/partitions.h>
24 #include <linux/platform_device.h>
25 #include <linux/ar8216_platform.h>
27 #include <asm/mach-ath79/ar71xx_regs.h>
31 #include "dev-ap9x-pci.h"
32 #include "dev-gpio-buttons.h"
34 #include "dev-leds-gpio.h"
35 #include "dev-m25p80.h"
38 #include "machtypes.h"
41 #define DAP2695_GPIO_LED_GREEN_POWER 23
42 #define DAP2695_GPIO_LED_RED_POWER 14
43 #define DAP2695_GPIO_LED_WLAN_2G 13
45 #define DAP2695_GPIO_BTN_RESET 17
47 #define DAP2695_KEYS_POLL_INTERVAL 20 /* msecs */
48 #define DAP2695_KEYS_DEBOUNCE_INTERVAL (3 * DAP2695_KEYS_POLL_INTERVAL)
50 #define DAP2695_NVRAM_ADDR 0x1f040000
51 #define DAP2695_NVRAM_SIZE 0x10000
53 #define DAP2695_MAC0_OFFSET 1
54 #define DAP2695_MAC1_OFFSET 2
55 #define DAP2695_WMAC_CALDATA_OFFSET 0x1000
57 static struct gpio_led dap2695_leds_gpio[] __initdata = {
59 .name = "d-link:green:power",
60 .gpio = DAP2695_GPIO_LED_GREEN_POWER,
64 .name = "d-link:red:power",
65 .gpio = DAP2695_GPIO_LED_RED_POWER,
69 .name = "d-link:green:wlan2g",
70 .gpio = DAP2695_GPIO_LED_WLAN_2G,
75 static struct gpio_keys_button dap2695_gpio_keys[] __initdata = {
80 .debounce_interval = DAP2695_KEYS_DEBOUNCE_INTERVAL,
81 .gpio = DAP2695_GPIO_BTN_RESET,
86 static struct ar8327_pad_cfg dap2695_ar8327_pad0_cfg = {
87 .mode = AR8327_PAD_MAC_RGMII,
88 .txclk_delay_en = true,
89 .rxclk_delay_en = true,
90 .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
91 .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
92 .mac06_exchange_dis = true,
95 static struct ar8327_pad_cfg dap2695_ar8327_pad6_cfg = {
96 .mode = AR8327_PAD_MAC_SGMII,
97 .sgmii_delay_en = true,
100 static struct ar8327_platform_data dap2695_ar8327_data = {
101 .pad0_cfg = &dap2695_ar8327_pad0_cfg,
102 .pad6_cfg = &dap2695_ar8327_pad6_cfg,
105 .speed = AR8327_PORT_SPEED_1000,
112 .speed = AR8327_PORT_SPEED_1000,
119 static struct mdio_board_info dap2695_mdio0_info[] = {
121 .bus_id = "ag71xx-mdio.0",
123 .platform_data = &dap2695_ar8327_data,
127 static struct flash_platform_data dap2695_flash_data = {
128 .type = "mx25l12805d",
131 static void dap2695_get_mac(const char *name, char *mac)
133 u8 *nvram = (u8 *) KSEG1ADDR(DAP2695_NVRAM_ADDR);
136 err = ath79_nvram_parse_mac_addr(nvram, DAP2695_NVRAM_SIZE,
139 pr_err("no MAC address found for %s\n", name);
142 static void __init dap2695_setup(void)
144 u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
145 u8 mac0[ETH_ALEN], mac1[ETH_ALEN], wmac0[ETH_ALEN];
147 dap2695_get_mac("lanmac=", mac0);
148 dap2695_get_mac("wanmac=", mac1);
149 dap2695_get_mac("wlanmac=", wmac0);
151 ath79_register_m25p80(&dap2695_flash_data);
153 ath79_register_leds_gpio(-1, ARRAY_SIZE(dap2695_leds_gpio),
155 ath79_register_gpio_keys_polled(-1, DAP2695_KEYS_POLL_INTERVAL,
156 ARRAY_SIZE(dap2695_gpio_keys),
159 ath79_register_wmac(art + DAP2695_WMAC_CALDATA_OFFSET, wmac0);
161 ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
163 ath79_register_mdio(0, 0x0);
165 mdiobus_register_board_info(dap2695_mdio0_info,
166 ARRAY_SIZE(dap2695_mdio0_info));
168 /* GMAC0 is connected to the RGMII interface */
169 ath79_init_mac(ath79_eth0_data.mac_addr, mac0, DAP2695_MAC0_OFFSET);
170 ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
171 ath79_eth0_data.phy_mask = BIT(0);
172 ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
173 ath79_eth0_pll_data.pll_1000 = 0x56000000;
175 ath79_register_eth(0);
177 /* GMAC1 is connected to the SGMII interface */
178 ath79_init_mac(ath79_eth1_data.mac_addr, mac1, DAP2695_MAC1_OFFSET);
179 ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
180 ath79_eth1_data.speed = SPEED_1000;
181 ath79_eth1_data.duplex = DUPLEX_FULL;
182 ath79_eth1_pll_data.pll_1000 = 0x03000101;
184 ath79_register_eth(1);
186 ath79_register_pci();
189 MIPS_MACHINE(ATH79_MACH_DAP_2695_A1, "DAP-2695-A1",
190 "D-Link DAP-2695 rev. A1",