2 * Atheros AR71xx SoC platform devices
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
8 * Parts of this file are based on Atheros 2.6.15 BSP
9 * Parts of this file are based on Atheros 2.6.31 BSP
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/etherdevice.h>
20 #include <linux/platform_device.h>
21 #include <linux/serial_8250.h>
23 #include <asm/mach-ath79/ath79.h>
24 #include <asm/mach-ath79/ar71xx_regs.h>
25 #include <asm/mach-ath79/irq.h>
30 unsigned char ath79_mac_base[ETH_ALEN] __initdata;
32 static struct resource ath79_mdio0_resources[] = {
35 .flags = IORESOURCE_MEM,
36 .start = AR71XX_GE0_BASE,
37 .end = AR71XX_GE0_BASE + 0x200 - 1,
41 static struct ag71xx_mdio_platform_data ath79_mdio0_data;
43 struct platform_device ath79_mdio0_device = {
44 .name = "ag71xx-mdio",
46 .resource = ath79_mdio0_resources,
47 .num_resources = ARRAY_SIZE(ath79_mdio0_resources),
49 .platform_data = &ath79_mdio0_data,
53 static struct resource ath79_mdio1_resources[] = {
56 .flags = IORESOURCE_MEM,
57 .start = AR71XX_GE1_BASE,
58 .end = AR71XX_GE1_BASE + 0x200 - 1,
62 static struct ag71xx_mdio_platform_data ath79_mdio1_data;
64 struct platform_device ath79_mdio1_device = {
65 .name = "ag71xx-mdio",
67 .resource = ath79_mdio1_resources,
68 .num_resources = ARRAY_SIZE(ath79_mdio1_resources),
70 .platform_data = &ath79_mdio1_data,
74 static void ath79_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift)
79 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
81 t = __raw_readl(base + cfg_reg);
84 __raw_writel(t, base + cfg_reg);
87 __raw_writel(pll_val, base + pll_reg);
90 __raw_writel(t, base + cfg_reg);
94 __raw_writel(t, base + cfg_reg);
97 printk(KERN_DEBUG "ar71xx: pll_reg %#x: %#x\n",
98 (unsigned int)(base + pll_reg), __raw_readl(base + pll_reg));
103 static void __init ath79_mii_ctrl_set_if(unsigned int reg,
109 base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
111 t = __raw_readl(base + reg);
112 t &= ~(AR71XX_MII_CTRL_IF_MASK);
113 t |= (mii_if & AR71XX_MII_CTRL_IF_MASK);
114 __raw_writel(t, base + reg);
119 static void ath79_mii_ctrl_set_speed(unsigned int reg, unsigned int speed)
122 unsigned int mii_speed;
127 mii_speed = AR71XX_MII_CTRL_SPEED_10;
130 mii_speed = AR71XX_MII_CTRL_SPEED_100;
133 mii_speed = AR71XX_MII_CTRL_SPEED_1000;
139 base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
141 t = __raw_readl(base + reg);
142 t &= ~(AR71XX_MII_CTRL_SPEED_MASK << AR71XX_MII_CTRL_SPEED_SHIFT);
143 t |= mii_speed << AR71XX_MII_CTRL_SPEED_SHIFT;
144 __raw_writel(t, base + reg);
149 void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
151 struct platform_device *mdio_dev;
152 struct ag71xx_mdio_platform_data *mdio_data;
155 if (ath79_soc == ATH79_SOC_AR9341 ||
156 ath79_soc == ATH79_SOC_AR9342 ||
157 ath79_soc == ATH79_SOC_AR9344)
163 printk(KERN_ERR "ar71xx: invalid MDIO id %u\n", id);
168 case ATH79_SOC_AR7241:
169 case ATH79_SOC_AR9330:
170 case ATH79_SOC_AR9331:
171 mdio_dev = &ath79_mdio1_device;
172 mdio_data = &ath79_mdio1_data;
175 case ATH79_SOC_AR9341:
176 case ATH79_SOC_AR9342:
177 case ATH79_SOC_AR9344:
179 mdio_dev = &ath79_mdio0_device;
180 mdio_data = &ath79_mdio0_data;
182 mdio_dev = &ath79_mdio1_device;
183 mdio_data = &ath79_mdio1_data;
187 case ATH79_SOC_AR7242:
188 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG,
189 AR7242_PLL_REG_ETH0_INT_CLOCK, 0x62000000,
190 AR71XX_ETH0_PLL_SHIFT);
193 mdio_dev = &ath79_mdio0_device;
194 mdio_data = &ath79_mdio0_data;
198 mdio_data->phy_mask = phy_mask;
201 case ATH79_SOC_AR7240:
202 case ATH79_SOC_AR7241:
203 case ATH79_SOC_AR9330:
204 case ATH79_SOC_AR9331:
205 mdio_data->is_ar7240 = 1;
208 case ATH79_SOC_AR9341:
209 case ATH79_SOC_AR9342:
210 case ATH79_SOC_AR9344:
212 mdio_data->is_ar7240 = 1;
219 platform_device_register(mdio_dev);
222 struct ath79_eth_pll_data ath79_eth0_pll_data;
223 struct ath79_eth_pll_data ath79_eth1_pll_data;
225 static u32 ath79_get_eth_pll(unsigned int mac, int speed)
227 struct ath79_eth_pll_data *pll_data;
232 pll_data = &ath79_eth0_pll_data;
235 pll_data = &ath79_eth1_pll_data;
243 pll_val = pll_data->pll_10;
246 pll_val = pll_data->pll_100;
249 pll_val = pll_data->pll_1000;
258 static void ath79_set_speed_ge0(int speed)
260 u32 val = ath79_get_eth_pll(0, speed);
262 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK,
263 val, AR71XX_ETH0_PLL_SHIFT);
264 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
267 static void ath79_set_speed_ge1(int speed)
269 u32 val = ath79_get_eth_pll(1, speed);
271 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK,
272 val, AR71XX_ETH1_PLL_SHIFT);
273 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
276 static void ar7242_set_speed_ge0(int speed)
278 u32 val = ath79_get_eth_pll(0, speed);
281 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
282 __raw_writel(val, base + AR7242_PLL_REG_ETH0_INT_CLOCK);
286 static void ar91xx_set_speed_ge0(int speed)
288 u32 val = ath79_get_eth_pll(0, speed);
290 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH0_INT_CLOCK,
291 val, AR913X_ETH0_PLL_SHIFT);
292 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
295 static void ar91xx_set_speed_ge1(int speed)
297 u32 val = ath79_get_eth_pll(1, speed);
299 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH1_INT_CLOCK,
300 val, AR913X_ETH1_PLL_SHIFT);
301 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
304 static void ar934x_set_speed_ge0(int speed)
309 static void ath79_set_speed_dummy(int speed)
313 static void ath79_ddr_no_flush(void)
317 static void ath79_ddr_flush_ge0(void)
319 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE0);
322 static void ath79_ddr_flush_ge1(void)
324 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE1);
327 static void ar724x_ddr_flush_ge0(void)
329 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE0);
332 static void ar724x_ddr_flush_ge1(void)
334 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE1);
337 static void ar91xx_ddr_flush_ge0(void)
339 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE0);
342 static void ar91xx_ddr_flush_ge1(void)
344 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE1);
347 static void ar933x_ddr_flush_ge0(void)
349 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE0);
352 static void ar933x_ddr_flush_ge1(void)
354 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE1);
357 static struct resource ath79_eth0_resources[] = {
360 .flags = IORESOURCE_MEM,
361 .start = AR71XX_GE0_BASE,
362 .end = AR71XX_GE0_BASE + 0x200 - 1,
365 .flags = IORESOURCE_IRQ,
366 .start = ATH79_CPU_IRQ_GE0,
367 .end = ATH79_CPU_IRQ_GE0,
371 struct ag71xx_platform_data ath79_eth0_data = {
372 .reset_bit = AR71XX_RESET_GE0_MAC,
375 struct platform_device ath79_eth0_device = {
378 .resource = ath79_eth0_resources,
379 .num_resources = ARRAY_SIZE(ath79_eth0_resources),
381 .platform_data = &ath79_eth0_data,
385 static struct resource ath79_eth1_resources[] = {
388 .flags = IORESOURCE_MEM,
389 .start = AR71XX_GE1_BASE,
390 .end = AR71XX_GE1_BASE + 0x200 - 1,
393 .flags = IORESOURCE_IRQ,
394 .start = ATH79_CPU_IRQ_GE1,
395 .end = ATH79_CPU_IRQ_GE1,
399 struct ag71xx_platform_data ath79_eth1_data = {
400 .reset_bit = AR71XX_RESET_GE1_MAC,
403 struct platform_device ath79_eth1_device = {
406 .resource = ath79_eth1_resources,
407 .num_resources = ARRAY_SIZE(ath79_eth1_resources),
409 .platform_data = &ath79_eth1_data,
413 struct ag71xx_switch_platform_data ath79_switch_data;
415 #define AR71XX_PLL_VAL_1000 0x00110000
416 #define AR71XX_PLL_VAL_100 0x00001099
417 #define AR71XX_PLL_VAL_10 0x00991099
419 #define AR724X_PLL_VAL_1000 0x00110000
420 #define AR724X_PLL_VAL_100 0x00001099
421 #define AR724X_PLL_VAL_10 0x00991099
423 #define AR7242_PLL_VAL_1000 0x16000000
424 #define AR7242_PLL_VAL_100 0x00000101
425 #define AR7242_PLL_VAL_10 0x00001616
427 #define AR913X_PLL_VAL_1000 0x1a000000
428 #define AR913X_PLL_VAL_100 0x13000a44
429 #define AR913X_PLL_VAL_10 0x00441099
431 #define AR933X_PLL_VAL_1000 0x00110000
432 #define AR933X_PLL_VAL_100 0x00001099
433 #define AR933X_PLL_VAL_10 0x00991099
435 #define AR934X_PLL_VAL_1000 0x00110000
436 #define AR934X_PLL_VAL_100 0x00001099
437 #define AR934X_PLL_VAL_10 0x00991099
439 static void __init ath79_init_eth_pll_data(unsigned int id)
441 struct ath79_eth_pll_data *pll_data;
442 u32 pll_10, pll_100, pll_1000;
446 pll_data = &ath79_eth0_pll_data;
449 pll_data = &ath79_eth1_pll_data;
456 case ATH79_SOC_AR7130:
457 case ATH79_SOC_AR7141:
458 case ATH79_SOC_AR7161:
459 pll_10 = AR71XX_PLL_VAL_10;
460 pll_100 = AR71XX_PLL_VAL_100;
461 pll_1000 = AR71XX_PLL_VAL_1000;
464 case ATH79_SOC_AR7240:
465 case ATH79_SOC_AR7241:
466 pll_10 = AR724X_PLL_VAL_10;
467 pll_100 = AR724X_PLL_VAL_100;
468 pll_1000 = AR724X_PLL_VAL_1000;
471 case ATH79_SOC_AR7242:
472 pll_10 = AR7242_PLL_VAL_10;
473 pll_100 = AR7242_PLL_VAL_100;
474 pll_1000 = AR7242_PLL_VAL_1000;
477 case ATH79_SOC_AR9130:
478 case ATH79_SOC_AR9132:
479 pll_10 = AR913X_PLL_VAL_10;
480 pll_100 = AR913X_PLL_VAL_100;
481 pll_1000 = AR913X_PLL_VAL_1000;
484 case ATH79_SOC_AR9330:
485 case ATH79_SOC_AR9331:
486 pll_10 = AR933X_PLL_VAL_10;
487 pll_100 = AR933X_PLL_VAL_100;
488 pll_1000 = AR933X_PLL_VAL_1000;
491 case ATH79_SOC_AR9341:
492 case ATH79_SOC_AR9342:
493 case ATH79_SOC_AR9344:
494 pll_10 = AR934X_PLL_VAL_10;
495 pll_100 = AR934X_PLL_VAL_100;
496 pll_1000 = AR934X_PLL_VAL_1000;
503 if (!pll_data->pll_10)
504 pll_data->pll_10 = pll_10;
506 if (!pll_data->pll_100)
507 pll_data->pll_100 = pll_100;
509 if (!pll_data->pll_1000)
510 pll_data->pll_1000 = pll_1000;
513 static int __init ath79_setup_phy_if_mode(unsigned int id,
514 struct ag71xx_platform_data *pdata)
521 case ATH79_SOC_AR7130:
522 case ATH79_SOC_AR7141:
523 case ATH79_SOC_AR7161:
524 case ATH79_SOC_AR9130:
525 case ATH79_SOC_AR9132:
526 switch (pdata->phy_if_mode) {
527 case PHY_INTERFACE_MODE_MII:
528 mii_if = AR71XX_MII0_CTRL_IF_MII;
530 case PHY_INTERFACE_MODE_GMII:
531 mii_if = AR71XX_MII0_CTRL_IF_GMII;
533 case PHY_INTERFACE_MODE_RGMII:
534 mii_if = AR71XX_MII0_CTRL_IF_RGMII;
536 case PHY_INTERFACE_MODE_RMII:
537 mii_if = AR71XX_MII0_CTRL_IF_RMII;
542 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII0_CTRL, mii_if);
545 case ATH79_SOC_AR7240:
546 case ATH79_SOC_AR7241:
547 case ATH79_SOC_AR9330:
548 case ATH79_SOC_AR9331:
549 pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
552 case ATH79_SOC_AR7242:
555 case ATH79_SOC_AR9341:
556 case ATH79_SOC_AR9342:
557 case ATH79_SOC_AR9344:
558 switch (pdata->phy_if_mode) {
559 case PHY_INTERFACE_MODE_MII:
560 case PHY_INTERFACE_MODE_GMII:
561 case PHY_INTERFACE_MODE_RGMII:
562 case PHY_INTERFACE_MODE_RMII:
575 case ATH79_SOC_AR7130:
576 case ATH79_SOC_AR7141:
577 case ATH79_SOC_AR7161:
578 case ATH79_SOC_AR9130:
579 case ATH79_SOC_AR9132:
580 switch (pdata->phy_if_mode) {
581 case PHY_INTERFACE_MODE_RMII:
582 mii_if = AR71XX_MII1_CTRL_IF_RMII;
584 case PHY_INTERFACE_MODE_RGMII:
585 mii_if = AR71XX_MII1_CTRL_IF_RGMII;
590 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII1_CTRL, mii_if);
593 case ATH79_SOC_AR7240:
594 case ATH79_SOC_AR7241:
595 case ATH79_SOC_AR9330:
596 case ATH79_SOC_AR9331:
597 pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
600 case ATH79_SOC_AR7242:
603 case ATH79_SOC_AR9341:
604 case ATH79_SOC_AR9342:
605 case ATH79_SOC_AR9344:
606 switch (pdata->phy_if_mode) {
607 case PHY_INTERFACE_MODE_MII:
608 case PHY_INTERFACE_MODE_GMII:
624 static int ath79_eth_instance __initdata;
625 void __init ath79_register_eth(unsigned int id)
627 struct platform_device *pdev;
628 struct ag71xx_platform_data *pdata;
632 printk(KERN_ERR "ar71xx: invalid ethernet id %d\n", id);
636 ath79_init_eth_pll_data(id);
639 pdev = &ath79_eth0_device;
641 pdev = &ath79_eth1_device;
643 pdata = pdev->dev.platform_data;
645 err = ath79_setup_phy_if_mode(id, pdata);
648 "ar71xx: invalid PHY interface mode for GE%u\n", id);
653 case ATH79_SOC_AR7130:
655 pdata->ddr_flush = ath79_ddr_flush_ge0;
656 pdata->set_speed = ath79_set_speed_ge0;
658 pdata->ddr_flush = ath79_ddr_flush_ge1;
659 pdata->set_speed = ath79_set_speed_ge1;
663 case ATH79_SOC_AR7141:
664 case ATH79_SOC_AR7161:
666 pdata->ddr_flush = ath79_ddr_flush_ge0;
667 pdata->set_speed = ath79_set_speed_ge0;
669 pdata->ddr_flush = ath79_ddr_flush_ge1;
670 pdata->set_speed = ath79_set_speed_ge1;
675 case ATH79_SOC_AR7242:
677 pdata->reset_bit |= AR724X_RESET_GE0_MDIO |
678 AR71XX_RESET_GE0_PHY;
679 pdata->ddr_flush = ar724x_ddr_flush_ge0;
680 pdata->set_speed = ar7242_set_speed_ge0;
682 pdata->reset_bit |= AR724X_RESET_GE1_MDIO |
683 AR71XX_RESET_GE1_PHY;
684 pdata->ddr_flush = ar724x_ddr_flush_ge1;
685 pdata->set_speed = ath79_set_speed_dummy;
688 pdata->is_ar724x = 1;
690 if (!pdata->fifo_cfg1)
691 pdata->fifo_cfg1 = 0x0010ffff;
692 if (!pdata->fifo_cfg2)
693 pdata->fifo_cfg2 = 0x015500aa;
694 if (!pdata->fifo_cfg3)
695 pdata->fifo_cfg3 = 0x01f00140;
698 case ATH79_SOC_AR7241:
700 pdata->reset_bit |= AR724X_RESET_GE0_MDIO;
702 pdata->reset_bit |= AR724X_RESET_GE1_MDIO;
704 case ATH79_SOC_AR7240:
706 pdata->reset_bit |= AR71XX_RESET_GE0_PHY;
707 pdata->ddr_flush = ar724x_ddr_flush_ge0;
708 pdata->set_speed = ath79_set_speed_dummy;
710 pdata->phy_mask = BIT(4);
712 pdata->reset_bit |= AR71XX_RESET_GE1_PHY;
713 pdata->ddr_flush = ar724x_ddr_flush_ge1;
714 pdata->set_speed = ath79_set_speed_dummy;
716 pdata->speed = SPEED_1000;
717 pdata->duplex = DUPLEX_FULL;
718 pdata->switch_data = &ath79_switch_data;
721 pdata->is_ar724x = 1;
722 if (ath79_soc == ATH79_SOC_AR7240)
723 pdata->is_ar7240 = 1;
725 if (!pdata->fifo_cfg1)
726 pdata->fifo_cfg1 = 0x0010ffff;
727 if (!pdata->fifo_cfg2)
728 pdata->fifo_cfg2 = 0x015500aa;
729 if (!pdata->fifo_cfg3)
730 pdata->fifo_cfg3 = 0x01f00140;
733 case ATH79_SOC_AR9130:
735 pdata->ddr_flush = ar91xx_ddr_flush_ge0;
736 pdata->set_speed = ar91xx_set_speed_ge0;
738 pdata->ddr_flush = ar91xx_ddr_flush_ge1;
739 pdata->set_speed = ar91xx_set_speed_ge1;
741 pdata->is_ar91xx = 1;
744 case ATH79_SOC_AR9132:
746 pdata->ddr_flush = ar91xx_ddr_flush_ge0;
747 pdata->set_speed = ar91xx_set_speed_ge0;
749 pdata->ddr_flush = ar91xx_ddr_flush_ge1;
750 pdata->set_speed = ar91xx_set_speed_ge1;
752 pdata->is_ar91xx = 1;
756 case ATH79_SOC_AR9330:
757 case ATH79_SOC_AR9331:
759 pdata->reset_bit = AR933X_RESET_GE0_MAC |
760 AR933X_RESET_GE0_MDIO;
761 pdata->ddr_flush = ar933x_ddr_flush_ge0;
762 pdata->set_speed = ath79_set_speed_dummy;
764 pdata->phy_mask = BIT(4);
766 pdata->reset_bit = AR933X_RESET_GE1_MAC |
767 AR933X_RESET_GE1_MDIO;
768 pdata->ddr_flush = ar933x_ddr_flush_ge1;
769 pdata->set_speed = ath79_set_speed_dummy;
771 pdata->speed = SPEED_1000;
772 pdata->duplex = DUPLEX_FULL;
773 pdata->switch_data = &ath79_switch_data;
777 pdata->is_ar724x = 1;
779 if (!pdata->fifo_cfg1)
780 pdata->fifo_cfg1 = 0x0010ffff;
781 if (!pdata->fifo_cfg2)
782 pdata->fifo_cfg2 = 0x015500aa;
783 if (!pdata->fifo_cfg3)
784 pdata->fifo_cfg3 = 0x01f00140;
787 case ATH79_SOC_AR9341:
788 case ATH79_SOC_AR9342:
789 case ATH79_SOC_AR9344:
791 pdata->reset_bit = AR934X_RESET_GE0_MAC |
792 AR934X_RESET_GE0_MDIO;
793 pdata->set_speed = ar934x_set_speed_ge0;
795 pdata->reset_bit = AR934X_RESET_GE1_MAC |
796 AR934X_RESET_GE1_MDIO;
797 pdata->set_speed = ath79_set_speed_dummy;
799 pdata->switch_data = &ath79_switch_data;
802 pdata->ddr_flush = ath79_ddr_no_flush;
804 pdata->is_ar724x = 1;
806 if (!pdata->fifo_cfg1)
807 pdata->fifo_cfg1 = 0x0010ffff;
808 if (!pdata->fifo_cfg2)
809 pdata->fifo_cfg2 = 0x015500aa;
810 if (!pdata->fifo_cfg3)
811 pdata->fifo_cfg3 = 0x01f00140;
818 switch (pdata->phy_if_mode) {
819 case PHY_INTERFACE_MODE_GMII:
820 case PHY_INTERFACE_MODE_RGMII:
821 if (!pdata->has_gbit) {
822 printk(KERN_ERR "ar71xx: no gbit available on eth%d\n",
831 if (!is_valid_ether_addr(pdata->mac_addr)) {
832 random_ether_addr(pdata->mac_addr);
834 "ar71xx: using random MAC address for eth%d\n",
838 if (pdata->mii_bus_dev == NULL) {
840 case ATH79_SOC_AR9341:
841 case ATH79_SOC_AR9342:
842 case ATH79_SOC_AR9344:
844 pdata->mii_bus_dev = &ath79_mdio0_device.dev;
846 pdata->mii_bus_dev = &ath79_mdio1_device.dev;
849 case ATH79_SOC_AR7241:
850 case ATH79_SOC_AR9330:
851 case ATH79_SOC_AR9331:
852 pdata->mii_bus_dev = &ath79_mdio1_device.dev;
856 pdata->mii_bus_dev = &ath79_mdio0_device.dev;
861 /* Reset the device */
862 ath79_device_reset_set(pdata->reset_bit);
865 ath79_device_reset_clear(pdata->reset_bit);
868 platform_device_register(pdev);
869 ath79_eth_instance++;
872 void __init ath79_set_mac_base(unsigned char *mac)
874 memcpy(ath79_mac_base, mac, ETH_ALEN);
877 void __init ath79_parse_mac_addr(char *mac_str)
882 t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
883 &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
886 t = sscanf(mac_str, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
887 &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
890 ath79_set_mac_base(tmp);
892 printk(KERN_DEBUG "ar71xx: failed to parse mac address "
893 "\"%s\"\n", mac_str);
896 static int __init ath79_ethaddr_setup(char *str)
898 ath79_parse_mac_addr(str);
901 __setup("ethaddr=", ath79_ethaddr_setup);
903 static int __init ath79_kmac_setup(char *str)
905 ath79_parse_mac_addr(str);
908 __setup("kmac=", ath79_kmac_setup);
910 void __init ath79_init_mac(unsigned char *dst, const unsigned char *src,
915 if (!is_valid_ether_addr(src)) {
916 memset(dst, '\0', ETH_ALEN);
920 t = (((u32) src[3]) << 16) + (((u32) src[4]) << 8) + ((u32) src[5]);
926 dst[3] = (t >> 16) & 0xff;
927 dst[4] = (t >> 8) & 0xff;
931 void __init ath79_init_local_mac(unsigned char *dst, const unsigned char *src)
935 if (!is_valid_ether_addr(src)) {
936 memset(dst, '\0', ETH_ALEN);
940 for (i = 0; i < ETH_ALEN; i++)