2 * Atheros AR71xx SoC platform devices
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
8 * Parts of this file are based on Atheros 2.6.15 BSP
9 * Parts of this file are based on Atheros 2.6.31 BSP
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/etherdevice.h>
20 #include <linux/platform_device.h>
21 #include <linux/serial_8250.h>
22 #include <linux/clk.h>
24 #include <asm/mach-ath79/ath79.h>
25 #include <asm/mach-ath79/ar71xx_regs.h>
26 #include <asm/mach-ath79/irq.h>
31 unsigned char ath79_mac_base[ETH_ALEN] __initdata;
33 static struct resource ath79_mdio0_resources[] = {
36 .flags = IORESOURCE_MEM,
37 .start = AR71XX_GE0_BASE,
38 .end = AR71XX_GE0_BASE + 0x200 - 1,
42 static struct ag71xx_mdio_platform_data ath79_mdio0_data;
44 struct platform_device ath79_mdio0_device = {
45 .name = "ag71xx-mdio",
47 .resource = ath79_mdio0_resources,
48 .num_resources = ARRAY_SIZE(ath79_mdio0_resources),
50 .platform_data = &ath79_mdio0_data,
54 static struct resource ath79_mdio1_resources[] = {
57 .flags = IORESOURCE_MEM,
58 .start = AR71XX_GE1_BASE,
59 .end = AR71XX_GE1_BASE + 0x200 - 1,
63 static struct ag71xx_mdio_platform_data ath79_mdio1_data;
65 struct platform_device ath79_mdio1_device = {
66 .name = "ag71xx-mdio",
68 .resource = ath79_mdio1_resources,
69 .num_resources = ARRAY_SIZE(ath79_mdio1_resources),
71 .platform_data = &ath79_mdio1_data,
75 static void ath79_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift)
80 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
82 t = __raw_readl(base + cfg_reg);
85 __raw_writel(t, base + cfg_reg);
88 __raw_writel(pll_val, base + pll_reg);
91 __raw_writel(t, base + cfg_reg);
95 __raw_writel(t, base + cfg_reg);
98 printk(KERN_DEBUG "ar71xx: pll_reg %#x: %#x\n",
99 (unsigned int)(base + pll_reg), __raw_readl(base + pll_reg));
104 static void __init ath79_mii_ctrl_set_if(unsigned int reg,
110 base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
112 t = __raw_readl(base + reg);
113 t &= ~(AR71XX_MII_CTRL_IF_MASK);
114 t |= (mii_if & AR71XX_MII_CTRL_IF_MASK);
115 __raw_writel(t, base + reg);
120 static void ath79_mii_ctrl_set_speed(unsigned int reg, unsigned int speed)
123 unsigned int mii_speed;
128 mii_speed = AR71XX_MII_CTRL_SPEED_10;
131 mii_speed = AR71XX_MII_CTRL_SPEED_100;
134 mii_speed = AR71XX_MII_CTRL_SPEED_1000;
140 base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
142 t = __raw_readl(base + reg);
143 t &= ~(AR71XX_MII_CTRL_SPEED_MASK << AR71XX_MII_CTRL_SPEED_SHIFT);
144 t |= mii_speed << AR71XX_MII_CTRL_SPEED_SHIFT;
145 __raw_writel(t, base + reg);
150 static unsigned long ar934x_get_mdio_ref_clock(void)
156 base = ioremap(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
159 t = __raw_readl(base + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
160 if (t & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL) {
161 ret = 100 * 1000 * 1000;
165 clk = clk_get(NULL, "ref");
167 ret = clk_get_rate(clk);
175 void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
177 struct platform_device *mdio_dev;
178 struct ag71xx_mdio_platform_data *mdio_data;
181 if (ath79_soc == ATH79_SOC_AR9341 ||
182 ath79_soc == ATH79_SOC_AR9342 ||
183 ath79_soc == ATH79_SOC_AR9344 ||
184 ath79_soc == ATH79_SOC_QCA9558)
190 printk(KERN_ERR "ar71xx: invalid MDIO id %u\n", id);
195 case ATH79_SOC_AR7241:
196 case ATH79_SOC_AR9330:
197 case ATH79_SOC_AR9331:
198 mdio_dev = &ath79_mdio1_device;
199 mdio_data = &ath79_mdio1_data;
202 case ATH79_SOC_AR9341:
203 case ATH79_SOC_AR9342:
204 case ATH79_SOC_AR9344:
205 case ATH79_SOC_QCA9558:
207 mdio_dev = &ath79_mdio0_device;
208 mdio_data = &ath79_mdio0_data;
210 mdio_dev = &ath79_mdio1_device;
211 mdio_data = &ath79_mdio1_data;
215 case ATH79_SOC_AR7242:
216 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG,
217 AR7242_PLL_REG_ETH0_INT_CLOCK, 0x62000000,
218 AR71XX_ETH0_PLL_SHIFT);
221 mdio_dev = &ath79_mdio0_device;
222 mdio_data = &ath79_mdio0_data;
226 mdio_data->phy_mask = phy_mask;
229 case ATH79_SOC_AR7240:
230 mdio_data->is_ar7240 = 1;
232 case ATH79_SOC_AR7241:
233 mdio_data->builtin_switch = 1;
236 case ATH79_SOC_AR9330:
237 mdio_data->is_ar9330 = 1;
239 case ATH79_SOC_AR9331:
240 mdio_data->builtin_switch = 1;
243 case ATH79_SOC_AR9341:
244 case ATH79_SOC_AR9342:
245 case ATH79_SOC_AR9344:
247 mdio_data->builtin_switch = 1;
248 mdio_data->ref_clock = ar934x_get_mdio_ref_clock();
249 mdio_data->mdio_clock = 6250000;
251 mdio_data->is_ar934x = 1;
253 case ATH79_SOC_QCA9558:
255 mdio_data->builtin_switch = 1;
256 mdio_data->is_ar934x = 1;
263 platform_device_register(mdio_dev);
266 struct ath79_eth_pll_data ath79_eth0_pll_data;
267 struct ath79_eth_pll_data ath79_eth1_pll_data;
269 static u32 ath79_get_eth_pll(unsigned int mac, int speed)
271 struct ath79_eth_pll_data *pll_data;
276 pll_data = &ath79_eth0_pll_data;
279 pll_data = &ath79_eth1_pll_data;
287 pll_val = pll_data->pll_10;
290 pll_val = pll_data->pll_100;
293 pll_val = pll_data->pll_1000;
302 static void ath79_set_speed_ge0(int speed)
304 u32 val = ath79_get_eth_pll(0, speed);
306 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK,
307 val, AR71XX_ETH0_PLL_SHIFT);
308 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
311 static void ath79_set_speed_ge1(int speed)
313 u32 val = ath79_get_eth_pll(1, speed);
315 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK,
316 val, AR71XX_ETH1_PLL_SHIFT);
317 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
320 static void ar7242_set_speed_ge0(int speed)
322 u32 val = ath79_get_eth_pll(0, speed);
325 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
326 __raw_writel(val, base + AR7242_PLL_REG_ETH0_INT_CLOCK);
330 static void ar91xx_set_speed_ge0(int speed)
332 u32 val = ath79_get_eth_pll(0, speed);
334 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH0_INT_CLOCK,
335 val, AR913X_ETH0_PLL_SHIFT);
336 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
339 static void ar91xx_set_speed_ge1(int speed)
341 u32 val = ath79_get_eth_pll(1, speed);
343 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH1_INT_CLOCK,
344 val, AR913X_ETH1_PLL_SHIFT);
345 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
348 static void ar934x_set_speed_ge0(int speed)
351 u32 val = ath79_get_eth_pll(0, speed);
353 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
354 __raw_writel(val, base + AR934X_PLL_ETH_XMII_CONTROL_REG);
358 static void ath79_set_speed_dummy(int speed)
362 static void ath79_ddr_no_flush(void)
366 static void ath79_ddr_flush_ge0(void)
368 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE0);
371 static void ath79_ddr_flush_ge1(void)
373 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE1);
376 static void ar724x_ddr_flush_ge0(void)
378 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE0);
381 static void ar724x_ddr_flush_ge1(void)
383 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE1);
386 static void ar91xx_ddr_flush_ge0(void)
388 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE0);
391 static void ar91xx_ddr_flush_ge1(void)
393 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE1);
396 static void ar933x_ddr_flush_ge0(void)
398 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE0);
401 static void ar933x_ddr_flush_ge1(void)
403 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE1);
406 static struct resource ath79_eth0_resources[] = {
409 .flags = IORESOURCE_MEM,
410 .start = AR71XX_GE0_BASE,
411 .end = AR71XX_GE0_BASE + 0x200 - 1,
414 .flags = IORESOURCE_IRQ,
415 .start = ATH79_CPU_IRQ_GE0,
416 .end = ATH79_CPU_IRQ_GE0,
420 struct ag71xx_platform_data ath79_eth0_data = {
421 .reset_bit = AR71XX_RESET_GE0_MAC,
424 struct platform_device ath79_eth0_device = {
427 .resource = ath79_eth0_resources,
428 .num_resources = ARRAY_SIZE(ath79_eth0_resources),
430 .platform_data = &ath79_eth0_data,
434 static struct resource ath79_eth1_resources[] = {
437 .flags = IORESOURCE_MEM,
438 .start = AR71XX_GE1_BASE,
439 .end = AR71XX_GE1_BASE + 0x200 - 1,
442 .flags = IORESOURCE_IRQ,
443 .start = ATH79_CPU_IRQ_GE1,
444 .end = ATH79_CPU_IRQ_GE1,
448 struct ag71xx_platform_data ath79_eth1_data = {
449 .reset_bit = AR71XX_RESET_GE1_MAC,
452 struct platform_device ath79_eth1_device = {
455 .resource = ath79_eth1_resources,
456 .num_resources = ARRAY_SIZE(ath79_eth1_resources),
458 .platform_data = &ath79_eth1_data,
462 struct ag71xx_switch_platform_data ath79_switch_data;
464 #define AR71XX_PLL_VAL_1000 0x00110000
465 #define AR71XX_PLL_VAL_100 0x00001099
466 #define AR71XX_PLL_VAL_10 0x00991099
468 #define AR724X_PLL_VAL_1000 0x00110000
469 #define AR724X_PLL_VAL_100 0x00001099
470 #define AR724X_PLL_VAL_10 0x00991099
472 #define AR7242_PLL_VAL_1000 0x16000000
473 #define AR7242_PLL_VAL_100 0x00000101
474 #define AR7242_PLL_VAL_10 0x00001616
476 #define AR913X_PLL_VAL_1000 0x1a000000
477 #define AR913X_PLL_VAL_100 0x13000a44
478 #define AR913X_PLL_VAL_10 0x00441099
480 #define AR933X_PLL_VAL_1000 0x00110000
481 #define AR933X_PLL_VAL_100 0x00001099
482 #define AR933X_PLL_VAL_10 0x00991099
484 #define AR934X_PLL_VAL_1000 0x16000000
485 #define AR934X_PLL_VAL_100 0x00000101
486 #define AR934X_PLL_VAL_10 0x00001616
488 static void __init ath79_init_eth_pll_data(unsigned int id)
490 struct ath79_eth_pll_data *pll_data;
491 u32 pll_10, pll_100, pll_1000;
495 pll_data = &ath79_eth0_pll_data;
498 pll_data = &ath79_eth1_pll_data;
505 case ATH79_SOC_AR7130:
506 case ATH79_SOC_AR7141:
507 case ATH79_SOC_AR7161:
508 pll_10 = AR71XX_PLL_VAL_10;
509 pll_100 = AR71XX_PLL_VAL_100;
510 pll_1000 = AR71XX_PLL_VAL_1000;
513 case ATH79_SOC_AR7240:
514 case ATH79_SOC_AR7241:
515 pll_10 = AR724X_PLL_VAL_10;
516 pll_100 = AR724X_PLL_VAL_100;
517 pll_1000 = AR724X_PLL_VAL_1000;
520 case ATH79_SOC_AR7242:
521 pll_10 = AR7242_PLL_VAL_10;
522 pll_100 = AR7242_PLL_VAL_100;
523 pll_1000 = AR7242_PLL_VAL_1000;
526 case ATH79_SOC_AR9130:
527 case ATH79_SOC_AR9132:
528 pll_10 = AR913X_PLL_VAL_10;
529 pll_100 = AR913X_PLL_VAL_100;
530 pll_1000 = AR913X_PLL_VAL_1000;
533 case ATH79_SOC_AR9330:
534 case ATH79_SOC_AR9331:
535 pll_10 = AR933X_PLL_VAL_10;
536 pll_100 = AR933X_PLL_VAL_100;
537 pll_1000 = AR933X_PLL_VAL_1000;
540 case ATH79_SOC_AR9341:
541 case ATH79_SOC_AR9342:
542 case ATH79_SOC_AR9344:
543 case ATH79_SOC_QCA9558:
544 pll_10 = AR934X_PLL_VAL_10;
545 pll_100 = AR934X_PLL_VAL_100;
546 pll_1000 = AR934X_PLL_VAL_1000;
553 if (!pll_data->pll_10)
554 pll_data->pll_10 = pll_10;
556 if (!pll_data->pll_100)
557 pll_data->pll_100 = pll_100;
559 if (!pll_data->pll_1000)
560 pll_data->pll_1000 = pll_1000;
563 static int __init ath79_setup_phy_if_mode(unsigned int id,
564 struct ag71xx_platform_data *pdata)
571 case ATH79_SOC_AR7130:
572 case ATH79_SOC_AR7141:
573 case ATH79_SOC_AR7161:
574 case ATH79_SOC_AR9130:
575 case ATH79_SOC_AR9132:
576 switch (pdata->phy_if_mode) {
577 case PHY_INTERFACE_MODE_MII:
578 mii_if = AR71XX_MII0_CTRL_IF_MII;
580 case PHY_INTERFACE_MODE_GMII:
581 mii_if = AR71XX_MII0_CTRL_IF_GMII;
583 case PHY_INTERFACE_MODE_RGMII:
584 mii_if = AR71XX_MII0_CTRL_IF_RGMII;
586 case PHY_INTERFACE_MODE_RMII:
587 mii_if = AR71XX_MII0_CTRL_IF_RMII;
592 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII0_CTRL, mii_if);
595 case ATH79_SOC_AR7240:
596 case ATH79_SOC_AR7241:
597 case ATH79_SOC_AR9330:
598 case ATH79_SOC_AR9331:
599 pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
602 case ATH79_SOC_AR7242:
605 case ATH79_SOC_AR9341:
606 case ATH79_SOC_AR9342:
607 case ATH79_SOC_AR9344:
608 switch (pdata->phy_if_mode) {
609 case PHY_INTERFACE_MODE_MII:
610 case PHY_INTERFACE_MODE_GMII:
611 case PHY_INTERFACE_MODE_RGMII:
612 case PHY_INTERFACE_MODE_RMII:
619 case ATH79_SOC_QCA9558:
620 switch (pdata->phy_if_mode) {
621 case PHY_INTERFACE_MODE_MII:
622 case PHY_INTERFACE_MODE_RGMII:
623 case PHY_INTERFACE_MODE_SGMII:
636 case ATH79_SOC_AR7130:
637 case ATH79_SOC_AR7141:
638 case ATH79_SOC_AR7161:
639 case ATH79_SOC_AR9130:
640 case ATH79_SOC_AR9132:
641 switch (pdata->phy_if_mode) {
642 case PHY_INTERFACE_MODE_RMII:
643 mii_if = AR71XX_MII1_CTRL_IF_RMII;
645 case PHY_INTERFACE_MODE_RGMII:
646 mii_if = AR71XX_MII1_CTRL_IF_RGMII;
651 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII1_CTRL, mii_if);
654 case ATH79_SOC_AR7240:
655 case ATH79_SOC_AR7241:
656 case ATH79_SOC_AR9330:
657 case ATH79_SOC_AR9331:
658 pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
661 case ATH79_SOC_AR7242:
664 case ATH79_SOC_AR9341:
665 case ATH79_SOC_AR9342:
666 case ATH79_SOC_AR9344:
667 switch (pdata->phy_if_mode) {
668 case PHY_INTERFACE_MODE_MII:
669 case PHY_INTERFACE_MODE_GMII:
676 case ATH79_SOC_QCA9558:
677 switch (pdata->phy_if_mode) {
678 case PHY_INTERFACE_MODE_MII:
679 case PHY_INTERFACE_MODE_RGMII:
680 case PHY_INTERFACE_MODE_SGMII:
696 void __init ath79_setup_ar933x_phy4_switch(bool mac, bool mdio)
701 base = ioremap(AR933X_GMAC_BASE, AR933X_GMAC_SIZE);
703 t = __raw_readl(base + AR933X_GMAC_REG_ETH_CFG);
704 t &= ~(AR933X_ETH_CFG_SW_PHY_SWAP | AR933X_ETH_CFG_SW_PHY_ADDR_SWAP);
706 t |= AR933X_ETH_CFG_SW_PHY_SWAP;
708 t |= AR933X_ETH_CFG_SW_PHY_ADDR_SWAP;
709 __raw_writel(t, base + AR933X_GMAC_REG_ETH_CFG);
714 void __init ath79_setup_ar934x_eth_cfg(u32 mask)
719 base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
721 t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
723 t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 |
724 AR934X_ETH_CFG_MII_GMAC0 |
725 AR934X_ETH_CFG_GMII_GMAC0 |
726 AR934X_ETH_CFG_SW_ONLY_MODE |
727 AR934X_ETH_CFG_SW_PHY_SWAP);
731 __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
733 __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
738 static int ath79_eth_instance __initdata;
739 void __init ath79_register_eth(unsigned int id)
741 struct platform_device *pdev;
742 struct ag71xx_platform_data *pdata;
746 printk(KERN_ERR "ar71xx: invalid ethernet id %d\n", id);
750 ath79_init_eth_pll_data(id);
753 pdev = &ath79_eth0_device;
755 pdev = &ath79_eth1_device;
757 pdata = pdev->dev.platform_data;
759 err = ath79_setup_phy_if_mode(id, pdata);
762 "ar71xx: invalid PHY interface mode for GE%u\n", id);
767 case ATH79_SOC_AR7130:
769 pdata->ddr_flush = ath79_ddr_flush_ge0;
770 pdata->set_speed = ath79_set_speed_ge0;
772 pdata->ddr_flush = ath79_ddr_flush_ge1;
773 pdata->set_speed = ath79_set_speed_ge1;
777 case ATH79_SOC_AR7141:
778 case ATH79_SOC_AR7161:
780 pdata->ddr_flush = ath79_ddr_flush_ge0;
781 pdata->set_speed = ath79_set_speed_ge0;
783 pdata->ddr_flush = ath79_ddr_flush_ge1;
784 pdata->set_speed = ath79_set_speed_ge1;
789 case ATH79_SOC_AR7242:
791 pdata->reset_bit |= AR724X_RESET_GE0_MDIO |
792 AR71XX_RESET_GE0_PHY;
793 pdata->ddr_flush = ar724x_ddr_flush_ge0;
794 pdata->set_speed = ar7242_set_speed_ge0;
796 pdata->reset_bit |= AR724X_RESET_GE1_MDIO |
797 AR71XX_RESET_GE1_PHY;
798 pdata->ddr_flush = ar724x_ddr_flush_ge1;
799 pdata->set_speed = ath79_set_speed_dummy;
802 pdata->is_ar724x = 1;
804 if (!pdata->fifo_cfg1)
805 pdata->fifo_cfg1 = 0x0010ffff;
806 if (!pdata->fifo_cfg2)
807 pdata->fifo_cfg2 = 0x015500aa;
808 if (!pdata->fifo_cfg3)
809 pdata->fifo_cfg3 = 0x01f00140;
812 case ATH79_SOC_AR7241:
814 pdata->reset_bit |= AR724X_RESET_GE0_MDIO;
816 pdata->reset_bit |= AR724X_RESET_GE1_MDIO;
818 case ATH79_SOC_AR7240:
820 pdata->reset_bit |= AR71XX_RESET_GE0_PHY;
821 pdata->ddr_flush = ar724x_ddr_flush_ge0;
822 pdata->set_speed = ath79_set_speed_dummy;
824 pdata->phy_mask = BIT(4);
826 pdata->reset_bit |= AR71XX_RESET_GE1_PHY;
827 pdata->ddr_flush = ar724x_ddr_flush_ge1;
828 pdata->set_speed = ath79_set_speed_dummy;
830 pdata->speed = SPEED_1000;
831 pdata->duplex = DUPLEX_FULL;
832 pdata->switch_data = &ath79_switch_data;
834 ath79_switch_data.phy_poll_mask |= BIT(4);
837 pdata->is_ar724x = 1;
838 if (ath79_soc == ATH79_SOC_AR7240)
839 pdata->is_ar7240 = 1;
841 if (!pdata->fifo_cfg1)
842 pdata->fifo_cfg1 = 0x0010ffff;
843 if (!pdata->fifo_cfg2)
844 pdata->fifo_cfg2 = 0x015500aa;
845 if (!pdata->fifo_cfg3)
846 pdata->fifo_cfg3 = 0x01f00140;
849 case ATH79_SOC_AR9130:
851 pdata->ddr_flush = ar91xx_ddr_flush_ge0;
852 pdata->set_speed = ar91xx_set_speed_ge0;
854 pdata->ddr_flush = ar91xx_ddr_flush_ge1;
855 pdata->set_speed = ar91xx_set_speed_ge1;
857 pdata->is_ar91xx = 1;
860 case ATH79_SOC_AR9132:
862 pdata->ddr_flush = ar91xx_ddr_flush_ge0;
863 pdata->set_speed = ar91xx_set_speed_ge0;
865 pdata->ddr_flush = ar91xx_ddr_flush_ge1;
866 pdata->set_speed = ar91xx_set_speed_ge1;
868 pdata->is_ar91xx = 1;
872 case ATH79_SOC_AR9330:
873 case ATH79_SOC_AR9331:
875 pdata->reset_bit = AR933X_RESET_GE0_MAC |
876 AR933X_RESET_GE0_MDIO;
877 pdata->ddr_flush = ar933x_ddr_flush_ge0;
878 pdata->set_speed = ath79_set_speed_dummy;
880 pdata->phy_mask = BIT(4);
882 pdata->reset_bit = AR933X_RESET_GE1_MAC |
883 AR933X_RESET_GE1_MDIO;
884 pdata->ddr_flush = ar933x_ddr_flush_ge1;
885 pdata->set_speed = ath79_set_speed_dummy;
887 pdata->speed = SPEED_1000;
888 pdata->duplex = DUPLEX_FULL;
889 pdata->switch_data = &ath79_switch_data;
891 ath79_switch_data.phy_poll_mask |= BIT(4);
895 pdata->is_ar724x = 1;
897 if (!pdata->fifo_cfg1)
898 pdata->fifo_cfg1 = 0x0010ffff;
899 if (!pdata->fifo_cfg2)
900 pdata->fifo_cfg2 = 0x015500aa;
901 if (!pdata->fifo_cfg3)
902 pdata->fifo_cfg3 = 0x01f00140;
905 case ATH79_SOC_AR9341:
906 case ATH79_SOC_AR9342:
907 case ATH79_SOC_AR9344:
908 case ATH79_SOC_QCA9558:
910 pdata->reset_bit = AR934X_RESET_GE0_MAC |
911 AR934X_RESET_GE0_MDIO;
912 pdata->set_speed = ar934x_set_speed_ge0;
914 pdata->reset_bit = AR934X_RESET_GE1_MAC |
915 AR934X_RESET_GE1_MDIO;
916 pdata->set_speed = ath79_set_speed_dummy;
918 pdata->switch_data = &ath79_switch_data;
920 /* reset the built-in switch */
921 ath79_device_reset_set(AR934X_RESET_ETH_SWITCH);
922 ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH);
925 pdata->ddr_flush = ath79_ddr_no_flush;
927 pdata->is_ar724x = 1;
929 if (!pdata->fifo_cfg1)
930 pdata->fifo_cfg1 = 0x0010ffff;
931 if (!pdata->fifo_cfg2)
932 pdata->fifo_cfg2 = 0x015500aa;
933 if (!pdata->fifo_cfg3)
934 pdata->fifo_cfg3 = 0x01f00140;
941 switch (pdata->phy_if_mode) {
942 case PHY_INTERFACE_MODE_GMII:
943 case PHY_INTERFACE_MODE_RGMII:
944 case PHY_INTERFACE_MODE_SGMII:
945 if (!pdata->has_gbit) {
946 printk(KERN_ERR "ar71xx: no gbit available on eth%d\n",
955 if (!is_valid_ether_addr(pdata->mac_addr)) {
956 random_ether_addr(pdata->mac_addr);
958 "ar71xx: using random MAC address for eth%d\n",
962 if (pdata->mii_bus_dev == NULL) {
964 case ATH79_SOC_AR9341:
965 case ATH79_SOC_AR9342:
966 case ATH79_SOC_AR9344:
968 pdata->mii_bus_dev = &ath79_mdio0_device.dev;
970 pdata->mii_bus_dev = &ath79_mdio1_device.dev;
973 case ATH79_SOC_AR7241:
974 case ATH79_SOC_AR9330:
975 case ATH79_SOC_AR9331:
976 pdata->mii_bus_dev = &ath79_mdio1_device.dev;
979 case ATH79_SOC_QCA9558:
980 /* don't assign any MDIO device by default */
984 pdata->mii_bus_dev = &ath79_mdio0_device.dev;
989 /* Reset the device */
990 ath79_device_reset_set(pdata->reset_bit);
993 ath79_device_reset_clear(pdata->reset_bit);
996 platform_device_register(pdev);
997 ath79_eth_instance++;
1000 void __init ath79_set_mac_base(unsigned char *mac)
1002 memcpy(ath79_mac_base, mac, ETH_ALEN);
1005 void __init ath79_parse_mac_addr(char *mac_str)
1010 t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
1011 &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
1014 t = sscanf(mac_str, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
1015 &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
1018 ath79_set_mac_base(tmp);
1020 printk(KERN_DEBUG "ar71xx: failed to parse mac address "
1021 "\"%s\"\n", mac_str);
1024 static int __init ath79_ethaddr_setup(char *str)
1026 ath79_parse_mac_addr(str);
1029 __setup("ethaddr=", ath79_ethaddr_setup);
1031 static int __init ath79_kmac_setup(char *str)
1033 ath79_parse_mac_addr(str);
1036 __setup("kmac=", ath79_kmac_setup);
1038 void __init ath79_init_mac(unsigned char *dst, const unsigned char *src,
1046 if (!src || !is_valid_ether_addr(src)) {
1047 memset(dst, '\0', ETH_ALEN);
1051 t = (((u32) src[3]) << 16) + (((u32) src[4]) << 8) + ((u32) src[5]);
1057 dst[3] = (t >> 16) & 0xff;
1058 dst[4] = (t >> 8) & 0xff;
1062 void __init ath79_init_local_mac(unsigned char *dst, const unsigned char *src)
1069 if (!src || !is_valid_ether_addr(src)) {
1070 memset(dst, '\0', ETH_ALEN);
1074 for (i = 0; i < ETH_ALEN; i++)