2 * Atheros AR71xx SoC platform devices
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
8 * Parts of this file are based on Atheros 2.6.15 BSP
9 * Parts of this file are based on Atheros 2.6.31 BSP
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/etherdevice.h>
20 #include <linux/platform_device.h>
21 #include <linux/serial_8250.h>
23 #include <asm/mach-ath79/ath79.h>
24 #include <asm/mach-ath79/ar71xx_regs.h>
25 #include <asm/mach-ath79/irq.h>
30 unsigned char ath79_mac_base[ETH_ALEN] __initdata;
32 static struct resource ath79_mdio0_resources[] = {
35 .flags = IORESOURCE_MEM,
36 .start = AR71XX_GE0_BASE,
37 .end = AR71XX_GE0_BASE + 0x200 - 1,
41 static struct ag71xx_mdio_platform_data ath79_mdio0_data;
43 struct platform_device ath79_mdio0_device = {
44 .name = "ag71xx-mdio",
46 .resource = ath79_mdio0_resources,
47 .num_resources = ARRAY_SIZE(ath79_mdio0_resources),
49 .platform_data = &ath79_mdio0_data,
53 static struct resource ath79_mdio1_resources[] = {
56 .flags = IORESOURCE_MEM,
57 .start = AR71XX_GE1_BASE,
58 .end = AR71XX_GE1_BASE + 0x200 - 1,
62 static struct ag71xx_mdio_platform_data ath79_mdio1_data;
64 struct platform_device ath79_mdio1_device = {
65 .name = "ag71xx-mdio",
67 .resource = ath79_mdio1_resources,
68 .num_resources = ARRAY_SIZE(ath79_mdio1_resources),
70 .platform_data = &ath79_mdio1_data,
74 static void ath79_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift)
79 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
81 t = __raw_readl(base + cfg_reg);
84 __raw_writel(t, base + cfg_reg);
87 __raw_writel(pll_val, base + pll_reg);
90 __raw_writel(t, base + cfg_reg);
94 __raw_writel(t, base + cfg_reg);
97 printk(KERN_DEBUG "ar71xx: pll_reg %#x: %#x\n",
98 (unsigned int)(base + pll_reg), __raw_readl(base + pll_reg));
103 static void __init ath79_mii_ctrl_set_if(unsigned int reg,
109 base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
111 t = __raw_readl(base + reg);
112 t &= ~(AR71XX_MII_CTRL_IF_MASK);
113 t |= (mii_if & AR71XX_MII_CTRL_IF_MASK);
114 __raw_writel(t, base + reg);
119 static void ath79_mii_ctrl_set_speed(unsigned int reg, unsigned int speed)
122 unsigned int mii_speed;
127 mii_speed = AR71XX_MII_CTRL_SPEED_10;
130 mii_speed = AR71XX_MII_CTRL_SPEED_100;
133 mii_speed = AR71XX_MII_CTRL_SPEED_1000;
139 base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
141 t = __raw_readl(base + reg);
142 t &= ~(AR71XX_MII_CTRL_SPEED_MASK << AR71XX_MII_CTRL_SPEED_SHIFT);
143 t |= mii_speed << AR71XX_MII_CTRL_SPEED_SHIFT;
144 __raw_writel(t, base + reg);
149 void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
151 struct platform_device *mdio_dev;
152 struct ag71xx_mdio_platform_data *mdio_data;
155 if (ath79_soc == ATH79_SOC_AR9341 ||
156 ath79_soc == ATH79_SOC_AR9342 ||
157 ath79_soc == ATH79_SOC_AR9344)
163 printk(KERN_ERR "ar71xx: invalid MDIO id %u\n", id);
168 case ATH79_SOC_AR7241:
169 case ATH79_SOC_AR9330:
170 case ATH79_SOC_AR9331:
171 mdio_dev = &ath79_mdio1_device;
172 mdio_data = &ath79_mdio1_data;
175 case ATH79_SOC_AR9341:
176 case ATH79_SOC_AR9342:
177 case ATH79_SOC_AR9344:
179 mdio_dev = &ath79_mdio0_device;
180 mdio_data = &ath79_mdio0_data;
182 mdio_dev = &ath79_mdio1_device;
183 mdio_data = &ath79_mdio1_data;
187 case ATH79_SOC_AR7242:
188 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG,
189 AR7242_PLL_REG_ETH0_INT_CLOCK, 0x62000000,
190 AR71XX_ETH0_PLL_SHIFT);
193 mdio_dev = &ath79_mdio0_device;
194 mdio_data = &ath79_mdio0_data;
198 mdio_data->phy_mask = phy_mask;
201 case ATH79_SOC_AR7240:
202 case ATH79_SOC_AR7241:
203 case ATH79_SOC_AR9330:
204 case ATH79_SOC_AR9331:
205 mdio_data->is_ar7240 = 1;
208 case ATH79_SOC_AR9341:
209 case ATH79_SOC_AR9342:
210 case ATH79_SOC_AR9344:
212 mdio_data->is_ar7240 = 1;
219 platform_device_register(mdio_dev);
222 struct ath79_eth_pll_data ath79_eth0_pll_data;
223 struct ath79_eth_pll_data ath79_eth1_pll_data;
225 static u32 ath79_get_eth_pll(unsigned int mac, int speed)
227 struct ath79_eth_pll_data *pll_data;
232 pll_data = &ath79_eth0_pll_data;
235 pll_data = &ath79_eth1_pll_data;
243 pll_val = pll_data->pll_10;
246 pll_val = pll_data->pll_100;
249 pll_val = pll_data->pll_1000;
258 static void ath79_set_speed_ge0(int speed)
260 u32 val = ath79_get_eth_pll(0, speed);
262 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK,
263 val, AR71XX_ETH0_PLL_SHIFT);
264 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
267 static void ath79_set_speed_ge1(int speed)
269 u32 val = ath79_get_eth_pll(1, speed);
271 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK,
272 val, AR71XX_ETH1_PLL_SHIFT);
273 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
276 static void ar7242_set_speed_ge0(int speed)
278 u32 val = ath79_get_eth_pll(0, speed);
281 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
282 __raw_writel(val, base + AR7242_PLL_REG_ETH0_INT_CLOCK);
286 static void ar91xx_set_speed_ge0(int speed)
288 u32 val = ath79_get_eth_pll(0, speed);
290 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH0_INT_CLOCK,
291 val, AR913X_ETH0_PLL_SHIFT);
292 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
295 static void ar91xx_set_speed_ge1(int speed)
297 u32 val = ath79_get_eth_pll(1, speed);
299 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH1_INT_CLOCK,
300 val, AR913X_ETH1_PLL_SHIFT);
301 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
304 static void ar934x_set_speed_ge0(int speed)
307 u32 val = ath79_get_eth_pll(0, speed);
309 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
310 __raw_writel(val, base + AR934X_PLL_ETH_XMII_CONTROL_REG);
314 static void ath79_set_speed_dummy(int speed)
318 static void ath79_ddr_no_flush(void)
322 static void ath79_ddr_flush_ge0(void)
324 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE0);
327 static void ath79_ddr_flush_ge1(void)
329 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE1);
332 static void ar724x_ddr_flush_ge0(void)
334 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE0);
337 static void ar724x_ddr_flush_ge1(void)
339 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE1);
342 static void ar91xx_ddr_flush_ge0(void)
344 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE0);
347 static void ar91xx_ddr_flush_ge1(void)
349 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE1);
352 static void ar933x_ddr_flush_ge0(void)
354 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE0);
357 static void ar933x_ddr_flush_ge1(void)
359 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE1);
362 static struct resource ath79_eth0_resources[] = {
365 .flags = IORESOURCE_MEM,
366 .start = AR71XX_GE0_BASE,
367 .end = AR71XX_GE0_BASE + 0x200 - 1,
370 .flags = IORESOURCE_IRQ,
371 .start = ATH79_CPU_IRQ_GE0,
372 .end = ATH79_CPU_IRQ_GE0,
376 struct ag71xx_platform_data ath79_eth0_data = {
377 .reset_bit = AR71XX_RESET_GE0_MAC,
380 struct platform_device ath79_eth0_device = {
383 .resource = ath79_eth0_resources,
384 .num_resources = ARRAY_SIZE(ath79_eth0_resources),
386 .platform_data = &ath79_eth0_data,
390 static struct resource ath79_eth1_resources[] = {
393 .flags = IORESOURCE_MEM,
394 .start = AR71XX_GE1_BASE,
395 .end = AR71XX_GE1_BASE + 0x200 - 1,
398 .flags = IORESOURCE_IRQ,
399 .start = ATH79_CPU_IRQ_GE1,
400 .end = ATH79_CPU_IRQ_GE1,
404 struct ag71xx_platform_data ath79_eth1_data = {
405 .reset_bit = AR71XX_RESET_GE1_MAC,
408 struct platform_device ath79_eth1_device = {
411 .resource = ath79_eth1_resources,
412 .num_resources = ARRAY_SIZE(ath79_eth1_resources),
414 .platform_data = &ath79_eth1_data,
418 struct ag71xx_switch_platform_data ath79_switch_data;
420 #define AR71XX_PLL_VAL_1000 0x00110000
421 #define AR71XX_PLL_VAL_100 0x00001099
422 #define AR71XX_PLL_VAL_10 0x00991099
424 #define AR724X_PLL_VAL_1000 0x00110000
425 #define AR724X_PLL_VAL_100 0x00001099
426 #define AR724X_PLL_VAL_10 0x00991099
428 #define AR7242_PLL_VAL_1000 0x16000000
429 #define AR7242_PLL_VAL_100 0x00000101
430 #define AR7242_PLL_VAL_10 0x00001616
432 #define AR913X_PLL_VAL_1000 0x1a000000
433 #define AR913X_PLL_VAL_100 0x13000a44
434 #define AR913X_PLL_VAL_10 0x00441099
436 #define AR933X_PLL_VAL_1000 0x00110000
437 #define AR933X_PLL_VAL_100 0x00001099
438 #define AR933X_PLL_VAL_10 0x00991099
440 #define AR934X_PLL_VAL_1000 0x16000000
441 #define AR934X_PLL_VAL_100 0x00000101
442 #define AR934X_PLL_VAL_10 0x00001616
444 static void __init ath79_init_eth_pll_data(unsigned int id)
446 struct ath79_eth_pll_data *pll_data;
447 u32 pll_10, pll_100, pll_1000;
451 pll_data = &ath79_eth0_pll_data;
454 pll_data = &ath79_eth1_pll_data;
461 case ATH79_SOC_AR7130:
462 case ATH79_SOC_AR7141:
463 case ATH79_SOC_AR7161:
464 pll_10 = AR71XX_PLL_VAL_10;
465 pll_100 = AR71XX_PLL_VAL_100;
466 pll_1000 = AR71XX_PLL_VAL_1000;
469 case ATH79_SOC_AR7240:
470 case ATH79_SOC_AR7241:
471 pll_10 = AR724X_PLL_VAL_10;
472 pll_100 = AR724X_PLL_VAL_100;
473 pll_1000 = AR724X_PLL_VAL_1000;
476 case ATH79_SOC_AR7242:
477 pll_10 = AR7242_PLL_VAL_10;
478 pll_100 = AR7242_PLL_VAL_100;
479 pll_1000 = AR7242_PLL_VAL_1000;
482 case ATH79_SOC_AR9130:
483 case ATH79_SOC_AR9132:
484 pll_10 = AR913X_PLL_VAL_10;
485 pll_100 = AR913X_PLL_VAL_100;
486 pll_1000 = AR913X_PLL_VAL_1000;
489 case ATH79_SOC_AR9330:
490 case ATH79_SOC_AR9331:
491 pll_10 = AR933X_PLL_VAL_10;
492 pll_100 = AR933X_PLL_VAL_100;
493 pll_1000 = AR933X_PLL_VAL_1000;
496 case ATH79_SOC_AR9341:
497 case ATH79_SOC_AR9342:
498 case ATH79_SOC_AR9344:
499 pll_10 = AR934X_PLL_VAL_10;
500 pll_100 = AR934X_PLL_VAL_100;
501 pll_1000 = AR934X_PLL_VAL_1000;
508 if (!pll_data->pll_10)
509 pll_data->pll_10 = pll_10;
511 if (!pll_data->pll_100)
512 pll_data->pll_100 = pll_100;
514 if (!pll_data->pll_1000)
515 pll_data->pll_1000 = pll_1000;
518 static int __init ath79_setup_phy_if_mode(unsigned int id,
519 struct ag71xx_platform_data *pdata)
526 case ATH79_SOC_AR7130:
527 case ATH79_SOC_AR7141:
528 case ATH79_SOC_AR7161:
529 case ATH79_SOC_AR9130:
530 case ATH79_SOC_AR9132:
531 switch (pdata->phy_if_mode) {
532 case PHY_INTERFACE_MODE_MII:
533 mii_if = AR71XX_MII0_CTRL_IF_MII;
535 case PHY_INTERFACE_MODE_GMII:
536 mii_if = AR71XX_MII0_CTRL_IF_GMII;
538 case PHY_INTERFACE_MODE_RGMII:
539 mii_if = AR71XX_MII0_CTRL_IF_RGMII;
541 case PHY_INTERFACE_MODE_RMII:
542 mii_if = AR71XX_MII0_CTRL_IF_RMII;
547 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII0_CTRL, mii_if);
550 case ATH79_SOC_AR7240:
551 case ATH79_SOC_AR7241:
552 case ATH79_SOC_AR9330:
553 case ATH79_SOC_AR9331:
554 pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
557 case ATH79_SOC_AR7242:
560 case ATH79_SOC_AR9341:
561 case ATH79_SOC_AR9342:
562 case ATH79_SOC_AR9344:
563 switch (pdata->phy_if_mode) {
564 case PHY_INTERFACE_MODE_MII:
565 case PHY_INTERFACE_MODE_GMII:
566 case PHY_INTERFACE_MODE_RGMII:
567 case PHY_INTERFACE_MODE_RMII:
580 case ATH79_SOC_AR7130:
581 case ATH79_SOC_AR7141:
582 case ATH79_SOC_AR7161:
583 case ATH79_SOC_AR9130:
584 case ATH79_SOC_AR9132:
585 switch (pdata->phy_if_mode) {
586 case PHY_INTERFACE_MODE_RMII:
587 mii_if = AR71XX_MII1_CTRL_IF_RMII;
589 case PHY_INTERFACE_MODE_RGMII:
590 mii_if = AR71XX_MII1_CTRL_IF_RGMII;
595 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII1_CTRL, mii_if);
598 case ATH79_SOC_AR7240:
599 case ATH79_SOC_AR7241:
600 case ATH79_SOC_AR9330:
601 case ATH79_SOC_AR9331:
602 pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
605 case ATH79_SOC_AR7242:
608 case ATH79_SOC_AR9341:
609 case ATH79_SOC_AR9342:
610 case ATH79_SOC_AR9344:
611 switch (pdata->phy_if_mode) {
612 case PHY_INTERFACE_MODE_MII:
613 case PHY_INTERFACE_MODE_GMII:
629 static int ath79_eth_instance __initdata;
630 void __init ath79_register_eth(unsigned int id)
632 struct platform_device *pdev;
633 struct ag71xx_platform_data *pdata;
637 printk(KERN_ERR "ar71xx: invalid ethernet id %d\n", id);
641 ath79_init_eth_pll_data(id);
644 pdev = &ath79_eth0_device;
646 pdev = &ath79_eth1_device;
648 pdata = pdev->dev.platform_data;
650 err = ath79_setup_phy_if_mode(id, pdata);
653 "ar71xx: invalid PHY interface mode for GE%u\n", id);
658 case ATH79_SOC_AR7130:
660 pdata->ddr_flush = ath79_ddr_flush_ge0;
661 pdata->set_speed = ath79_set_speed_ge0;
663 pdata->ddr_flush = ath79_ddr_flush_ge1;
664 pdata->set_speed = ath79_set_speed_ge1;
668 case ATH79_SOC_AR7141:
669 case ATH79_SOC_AR7161:
671 pdata->ddr_flush = ath79_ddr_flush_ge0;
672 pdata->set_speed = ath79_set_speed_ge0;
674 pdata->ddr_flush = ath79_ddr_flush_ge1;
675 pdata->set_speed = ath79_set_speed_ge1;
680 case ATH79_SOC_AR7242:
682 pdata->reset_bit |= AR724X_RESET_GE0_MDIO |
683 AR71XX_RESET_GE0_PHY;
684 pdata->ddr_flush = ar724x_ddr_flush_ge0;
685 pdata->set_speed = ar7242_set_speed_ge0;
687 pdata->reset_bit |= AR724X_RESET_GE1_MDIO |
688 AR71XX_RESET_GE1_PHY;
689 pdata->ddr_flush = ar724x_ddr_flush_ge1;
690 pdata->set_speed = ath79_set_speed_dummy;
693 pdata->is_ar724x = 1;
695 if (!pdata->fifo_cfg1)
696 pdata->fifo_cfg1 = 0x0010ffff;
697 if (!pdata->fifo_cfg2)
698 pdata->fifo_cfg2 = 0x015500aa;
699 if (!pdata->fifo_cfg3)
700 pdata->fifo_cfg3 = 0x01f00140;
703 case ATH79_SOC_AR7241:
705 pdata->reset_bit |= AR724X_RESET_GE0_MDIO;
707 pdata->reset_bit |= AR724X_RESET_GE1_MDIO;
709 case ATH79_SOC_AR7240:
711 pdata->reset_bit |= AR71XX_RESET_GE0_PHY;
712 pdata->ddr_flush = ar724x_ddr_flush_ge0;
713 pdata->set_speed = ath79_set_speed_dummy;
715 pdata->phy_mask = BIT(4);
717 pdata->reset_bit |= AR71XX_RESET_GE1_PHY;
718 pdata->ddr_flush = ar724x_ddr_flush_ge1;
719 pdata->set_speed = ath79_set_speed_dummy;
721 pdata->speed = SPEED_1000;
722 pdata->duplex = DUPLEX_FULL;
723 pdata->switch_data = &ath79_switch_data;
725 ath79_switch_data.phy_poll_mask |= BIT(4);
728 pdata->is_ar724x = 1;
729 if (ath79_soc == ATH79_SOC_AR7240)
730 pdata->is_ar7240 = 1;
732 if (!pdata->fifo_cfg1)
733 pdata->fifo_cfg1 = 0x0010ffff;
734 if (!pdata->fifo_cfg2)
735 pdata->fifo_cfg2 = 0x015500aa;
736 if (!pdata->fifo_cfg3)
737 pdata->fifo_cfg3 = 0x01f00140;
740 case ATH79_SOC_AR9130:
742 pdata->ddr_flush = ar91xx_ddr_flush_ge0;
743 pdata->set_speed = ar91xx_set_speed_ge0;
745 pdata->ddr_flush = ar91xx_ddr_flush_ge1;
746 pdata->set_speed = ar91xx_set_speed_ge1;
748 pdata->is_ar91xx = 1;
751 case ATH79_SOC_AR9132:
753 pdata->ddr_flush = ar91xx_ddr_flush_ge0;
754 pdata->set_speed = ar91xx_set_speed_ge0;
756 pdata->ddr_flush = ar91xx_ddr_flush_ge1;
757 pdata->set_speed = ar91xx_set_speed_ge1;
759 pdata->is_ar91xx = 1;
763 case ATH79_SOC_AR9330:
764 case ATH79_SOC_AR9331:
766 pdata->reset_bit = AR933X_RESET_GE0_MAC |
767 AR933X_RESET_GE0_MDIO;
768 pdata->ddr_flush = ar933x_ddr_flush_ge0;
769 pdata->set_speed = ath79_set_speed_dummy;
771 pdata->phy_mask = BIT(4);
773 pdata->reset_bit = AR933X_RESET_GE1_MAC |
774 AR933X_RESET_GE1_MDIO;
775 pdata->ddr_flush = ar933x_ddr_flush_ge1;
776 pdata->set_speed = ath79_set_speed_dummy;
778 pdata->speed = SPEED_1000;
779 pdata->duplex = DUPLEX_FULL;
780 pdata->switch_data = &ath79_switch_data;
782 ath79_switch_data.phy_poll_mask |= BIT(4);
786 pdata->is_ar724x = 1;
788 if (!pdata->fifo_cfg1)
789 pdata->fifo_cfg1 = 0x0010ffff;
790 if (!pdata->fifo_cfg2)
791 pdata->fifo_cfg2 = 0x015500aa;
792 if (!pdata->fifo_cfg3)
793 pdata->fifo_cfg3 = 0x01f00140;
796 case ATH79_SOC_AR9341:
797 case ATH79_SOC_AR9342:
798 case ATH79_SOC_AR9344:
800 pdata->reset_bit = AR934X_RESET_GE0_MAC |
801 AR934X_RESET_GE0_MDIO;
802 pdata->set_speed = ar934x_set_speed_ge0;
804 pdata->reset_bit = AR934X_RESET_GE1_MAC |
805 AR934X_RESET_GE1_MDIO;
806 pdata->set_speed = ath79_set_speed_dummy;
808 pdata->switch_data = &ath79_switch_data;
810 /* reset the built-in switch */
811 ath79_device_reset_set(AR934X_RESET_ETH_SWITCH);
812 ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH);
815 pdata->ddr_flush = ath79_ddr_no_flush;
817 pdata->is_ar724x = 1;
819 if (!pdata->fifo_cfg1)
820 pdata->fifo_cfg1 = 0x0010ffff;
821 if (!pdata->fifo_cfg2)
822 pdata->fifo_cfg2 = 0x015500aa;
823 if (!pdata->fifo_cfg3)
824 pdata->fifo_cfg3 = 0x01f00140;
831 switch (pdata->phy_if_mode) {
832 case PHY_INTERFACE_MODE_GMII:
833 case PHY_INTERFACE_MODE_RGMII:
834 if (!pdata->has_gbit) {
835 printk(KERN_ERR "ar71xx: no gbit available on eth%d\n",
844 if (!is_valid_ether_addr(pdata->mac_addr)) {
845 random_ether_addr(pdata->mac_addr);
847 "ar71xx: using random MAC address for eth%d\n",
851 if (pdata->mii_bus_dev == NULL) {
853 case ATH79_SOC_AR9341:
854 case ATH79_SOC_AR9342:
855 case ATH79_SOC_AR9344:
857 pdata->mii_bus_dev = &ath79_mdio0_device.dev;
859 pdata->mii_bus_dev = &ath79_mdio1_device.dev;
862 case ATH79_SOC_AR7241:
863 case ATH79_SOC_AR9330:
864 case ATH79_SOC_AR9331:
865 pdata->mii_bus_dev = &ath79_mdio1_device.dev;
869 pdata->mii_bus_dev = &ath79_mdio0_device.dev;
874 /* Reset the device */
875 ath79_device_reset_set(pdata->reset_bit);
878 ath79_device_reset_clear(pdata->reset_bit);
881 platform_device_register(pdev);
882 ath79_eth_instance++;
885 void __init ath79_set_mac_base(unsigned char *mac)
887 memcpy(ath79_mac_base, mac, ETH_ALEN);
890 void __init ath79_parse_mac_addr(char *mac_str)
895 t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
896 &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
899 t = sscanf(mac_str, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
900 &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
903 ath79_set_mac_base(tmp);
905 printk(KERN_DEBUG "ar71xx: failed to parse mac address "
906 "\"%s\"\n", mac_str);
909 static int __init ath79_ethaddr_setup(char *str)
911 ath79_parse_mac_addr(str);
914 __setup("ethaddr=", ath79_ethaddr_setup);
916 static int __init ath79_kmac_setup(char *str)
918 ath79_parse_mac_addr(str);
921 __setup("kmac=", ath79_kmac_setup);
923 void __init ath79_init_mac(unsigned char *dst, const unsigned char *src,
928 if (!is_valid_ether_addr(src)) {
929 memset(dst, '\0', ETH_ALEN);
933 t = (((u32) src[3]) << 16) + (((u32) src[4]) << 8) + ((u32) src[5]);
939 dst[3] = (t >> 16) & 0xff;
940 dst[4] = (t >> 8) & 0xff;
944 void __init ath79_init_local_mac(unsigned char *dst, const unsigned char *src)
948 if (!is_valid_ether_addr(src)) {
949 memset(dst, '\0', ETH_ALEN);
953 for (i = 0; i < ETH_ALEN; i++)