2 * Atheros AR71xx SoC platform devices
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
8 * Parts of this file are based on Atheros 2.6.15 BSP
9 * Parts of this file are based on Atheros 2.6.31 BSP
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/etherdevice.h>
20 #include <linux/platform_device.h>
21 #include <linux/serial_8250.h>
22 #include <linux/clk.h>
23 #include <linux/sizes.h>
25 #include <asm/mach-ath79/ath79.h>
26 #include <asm/mach-ath79/ar71xx_regs.h>
27 #include <asm/mach-ath79/irq.h>
32 unsigned char ath79_mac_base[ETH_ALEN] __initdata;
34 static struct resource ath79_mdio0_resources[] = {
37 .flags = IORESOURCE_MEM,
38 .start = AR71XX_GE0_BASE,
39 .end = AR71XX_GE0_BASE + 0x200 - 1,
43 struct ag71xx_mdio_platform_data ath79_mdio0_data;
45 struct platform_device ath79_mdio0_device = {
46 .name = "ag71xx-mdio",
48 .resource = ath79_mdio0_resources,
49 .num_resources = ARRAY_SIZE(ath79_mdio0_resources),
51 .platform_data = &ath79_mdio0_data,
55 static struct resource ath79_mdio1_resources[] = {
58 .flags = IORESOURCE_MEM,
59 .start = AR71XX_GE1_BASE,
60 .end = AR71XX_GE1_BASE + 0x200 - 1,
64 struct ag71xx_mdio_platform_data ath79_mdio1_data;
66 struct platform_device ath79_mdio1_device = {
67 .name = "ag71xx-mdio",
69 .resource = ath79_mdio1_resources,
70 .num_resources = ARRAY_SIZE(ath79_mdio1_resources),
72 .platform_data = &ath79_mdio1_data,
76 static void ath79_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift)
81 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
83 t = __raw_readl(base + cfg_reg);
86 __raw_writel(t, base + cfg_reg);
89 __raw_writel(pll_val, base + pll_reg);
92 __raw_writel(t, base + cfg_reg);
96 __raw_writel(t, base + cfg_reg);
99 printk(KERN_DEBUG "ar71xx: pll_reg %#x: %#x\n",
100 (unsigned int)(base + pll_reg), __raw_readl(base + pll_reg));
105 static void __init ath79_mii_ctrl_set_if(unsigned int reg,
111 base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
113 t = __raw_readl(base + reg);
114 t &= ~(AR71XX_MII_CTRL_IF_MASK);
115 t |= (mii_if & AR71XX_MII_CTRL_IF_MASK);
116 __raw_writel(t, base + reg);
121 static void ath79_mii_ctrl_set_speed(unsigned int reg, unsigned int speed)
124 unsigned int mii_speed;
129 mii_speed = AR71XX_MII_CTRL_SPEED_10;
132 mii_speed = AR71XX_MII_CTRL_SPEED_100;
135 mii_speed = AR71XX_MII_CTRL_SPEED_1000;
141 base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
143 t = __raw_readl(base + reg);
144 t &= ~(AR71XX_MII_CTRL_SPEED_MASK << AR71XX_MII_CTRL_SPEED_SHIFT);
145 t |= mii_speed << AR71XX_MII_CTRL_SPEED_SHIFT;
146 __raw_writel(t, base + reg);
151 static unsigned long ar934x_get_mdio_ref_clock(void)
157 base = ioremap(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
160 t = __raw_readl(base + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
161 if (t & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL) {
162 ret = 100 * 1000 * 1000;
166 clk = clk_get(NULL, "ref");
168 ret = clk_get_rate(clk);
176 void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
178 struct platform_device *mdio_dev;
179 struct ag71xx_mdio_platform_data *mdio_data;
182 if (ath79_soc == ATH79_SOC_AR9341 ||
183 ath79_soc == ATH79_SOC_AR9342 ||
184 ath79_soc == ATH79_SOC_AR9344 ||
185 ath79_soc == ATH79_SOC_QCA9556 ||
186 ath79_soc == ATH79_SOC_QCA9558)
192 printk(KERN_ERR "ar71xx: invalid MDIO id %u\n", id);
197 case ATH79_SOC_AR7241:
198 case ATH79_SOC_AR9330:
199 case ATH79_SOC_AR9331:
200 mdio_dev = &ath79_mdio1_device;
201 mdio_data = &ath79_mdio1_data;
204 case ATH79_SOC_AR9341:
205 case ATH79_SOC_AR9342:
206 case ATH79_SOC_AR9344:
207 case ATH79_SOC_QCA9556:
208 case ATH79_SOC_QCA9558:
210 mdio_dev = &ath79_mdio0_device;
211 mdio_data = &ath79_mdio0_data;
213 mdio_dev = &ath79_mdio1_device;
214 mdio_data = &ath79_mdio1_data;
218 case ATH79_SOC_AR7242:
219 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG,
220 AR7242_PLL_REG_ETH0_INT_CLOCK, 0x62000000,
221 AR71XX_ETH0_PLL_SHIFT);
224 mdio_dev = &ath79_mdio0_device;
225 mdio_data = &ath79_mdio0_data;
229 mdio_data->phy_mask = phy_mask;
232 case ATH79_SOC_AR7240:
233 mdio_data->is_ar7240 = 1;
235 case ATH79_SOC_AR7241:
236 mdio_data->builtin_switch = 1;
239 case ATH79_SOC_AR9330:
240 mdio_data->is_ar9330 = 1;
242 case ATH79_SOC_AR9331:
243 mdio_data->builtin_switch = 1;
246 case ATH79_SOC_AR9341:
247 case ATH79_SOC_AR9342:
248 case ATH79_SOC_AR9344:
250 mdio_data->builtin_switch = 1;
251 mdio_data->ref_clock = ar934x_get_mdio_ref_clock();
252 mdio_data->mdio_clock = 6250000;
254 mdio_data->is_ar934x = 1;
257 case ATH79_SOC_QCA9558:
259 mdio_data->builtin_switch = 1;
260 mdio_data->is_ar934x = 1;
263 case ATH79_SOC_QCA9556:
264 mdio_data->is_ar934x = 1;
271 platform_device_register(mdio_dev);
274 struct ath79_eth_pll_data ath79_eth0_pll_data;
275 struct ath79_eth_pll_data ath79_eth1_pll_data;
277 static u32 ath79_get_eth_pll(unsigned int mac, int speed)
279 struct ath79_eth_pll_data *pll_data;
284 pll_data = &ath79_eth0_pll_data;
287 pll_data = &ath79_eth1_pll_data;
295 pll_val = pll_data->pll_10;
298 pll_val = pll_data->pll_100;
301 pll_val = pll_data->pll_1000;
310 static void ath79_set_speed_ge0(int speed)
312 u32 val = ath79_get_eth_pll(0, speed);
314 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK,
315 val, AR71XX_ETH0_PLL_SHIFT);
316 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
319 static void ath79_set_speed_ge1(int speed)
321 u32 val = ath79_get_eth_pll(1, speed);
323 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK,
324 val, AR71XX_ETH1_PLL_SHIFT);
325 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
328 static void ar7242_set_speed_ge0(int speed)
330 u32 val = ath79_get_eth_pll(0, speed);
333 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
334 __raw_writel(val, base + AR7242_PLL_REG_ETH0_INT_CLOCK);
338 static void ar91xx_set_speed_ge0(int speed)
340 u32 val = ath79_get_eth_pll(0, speed);
342 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH0_INT_CLOCK,
343 val, AR913X_ETH0_PLL_SHIFT);
344 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
347 static void ar91xx_set_speed_ge1(int speed)
349 u32 val = ath79_get_eth_pll(1, speed);
351 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH1_INT_CLOCK,
352 val, AR913X_ETH1_PLL_SHIFT);
353 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
356 static void ar934x_set_speed_ge0(int speed)
359 u32 val = ath79_get_eth_pll(0, speed);
361 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
362 __raw_writel(val, base + AR934X_PLL_ETH_XMII_CONTROL_REG);
366 static void qca955x_set_speed_xmii(int speed)
369 u32 val = ath79_get_eth_pll(0, speed);
371 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
372 __raw_writel(val, base + QCA955X_PLL_ETH_XMII_CONTROL_REG);
376 static void qca955x_set_speed_sgmii(int speed)
379 u32 val = ath79_get_eth_pll(1, speed);
381 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
382 __raw_writel(val, base + QCA955X_PLL_ETH_SGMII_CONTROL_REG);
386 static void ath79_set_speed_dummy(int speed)
390 static void ath79_ddr_no_flush(void)
394 static void ath79_ddr_flush_ge0(void)
396 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE0);
399 static void ath79_ddr_flush_ge1(void)
401 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE1);
404 static void ar724x_ddr_flush_ge0(void)
406 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE0);
409 static void ar724x_ddr_flush_ge1(void)
411 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE1);
414 static void ar91xx_ddr_flush_ge0(void)
416 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE0);
419 static void ar91xx_ddr_flush_ge1(void)
421 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE1);
424 static void ar933x_ddr_flush_ge0(void)
426 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE0);
429 static void ar933x_ddr_flush_ge1(void)
431 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE1);
434 static struct resource ath79_eth0_resources[] = {
437 .flags = IORESOURCE_MEM,
438 .start = AR71XX_GE0_BASE,
439 .end = AR71XX_GE0_BASE + 0x200 - 1,
442 .flags = IORESOURCE_IRQ,
443 .start = ATH79_CPU_IRQ(4),
444 .end = ATH79_CPU_IRQ(4),
448 struct ag71xx_platform_data ath79_eth0_data = {
449 .reset_bit = AR71XX_RESET_GE0_MAC,
452 struct platform_device ath79_eth0_device = {
455 .resource = ath79_eth0_resources,
456 .num_resources = ARRAY_SIZE(ath79_eth0_resources),
458 .platform_data = &ath79_eth0_data,
462 static struct resource ath79_eth1_resources[] = {
465 .flags = IORESOURCE_MEM,
466 .start = AR71XX_GE1_BASE,
467 .end = AR71XX_GE1_BASE + 0x200 - 1,
470 .flags = IORESOURCE_IRQ,
471 .start = ATH79_CPU_IRQ(5),
472 .end = ATH79_CPU_IRQ(5),
476 struct ag71xx_platform_data ath79_eth1_data = {
477 .reset_bit = AR71XX_RESET_GE1_MAC,
480 struct platform_device ath79_eth1_device = {
483 .resource = ath79_eth1_resources,
484 .num_resources = ARRAY_SIZE(ath79_eth1_resources),
486 .platform_data = &ath79_eth1_data,
490 struct ag71xx_switch_platform_data ath79_switch_data;
492 #define AR71XX_PLL_VAL_1000 0x00110000
493 #define AR71XX_PLL_VAL_100 0x00001099
494 #define AR71XX_PLL_VAL_10 0x00991099
496 #define AR724X_PLL_VAL_1000 0x00110000
497 #define AR724X_PLL_VAL_100 0x00001099
498 #define AR724X_PLL_VAL_10 0x00991099
500 #define AR7242_PLL_VAL_1000 0x16000000
501 #define AR7242_PLL_VAL_100 0x00000101
502 #define AR7242_PLL_VAL_10 0x00001616
504 #define AR913X_PLL_VAL_1000 0x1a000000
505 #define AR913X_PLL_VAL_100 0x13000a44
506 #define AR913X_PLL_VAL_10 0x00441099
508 #define AR933X_PLL_VAL_1000 0x00110000
509 #define AR933X_PLL_VAL_100 0x00001099
510 #define AR933X_PLL_VAL_10 0x00991099
512 #define AR934X_PLL_VAL_1000 0x16000000
513 #define AR934X_PLL_VAL_100 0x00000101
514 #define AR934X_PLL_VAL_10 0x00001616
516 static void __init ath79_init_eth_pll_data(unsigned int id)
518 struct ath79_eth_pll_data *pll_data;
519 u32 pll_10, pll_100, pll_1000;
523 pll_data = &ath79_eth0_pll_data;
526 pll_data = &ath79_eth1_pll_data;
533 case ATH79_SOC_AR7130:
534 case ATH79_SOC_AR7141:
535 case ATH79_SOC_AR7161:
536 pll_10 = AR71XX_PLL_VAL_10;
537 pll_100 = AR71XX_PLL_VAL_100;
538 pll_1000 = AR71XX_PLL_VAL_1000;
541 case ATH79_SOC_AR7240:
542 case ATH79_SOC_AR7241:
543 pll_10 = AR724X_PLL_VAL_10;
544 pll_100 = AR724X_PLL_VAL_100;
545 pll_1000 = AR724X_PLL_VAL_1000;
548 case ATH79_SOC_AR7242:
549 pll_10 = AR7242_PLL_VAL_10;
550 pll_100 = AR7242_PLL_VAL_100;
551 pll_1000 = AR7242_PLL_VAL_1000;
554 case ATH79_SOC_AR9130:
555 case ATH79_SOC_AR9132:
556 pll_10 = AR913X_PLL_VAL_10;
557 pll_100 = AR913X_PLL_VAL_100;
558 pll_1000 = AR913X_PLL_VAL_1000;
561 case ATH79_SOC_AR9330:
562 case ATH79_SOC_AR9331:
563 pll_10 = AR933X_PLL_VAL_10;
564 pll_100 = AR933X_PLL_VAL_100;
565 pll_1000 = AR933X_PLL_VAL_1000;
568 case ATH79_SOC_AR9341:
569 case ATH79_SOC_AR9342:
570 case ATH79_SOC_AR9344:
571 case ATH79_SOC_QCA9556:
572 case ATH79_SOC_QCA9558:
573 pll_10 = AR934X_PLL_VAL_10;
574 pll_100 = AR934X_PLL_VAL_100;
575 pll_1000 = AR934X_PLL_VAL_1000;
582 if (!pll_data->pll_10)
583 pll_data->pll_10 = pll_10;
585 if (!pll_data->pll_100)
586 pll_data->pll_100 = pll_100;
588 if (!pll_data->pll_1000)
589 pll_data->pll_1000 = pll_1000;
592 static int __init ath79_setup_phy_if_mode(unsigned int id,
593 struct ag71xx_platform_data *pdata)
600 case ATH79_SOC_AR7130:
601 case ATH79_SOC_AR7141:
602 case ATH79_SOC_AR7161:
603 case ATH79_SOC_AR9130:
604 case ATH79_SOC_AR9132:
605 switch (pdata->phy_if_mode) {
606 case PHY_INTERFACE_MODE_MII:
607 mii_if = AR71XX_MII0_CTRL_IF_MII;
609 case PHY_INTERFACE_MODE_GMII:
610 mii_if = AR71XX_MII0_CTRL_IF_GMII;
612 case PHY_INTERFACE_MODE_RGMII:
613 mii_if = AR71XX_MII0_CTRL_IF_RGMII;
615 case PHY_INTERFACE_MODE_RMII:
616 mii_if = AR71XX_MII0_CTRL_IF_RMII;
621 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII0_CTRL, mii_if);
624 case ATH79_SOC_AR7240:
625 case ATH79_SOC_AR7241:
626 case ATH79_SOC_AR9330:
627 case ATH79_SOC_AR9331:
628 pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
631 case ATH79_SOC_AR7242:
634 case ATH79_SOC_AR9341:
635 case ATH79_SOC_AR9342:
636 case ATH79_SOC_AR9344:
637 switch (pdata->phy_if_mode) {
638 case PHY_INTERFACE_MODE_MII:
639 case PHY_INTERFACE_MODE_GMII:
640 case PHY_INTERFACE_MODE_RGMII:
641 case PHY_INTERFACE_MODE_RMII:
648 case ATH79_SOC_QCA9556:
649 case ATH79_SOC_QCA9558:
650 switch (pdata->phy_if_mode) {
651 case PHY_INTERFACE_MODE_MII:
652 case PHY_INTERFACE_MODE_RGMII:
653 case PHY_INTERFACE_MODE_SGMII:
666 case ATH79_SOC_AR7130:
667 case ATH79_SOC_AR7141:
668 case ATH79_SOC_AR7161:
669 case ATH79_SOC_AR9130:
670 case ATH79_SOC_AR9132:
671 switch (pdata->phy_if_mode) {
672 case PHY_INTERFACE_MODE_RMII:
673 mii_if = AR71XX_MII1_CTRL_IF_RMII;
675 case PHY_INTERFACE_MODE_RGMII:
676 mii_if = AR71XX_MII1_CTRL_IF_RGMII;
681 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII1_CTRL, mii_if);
684 case ATH79_SOC_AR7240:
685 case ATH79_SOC_AR7241:
686 case ATH79_SOC_AR9330:
687 case ATH79_SOC_AR9331:
688 pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
691 case ATH79_SOC_AR7242:
694 case ATH79_SOC_AR9341:
695 case ATH79_SOC_AR9342:
696 case ATH79_SOC_AR9344:
697 switch (pdata->phy_if_mode) {
698 case PHY_INTERFACE_MODE_MII:
699 case PHY_INTERFACE_MODE_GMII:
706 case ATH79_SOC_QCA9556:
707 case ATH79_SOC_QCA9558:
708 switch (pdata->phy_if_mode) {
709 case PHY_INTERFACE_MODE_MII:
710 case PHY_INTERFACE_MODE_RGMII:
711 case PHY_INTERFACE_MODE_SGMII:
727 void __init ath79_setup_ar933x_phy4_switch(bool mac, bool mdio)
732 base = ioremap(AR933X_GMAC_BASE, AR933X_GMAC_SIZE);
734 t = __raw_readl(base + AR933X_GMAC_REG_ETH_CFG);
735 t &= ~(AR933X_ETH_CFG_SW_PHY_SWAP | AR933X_ETH_CFG_SW_PHY_ADDR_SWAP);
737 t |= AR933X_ETH_CFG_SW_PHY_SWAP;
739 t |= AR933X_ETH_CFG_SW_PHY_ADDR_SWAP;
740 __raw_writel(t, base + AR933X_GMAC_REG_ETH_CFG);
745 void __init ath79_setup_ar934x_eth_cfg(u32 mask)
750 base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
752 t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
754 t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 |
755 AR934X_ETH_CFG_MII_GMAC0 |
756 AR934X_ETH_CFG_GMII_GMAC0 |
757 AR934X_ETH_CFG_SW_ONLY_MODE |
758 AR934X_ETH_CFG_SW_PHY_SWAP);
762 __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
764 __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
769 static int ath79_eth_instance __initdata;
770 void __init ath79_register_eth(unsigned int id)
772 struct platform_device *pdev;
773 struct ag71xx_platform_data *pdata;
777 printk(KERN_ERR "ar71xx: invalid ethernet id %d\n", id);
781 ath79_init_eth_pll_data(id);
784 pdev = &ath79_eth0_device;
786 pdev = &ath79_eth1_device;
788 pdata = pdev->dev.platform_data;
790 pdata->max_frame_len = 1540;
791 pdata->desc_pktlen_mask = 0xfff;
793 err = ath79_setup_phy_if_mode(id, pdata);
796 "ar71xx: invalid PHY interface mode for GE%u\n", id);
801 case ATH79_SOC_AR7130:
803 pdata->ddr_flush = ath79_ddr_flush_ge0;
804 pdata->set_speed = ath79_set_speed_ge0;
806 pdata->ddr_flush = ath79_ddr_flush_ge1;
807 pdata->set_speed = ath79_set_speed_ge1;
811 case ATH79_SOC_AR7141:
812 case ATH79_SOC_AR7161:
814 pdata->ddr_flush = ath79_ddr_flush_ge0;
815 pdata->set_speed = ath79_set_speed_ge0;
817 pdata->ddr_flush = ath79_ddr_flush_ge1;
818 pdata->set_speed = ath79_set_speed_ge1;
823 case ATH79_SOC_AR7242:
825 pdata->reset_bit |= AR724X_RESET_GE0_MDIO |
826 AR71XX_RESET_GE0_PHY;
827 pdata->ddr_flush = ar724x_ddr_flush_ge0;
828 pdata->set_speed = ar7242_set_speed_ge0;
830 pdata->reset_bit |= AR724X_RESET_GE1_MDIO |
831 AR71XX_RESET_GE1_PHY;
832 pdata->ddr_flush = ar724x_ddr_flush_ge1;
833 pdata->set_speed = ath79_set_speed_dummy;
836 pdata->is_ar724x = 1;
838 if (!pdata->fifo_cfg1)
839 pdata->fifo_cfg1 = 0x0010ffff;
840 if (!pdata->fifo_cfg2)
841 pdata->fifo_cfg2 = 0x015500aa;
842 if (!pdata->fifo_cfg3)
843 pdata->fifo_cfg3 = 0x01f00140;
846 case ATH79_SOC_AR7241:
848 pdata->reset_bit |= AR724X_RESET_GE0_MDIO;
850 pdata->reset_bit |= AR724X_RESET_GE1_MDIO;
852 case ATH79_SOC_AR7240:
854 pdata->reset_bit |= AR71XX_RESET_GE0_PHY;
855 pdata->ddr_flush = ar724x_ddr_flush_ge0;
856 pdata->set_speed = ath79_set_speed_dummy;
858 pdata->phy_mask = BIT(4);
860 pdata->reset_bit |= AR71XX_RESET_GE1_PHY;
861 pdata->ddr_flush = ar724x_ddr_flush_ge1;
862 pdata->set_speed = ath79_set_speed_dummy;
864 pdata->speed = SPEED_1000;
865 pdata->duplex = DUPLEX_FULL;
866 pdata->switch_data = &ath79_switch_data;
868 ath79_switch_data.phy_poll_mask |= BIT(4);
871 pdata->is_ar724x = 1;
872 if (ath79_soc == ATH79_SOC_AR7240)
873 pdata->is_ar7240 = 1;
875 if (!pdata->fifo_cfg1)
876 pdata->fifo_cfg1 = 0x0010ffff;
877 if (!pdata->fifo_cfg2)
878 pdata->fifo_cfg2 = 0x015500aa;
879 if (!pdata->fifo_cfg3)
880 pdata->fifo_cfg3 = 0x01f00140;
883 case ATH79_SOC_AR9130:
885 pdata->ddr_flush = ar91xx_ddr_flush_ge0;
886 pdata->set_speed = ar91xx_set_speed_ge0;
888 pdata->ddr_flush = ar91xx_ddr_flush_ge1;
889 pdata->set_speed = ar91xx_set_speed_ge1;
891 pdata->is_ar91xx = 1;
894 case ATH79_SOC_AR9132:
896 pdata->ddr_flush = ar91xx_ddr_flush_ge0;
897 pdata->set_speed = ar91xx_set_speed_ge0;
899 pdata->ddr_flush = ar91xx_ddr_flush_ge1;
900 pdata->set_speed = ar91xx_set_speed_ge1;
902 pdata->is_ar91xx = 1;
906 case ATH79_SOC_AR9330:
907 case ATH79_SOC_AR9331:
909 pdata->reset_bit = AR933X_RESET_GE0_MAC |
910 AR933X_RESET_GE0_MDIO;
911 pdata->ddr_flush = ar933x_ddr_flush_ge0;
912 pdata->set_speed = ath79_set_speed_dummy;
914 pdata->phy_mask = BIT(4);
916 pdata->reset_bit = AR933X_RESET_GE1_MAC |
917 AR933X_RESET_GE1_MDIO;
918 pdata->ddr_flush = ar933x_ddr_flush_ge1;
919 pdata->set_speed = ath79_set_speed_dummy;
921 pdata->speed = SPEED_1000;
922 pdata->duplex = DUPLEX_FULL;
923 pdata->switch_data = &ath79_switch_data;
925 ath79_switch_data.phy_poll_mask |= BIT(4);
929 pdata->is_ar724x = 1;
931 if (!pdata->fifo_cfg1)
932 pdata->fifo_cfg1 = 0x0010ffff;
933 if (!pdata->fifo_cfg2)
934 pdata->fifo_cfg2 = 0x015500aa;
935 if (!pdata->fifo_cfg3)
936 pdata->fifo_cfg3 = 0x01f00140;
939 case ATH79_SOC_AR9341:
940 case ATH79_SOC_AR9342:
941 case ATH79_SOC_AR9344:
943 pdata->reset_bit = AR934X_RESET_GE0_MAC |
944 AR934X_RESET_GE0_MDIO;
945 pdata->set_speed = ar934x_set_speed_ge0;
947 pdata->reset_bit = AR934X_RESET_GE1_MAC |
948 AR934X_RESET_GE1_MDIO;
949 pdata->set_speed = ath79_set_speed_dummy;
951 pdata->switch_data = &ath79_switch_data;
953 /* reset the built-in switch */
954 ath79_device_reset_set(AR934X_RESET_ETH_SWITCH);
955 ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH);
958 pdata->ddr_flush = ath79_ddr_no_flush;
960 pdata->is_ar724x = 1;
962 pdata->max_frame_len = SZ_16K - 1;
963 pdata->desc_pktlen_mask = SZ_16K - 1;
965 if (!pdata->fifo_cfg1)
966 pdata->fifo_cfg1 = 0x0010ffff;
967 if (!pdata->fifo_cfg2)
968 pdata->fifo_cfg2 = 0x015500aa;
969 if (!pdata->fifo_cfg3)
970 pdata->fifo_cfg3 = 0x01f00140;
973 case ATH79_SOC_QCA9556:
974 case ATH79_SOC_QCA9558:
976 pdata->reset_bit = QCA955X_RESET_GE0_MAC |
977 QCA955X_RESET_GE0_MDIO;
978 pdata->set_speed = qca955x_set_speed_xmii;
980 pdata->reset_bit = QCA955X_RESET_GE1_MAC |
981 QCA955X_RESET_GE1_MDIO;
982 pdata->set_speed = qca955x_set_speed_sgmii;
985 pdata->ddr_flush = ath79_ddr_no_flush;
987 pdata->is_ar724x = 1;
989 if (!pdata->fifo_cfg1)
990 pdata->fifo_cfg1 = 0x0010ffff;
991 if (!pdata->fifo_cfg2)
992 pdata->fifo_cfg2 = 0x015500aa;
993 if (!pdata->fifo_cfg3)
994 pdata->fifo_cfg3 = 0x01f00140;
1001 switch (pdata->phy_if_mode) {
1002 case PHY_INTERFACE_MODE_GMII:
1003 case PHY_INTERFACE_MODE_RGMII:
1004 case PHY_INTERFACE_MODE_SGMII:
1005 if (!pdata->has_gbit) {
1006 printk(KERN_ERR "ar71xx: no gbit available on eth%d\n",
1015 if (!is_valid_ether_addr(pdata->mac_addr)) {
1016 random_ether_addr(pdata->mac_addr);
1018 "ar71xx: using random MAC address for eth%d\n",
1019 ath79_eth_instance);
1022 if (pdata->mii_bus_dev == NULL) {
1023 switch (ath79_soc) {
1024 case ATH79_SOC_AR9341:
1025 case ATH79_SOC_AR9342:
1026 case ATH79_SOC_AR9344:
1028 pdata->mii_bus_dev = &ath79_mdio0_device.dev;
1030 pdata->mii_bus_dev = &ath79_mdio1_device.dev;
1033 case ATH79_SOC_AR7241:
1034 case ATH79_SOC_AR9330:
1035 case ATH79_SOC_AR9331:
1036 pdata->mii_bus_dev = &ath79_mdio1_device.dev;
1039 case ATH79_SOC_QCA9556:
1040 case ATH79_SOC_QCA9558:
1041 /* don't assign any MDIO device by default */
1045 pdata->mii_bus_dev = &ath79_mdio0_device.dev;
1050 /* Reset the device */
1051 ath79_device_reset_set(pdata->reset_bit);
1054 ath79_device_reset_clear(pdata->reset_bit);
1057 platform_device_register(pdev);
1058 ath79_eth_instance++;
1061 void __init ath79_set_mac_base(unsigned char *mac)
1063 memcpy(ath79_mac_base, mac, ETH_ALEN);
1066 void __init ath79_parse_ascii_mac(char *mac_str, u8 *mac)
1070 t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
1071 &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5]);
1074 t = sscanf(mac_str, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
1075 &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5]);
1077 if (t != ETH_ALEN || !is_valid_ether_addr(mac)) {
1078 memset(mac, 0, ETH_ALEN);
1079 printk(KERN_DEBUG "ar71xx: invalid mac address \"%s\"\n",
1084 static void __init ath79_set_mac_base_ascii(char *str)
1088 ath79_parse_ascii_mac(str, mac);
1089 ath79_set_mac_base(mac);
1092 static int __init ath79_ethaddr_setup(char *str)
1094 ath79_set_mac_base_ascii(str);
1097 __setup("ethaddr=", ath79_ethaddr_setup);
1099 static int __init ath79_kmac_setup(char *str)
1101 ath79_set_mac_base_ascii(str);
1104 __setup("kmac=", ath79_kmac_setup);
1106 void __init ath79_init_mac(unsigned char *dst, const unsigned char *src,
1114 if (!src || !is_valid_ether_addr(src)) {
1115 memset(dst, '\0', ETH_ALEN);
1119 t = (((u32) src[3]) << 16) + (((u32) src[4]) << 8) + ((u32) src[5]);
1125 dst[3] = (t >> 16) & 0xff;
1126 dst[4] = (t >> 8) & 0xff;
1130 void __init ath79_init_local_mac(unsigned char *dst, const unsigned char *src)
1137 if (!src || !is_valid_ether_addr(src)) {
1138 memset(dst, '\0', ETH_ALEN);
1142 for (i = 0; i < ETH_ALEN; i++)