2 * Atheros AR71xx SoC platform devices
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
8 * Parts of this file are based on Atheros 2.6.15 BSP
9 * Parts of this file are based on Atheros 2.6.31 BSP
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/etherdevice.h>
20 #include <linux/platform_device.h>
21 #include <linux/serial_8250.h>
23 #include <asm/mach-ath79/ath79.h>
24 #include <asm/mach-ath79/ar71xx_regs.h>
25 #include <asm/mach-ath79/irq.h>
30 unsigned char ath79_mac_base[ETH_ALEN] __initdata;
32 static struct resource ath79_mdio0_resources[] = {
35 .flags = IORESOURCE_MEM,
36 .start = AR71XX_GE0_BASE,
37 .end = AR71XX_GE0_BASE + 0x200 - 1,
41 static struct ag71xx_mdio_platform_data ath79_mdio0_data;
43 struct platform_device ath79_mdio0_device = {
44 .name = "ag71xx-mdio",
46 .resource = ath79_mdio0_resources,
47 .num_resources = ARRAY_SIZE(ath79_mdio0_resources),
49 .platform_data = &ath79_mdio0_data,
53 static struct resource ath79_mdio1_resources[] = {
56 .flags = IORESOURCE_MEM,
57 .start = AR71XX_GE1_BASE,
58 .end = AR71XX_GE1_BASE + 0x200 - 1,
62 static struct ag71xx_mdio_platform_data ath79_mdio1_data;
64 struct platform_device ath79_mdio1_device = {
65 .name = "ag71xx-mdio",
67 .resource = ath79_mdio1_resources,
68 .num_resources = ARRAY_SIZE(ath79_mdio1_resources),
70 .platform_data = &ath79_mdio1_data,
74 static void ath79_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift)
79 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
81 t = __raw_readl(base + cfg_reg);
84 __raw_writel(t, base + cfg_reg);
87 __raw_writel(pll_val, base + pll_reg);
90 __raw_writel(t, base + cfg_reg);
94 __raw_writel(t, base + cfg_reg);
97 printk(KERN_DEBUG "ar71xx: pll_reg %#x: %#x\n",
98 (unsigned int)(base + pll_reg), __raw_readl(base + pll_reg));
103 static void __init ath79_mii_ctrl_set_if(unsigned int reg,
109 base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
111 t = __raw_readl(base + reg);
112 t &= ~(AR71XX_MII_CTRL_IF_MASK);
113 t |= (mii_if & AR71XX_MII_CTRL_IF_MASK);
114 __raw_writel(t, base + reg);
119 static void ath79_mii_ctrl_set_speed(unsigned int reg, unsigned int speed)
122 unsigned int mii_speed;
127 mii_speed = AR71XX_MII_CTRL_SPEED_10;
130 mii_speed = AR71XX_MII_CTRL_SPEED_100;
133 mii_speed = AR71XX_MII_CTRL_SPEED_1000;
139 base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
141 t = __raw_readl(base + reg);
142 t &= ~(AR71XX_MII_CTRL_SPEED_MASK << AR71XX_MII_CTRL_SPEED_SHIFT);
143 t |= mii_speed << AR71XX_MII_CTRL_SPEED_SHIFT;
144 __raw_writel(t, base + reg);
149 void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
151 struct platform_device *mdio_dev;
152 struct ag71xx_mdio_platform_data *mdio_data;
155 if (ath79_soc == ATH79_SOC_AR9341 ||
156 ath79_soc == ATH79_SOC_AR9342 ||
157 ath79_soc == ATH79_SOC_AR9344)
163 printk(KERN_ERR "ar71xx: invalid MDIO id %u\n", id);
168 case ATH79_SOC_AR7241:
169 case ATH79_SOC_AR9330:
170 case ATH79_SOC_AR9331:
171 mdio_dev = &ath79_mdio1_device;
172 mdio_data = &ath79_mdio1_data;
175 case ATH79_SOC_AR9341:
176 case ATH79_SOC_AR9342:
177 case ATH79_SOC_AR9344:
179 mdio_dev = &ath79_mdio0_device;
180 mdio_data = &ath79_mdio0_data;
182 mdio_dev = &ath79_mdio1_device;
183 mdio_data = &ath79_mdio1_data;
187 case ATH79_SOC_AR7242:
188 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG,
189 AR7242_PLL_REG_ETH0_INT_CLOCK, 0x62000000,
190 AR71XX_ETH0_PLL_SHIFT);
193 mdio_dev = &ath79_mdio0_device;
194 mdio_data = &ath79_mdio0_data;
198 mdio_data->phy_mask = phy_mask;
201 case ATH79_SOC_AR7240:
202 mdio_data->is_ar7240 = 1;
204 case ATH79_SOC_AR7241:
205 mdio_data->builtin_switch = 1;
208 case ATH79_SOC_AR9330:
209 mdio_data->is_ar9330 = 1;
211 case ATH79_SOC_AR9331:
212 mdio_data->builtin_switch = 1;
215 case ATH79_SOC_AR9341:
216 case ATH79_SOC_AR9342:
217 case ATH79_SOC_AR9344:
219 mdio_data->builtin_switch = 1;
220 mdio_data->is_ar934x = 1;
227 platform_device_register(mdio_dev);
230 struct ath79_eth_pll_data ath79_eth0_pll_data;
231 struct ath79_eth_pll_data ath79_eth1_pll_data;
233 static u32 ath79_get_eth_pll(unsigned int mac, int speed)
235 struct ath79_eth_pll_data *pll_data;
240 pll_data = &ath79_eth0_pll_data;
243 pll_data = &ath79_eth1_pll_data;
251 pll_val = pll_data->pll_10;
254 pll_val = pll_data->pll_100;
257 pll_val = pll_data->pll_1000;
266 static void ath79_set_speed_ge0(int speed)
268 u32 val = ath79_get_eth_pll(0, speed);
270 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK,
271 val, AR71XX_ETH0_PLL_SHIFT);
272 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
275 static void ath79_set_speed_ge1(int speed)
277 u32 val = ath79_get_eth_pll(1, speed);
279 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK,
280 val, AR71XX_ETH1_PLL_SHIFT);
281 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
284 static void ar7242_set_speed_ge0(int speed)
286 u32 val = ath79_get_eth_pll(0, speed);
289 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
290 __raw_writel(val, base + AR7242_PLL_REG_ETH0_INT_CLOCK);
294 static void ar91xx_set_speed_ge0(int speed)
296 u32 val = ath79_get_eth_pll(0, speed);
298 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH0_INT_CLOCK,
299 val, AR913X_ETH0_PLL_SHIFT);
300 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
303 static void ar91xx_set_speed_ge1(int speed)
305 u32 val = ath79_get_eth_pll(1, speed);
307 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH1_INT_CLOCK,
308 val, AR913X_ETH1_PLL_SHIFT);
309 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
312 static void ar934x_set_speed_ge0(int speed)
315 u32 val = ath79_get_eth_pll(0, speed);
317 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
318 __raw_writel(val, base + AR934X_PLL_ETH_XMII_CONTROL_REG);
322 static void ath79_set_speed_dummy(int speed)
326 static void ath79_ddr_no_flush(void)
330 static void ath79_ddr_flush_ge0(void)
332 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE0);
335 static void ath79_ddr_flush_ge1(void)
337 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE1);
340 static void ar724x_ddr_flush_ge0(void)
342 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE0);
345 static void ar724x_ddr_flush_ge1(void)
347 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE1);
350 static void ar91xx_ddr_flush_ge0(void)
352 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE0);
355 static void ar91xx_ddr_flush_ge1(void)
357 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE1);
360 static void ar933x_ddr_flush_ge0(void)
362 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE0);
365 static void ar933x_ddr_flush_ge1(void)
367 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE1);
370 static struct resource ath79_eth0_resources[] = {
373 .flags = IORESOURCE_MEM,
374 .start = AR71XX_GE0_BASE,
375 .end = AR71XX_GE0_BASE + 0x200 - 1,
378 .flags = IORESOURCE_IRQ,
379 .start = ATH79_CPU_IRQ_GE0,
380 .end = ATH79_CPU_IRQ_GE0,
384 struct ag71xx_platform_data ath79_eth0_data = {
385 .reset_bit = AR71XX_RESET_GE0_MAC,
388 struct platform_device ath79_eth0_device = {
391 .resource = ath79_eth0_resources,
392 .num_resources = ARRAY_SIZE(ath79_eth0_resources),
394 .platform_data = &ath79_eth0_data,
398 static struct resource ath79_eth1_resources[] = {
401 .flags = IORESOURCE_MEM,
402 .start = AR71XX_GE1_BASE,
403 .end = AR71XX_GE1_BASE + 0x200 - 1,
406 .flags = IORESOURCE_IRQ,
407 .start = ATH79_CPU_IRQ_GE1,
408 .end = ATH79_CPU_IRQ_GE1,
412 struct ag71xx_platform_data ath79_eth1_data = {
413 .reset_bit = AR71XX_RESET_GE1_MAC,
416 struct platform_device ath79_eth1_device = {
419 .resource = ath79_eth1_resources,
420 .num_resources = ARRAY_SIZE(ath79_eth1_resources),
422 .platform_data = &ath79_eth1_data,
426 struct ag71xx_switch_platform_data ath79_switch_data;
428 #define AR71XX_PLL_VAL_1000 0x00110000
429 #define AR71XX_PLL_VAL_100 0x00001099
430 #define AR71XX_PLL_VAL_10 0x00991099
432 #define AR724X_PLL_VAL_1000 0x00110000
433 #define AR724X_PLL_VAL_100 0x00001099
434 #define AR724X_PLL_VAL_10 0x00991099
436 #define AR7242_PLL_VAL_1000 0x16000000
437 #define AR7242_PLL_VAL_100 0x00000101
438 #define AR7242_PLL_VAL_10 0x00001616
440 #define AR913X_PLL_VAL_1000 0x1a000000
441 #define AR913X_PLL_VAL_100 0x13000a44
442 #define AR913X_PLL_VAL_10 0x00441099
444 #define AR933X_PLL_VAL_1000 0x00110000
445 #define AR933X_PLL_VAL_100 0x00001099
446 #define AR933X_PLL_VAL_10 0x00991099
448 #define AR934X_PLL_VAL_1000 0x16000000
449 #define AR934X_PLL_VAL_100 0x00000101
450 #define AR934X_PLL_VAL_10 0x00001616
452 static void __init ath79_init_eth_pll_data(unsigned int id)
454 struct ath79_eth_pll_data *pll_data;
455 u32 pll_10, pll_100, pll_1000;
459 pll_data = &ath79_eth0_pll_data;
462 pll_data = &ath79_eth1_pll_data;
469 case ATH79_SOC_AR7130:
470 case ATH79_SOC_AR7141:
471 case ATH79_SOC_AR7161:
472 pll_10 = AR71XX_PLL_VAL_10;
473 pll_100 = AR71XX_PLL_VAL_100;
474 pll_1000 = AR71XX_PLL_VAL_1000;
477 case ATH79_SOC_AR7240:
478 case ATH79_SOC_AR7241:
479 pll_10 = AR724X_PLL_VAL_10;
480 pll_100 = AR724X_PLL_VAL_100;
481 pll_1000 = AR724X_PLL_VAL_1000;
484 case ATH79_SOC_AR7242:
485 pll_10 = AR7242_PLL_VAL_10;
486 pll_100 = AR7242_PLL_VAL_100;
487 pll_1000 = AR7242_PLL_VAL_1000;
490 case ATH79_SOC_AR9130:
491 case ATH79_SOC_AR9132:
492 pll_10 = AR913X_PLL_VAL_10;
493 pll_100 = AR913X_PLL_VAL_100;
494 pll_1000 = AR913X_PLL_VAL_1000;
497 case ATH79_SOC_AR9330:
498 case ATH79_SOC_AR9331:
499 pll_10 = AR933X_PLL_VAL_10;
500 pll_100 = AR933X_PLL_VAL_100;
501 pll_1000 = AR933X_PLL_VAL_1000;
504 case ATH79_SOC_AR9341:
505 case ATH79_SOC_AR9342:
506 case ATH79_SOC_AR9344:
507 pll_10 = AR934X_PLL_VAL_10;
508 pll_100 = AR934X_PLL_VAL_100;
509 pll_1000 = AR934X_PLL_VAL_1000;
516 if (!pll_data->pll_10)
517 pll_data->pll_10 = pll_10;
519 if (!pll_data->pll_100)
520 pll_data->pll_100 = pll_100;
522 if (!pll_data->pll_1000)
523 pll_data->pll_1000 = pll_1000;
526 static int __init ath79_setup_phy_if_mode(unsigned int id,
527 struct ag71xx_platform_data *pdata)
534 case ATH79_SOC_AR7130:
535 case ATH79_SOC_AR7141:
536 case ATH79_SOC_AR7161:
537 case ATH79_SOC_AR9130:
538 case ATH79_SOC_AR9132:
539 switch (pdata->phy_if_mode) {
540 case PHY_INTERFACE_MODE_MII:
541 mii_if = AR71XX_MII0_CTRL_IF_MII;
543 case PHY_INTERFACE_MODE_GMII:
544 mii_if = AR71XX_MII0_CTRL_IF_GMII;
546 case PHY_INTERFACE_MODE_RGMII:
547 mii_if = AR71XX_MII0_CTRL_IF_RGMII;
549 case PHY_INTERFACE_MODE_RMII:
550 mii_if = AR71XX_MII0_CTRL_IF_RMII;
555 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII0_CTRL, mii_if);
558 case ATH79_SOC_AR7240:
559 case ATH79_SOC_AR7241:
560 case ATH79_SOC_AR9330:
561 case ATH79_SOC_AR9331:
562 pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
565 case ATH79_SOC_AR7242:
568 case ATH79_SOC_AR9341:
569 case ATH79_SOC_AR9342:
570 case ATH79_SOC_AR9344:
571 switch (pdata->phy_if_mode) {
572 case PHY_INTERFACE_MODE_MII:
573 case PHY_INTERFACE_MODE_GMII:
574 case PHY_INTERFACE_MODE_RGMII:
575 case PHY_INTERFACE_MODE_RMII:
588 case ATH79_SOC_AR7130:
589 case ATH79_SOC_AR7141:
590 case ATH79_SOC_AR7161:
591 case ATH79_SOC_AR9130:
592 case ATH79_SOC_AR9132:
593 switch (pdata->phy_if_mode) {
594 case PHY_INTERFACE_MODE_RMII:
595 mii_if = AR71XX_MII1_CTRL_IF_RMII;
597 case PHY_INTERFACE_MODE_RGMII:
598 mii_if = AR71XX_MII1_CTRL_IF_RGMII;
603 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII1_CTRL, mii_if);
606 case ATH79_SOC_AR7240:
607 case ATH79_SOC_AR7241:
608 case ATH79_SOC_AR9330:
609 case ATH79_SOC_AR9331:
610 pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
613 case ATH79_SOC_AR7242:
616 case ATH79_SOC_AR9341:
617 case ATH79_SOC_AR9342:
618 case ATH79_SOC_AR9344:
619 switch (pdata->phy_if_mode) {
620 case PHY_INTERFACE_MODE_MII:
621 case PHY_INTERFACE_MODE_GMII:
637 static int ath79_eth_instance __initdata;
638 void __init ath79_register_eth(unsigned int id)
640 struct platform_device *pdev;
641 struct ag71xx_platform_data *pdata;
645 printk(KERN_ERR "ar71xx: invalid ethernet id %d\n", id);
649 ath79_init_eth_pll_data(id);
652 pdev = &ath79_eth0_device;
654 pdev = &ath79_eth1_device;
656 pdata = pdev->dev.platform_data;
658 err = ath79_setup_phy_if_mode(id, pdata);
661 "ar71xx: invalid PHY interface mode for GE%u\n", id);
666 case ATH79_SOC_AR7130:
668 pdata->ddr_flush = ath79_ddr_flush_ge0;
669 pdata->set_speed = ath79_set_speed_ge0;
671 pdata->ddr_flush = ath79_ddr_flush_ge1;
672 pdata->set_speed = ath79_set_speed_ge1;
676 case ATH79_SOC_AR7141:
677 case ATH79_SOC_AR7161:
679 pdata->ddr_flush = ath79_ddr_flush_ge0;
680 pdata->set_speed = ath79_set_speed_ge0;
682 pdata->ddr_flush = ath79_ddr_flush_ge1;
683 pdata->set_speed = ath79_set_speed_ge1;
688 case ATH79_SOC_AR7242:
690 pdata->reset_bit |= AR724X_RESET_GE0_MDIO |
691 AR71XX_RESET_GE0_PHY;
692 pdata->ddr_flush = ar724x_ddr_flush_ge0;
693 pdata->set_speed = ar7242_set_speed_ge0;
695 pdata->reset_bit |= AR724X_RESET_GE1_MDIO |
696 AR71XX_RESET_GE1_PHY;
697 pdata->ddr_flush = ar724x_ddr_flush_ge1;
698 pdata->set_speed = ath79_set_speed_dummy;
701 pdata->is_ar724x = 1;
703 if (!pdata->fifo_cfg1)
704 pdata->fifo_cfg1 = 0x0010ffff;
705 if (!pdata->fifo_cfg2)
706 pdata->fifo_cfg2 = 0x015500aa;
707 if (!pdata->fifo_cfg3)
708 pdata->fifo_cfg3 = 0x01f00140;
711 case ATH79_SOC_AR7241:
713 pdata->reset_bit |= AR724X_RESET_GE0_MDIO;
715 pdata->reset_bit |= AR724X_RESET_GE1_MDIO;
717 case ATH79_SOC_AR7240:
719 pdata->reset_bit |= AR71XX_RESET_GE0_PHY;
720 pdata->ddr_flush = ar724x_ddr_flush_ge0;
721 pdata->set_speed = ath79_set_speed_dummy;
723 pdata->phy_mask = BIT(4);
725 pdata->reset_bit |= AR71XX_RESET_GE1_PHY;
726 pdata->ddr_flush = ar724x_ddr_flush_ge1;
727 pdata->set_speed = ath79_set_speed_dummy;
729 pdata->speed = SPEED_1000;
730 pdata->duplex = DUPLEX_FULL;
731 pdata->switch_data = &ath79_switch_data;
733 ath79_switch_data.phy_poll_mask |= BIT(4);
736 pdata->is_ar724x = 1;
737 if (ath79_soc == ATH79_SOC_AR7240)
738 pdata->is_ar7240 = 1;
740 if (!pdata->fifo_cfg1)
741 pdata->fifo_cfg1 = 0x0010ffff;
742 if (!pdata->fifo_cfg2)
743 pdata->fifo_cfg2 = 0x015500aa;
744 if (!pdata->fifo_cfg3)
745 pdata->fifo_cfg3 = 0x01f00140;
748 case ATH79_SOC_AR9130:
750 pdata->ddr_flush = ar91xx_ddr_flush_ge0;
751 pdata->set_speed = ar91xx_set_speed_ge0;
753 pdata->ddr_flush = ar91xx_ddr_flush_ge1;
754 pdata->set_speed = ar91xx_set_speed_ge1;
756 pdata->is_ar91xx = 1;
759 case ATH79_SOC_AR9132:
761 pdata->ddr_flush = ar91xx_ddr_flush_ge0;
762 pdata->set_speed = ar91xx_set_speed_ge0;
764 pdata->ddr_flush = ar91xx_ddr_flush_ge1;
765 pdata->set_speed = ar91xx_set_speed_ge1;
767 pdata->is_ar91xx = 1;
771 case ATH79_SOC_AR9330:
772 case ATH79_SOC_AR9331:
774 pdata->reset_bit = AR933X_RESET_GE0_MAC |
775 AR933X_RESET_GE0_MDIO;
776 pdata->ddr_flush = ar933x_ddr_flush_ge0;
777 pdata->set_speed = ath79_set_speed_dummy;
779 pdata->phy_mask = BIT(4);
781 pdata->reset_bit = AR933X_RESET_GE1_MAC |
782 AR933X_RESET_GE1_MDIO;
783 pdata->ddr_flush = ar933x_ddr_flush_ge1;
784 pdata->set_speed = ath79_set_speed_dummy;
786 pdata->speed = SPEED_1000;
787 pdata->duplex = DUPLEX_FULL;
788 pdata->switch_data = &ath79_switch_data;
790 ath79_switch_data.phy_poll_mask |= BIT(4);
794 pdata->is_ar724x = 1;
796 if (!pdata->fifo_cfg1)
797 pdata->fifo_cfg1 = 0x0010ffff;
798 if (!pdata->fifo_cfg2)
799 pdata->fifo_cfg2 = 0x015500aa;
800 if (!pdata->fifo_cfg3)
801 pdata->fifo_cfg3 = 0x01f00140;
804 case ATH79_SOC_AR9341:
805 case ATH79_SOC_AR9342:
806 case ATH79_SOC_AR9344:
808 pdata->reset_bit = AR934X_RESET_GE0_MAC |
809 AR934X_RESET_GE0_MDIO;
810 pdata->set_speed = ar934x_set_speed_ge0;
812 pdata->reset_bit = AR934X_RESET_GE1_MAC |
813 AR934X_RESET_GE1_MDIO;
814 pdata->set_speed = ath79_set_speed_dummy;
816 pdata->switch_data = &ath79_switch_data;
818 /* reset the built-in switch */
819 ath79_device_reset_set(AR934X_RESET_ETH_SWITCH);
820 ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH);
823 pdata->ddr_flush = ath79_ddr_no_flush;
825 pdata->is_ar724x = 1;
827 if (!pdata->fifo_cfg1)
828 pdata->fifo_cfg1 = 0x0010ffff;
829 if (!pdata->fifo_cfg2)
830 pdata->fifo_cfg2 = 0x015500aa;
831 if (!pdata->fifo_cfg3)
832 pdata->fifo_cfg3 = 0x01f00140;
839 switch (pdata->phy_if_mode) {
840 case PHY_INTERFACE_MODE_GMII:
841 case PHY_INTERFACE_MODE_RGMII:
842 if (!pdata->has_gbit) {
843 printk(KERN_ERR "ar71xx: no gbit available on eth%d\n",
852 if (!is_valid_ether_addr(pdata->mac_addr)) {
853 random_ether_addr(pdata->mac_addr);
855 "ar71xx: using random MAC address for eth%d\n",
859 if (pdata->mii_bus_dev == NULL) {
861 case ATH79_SOC_AR9341:
862 case ATH79_SOC_AR9342:
863 case ATH79_SOC_AR9344:
865 pdata->mii_bus_dev = &ath79_mdio0_device.dev;
867 pdata->mii_bus_dev = &ath79_mdio1_device.dev;
870 case ATH79_SOC_AR7241:
871 case ATH79_SOC_AR9330:
872 case ATH79_SOC_AR9331:
873 pdata->mii_bus_dev = &ath79_mdio1_device.dev;
877 pdata->mii_bus_dev = &ath79_mdio0_device.dev;
882 /* Reset the device */
883 ath79_device_reset_set(pdata->reset_bit);
886 ath79_device_reset_clear(pdata->reset_bit);
889 platform_device_register(pdev);
890 ath79_eth_instance++;
893 void __init ath79_set_mac_base(unsigned char *mac)
895 memcpy(ath79_mac_base, mac, ETH_ALEN);
898 void __init ath79_parse_mac_addr(char *mac_str)
903 t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
904 &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
907 t = sscanf(mac_str, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
908 &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
911 ath79_set_mac_base(tmp);
913 printk(KERN_DEBUG "ar71xx: failed to parse mac address "
914 "\"%s\"\n", mac_str);
917 static int __init ath79_ethaddr_setup(char *str)
919 ath79_parse_mac_addr(str);
922 __setup("ethaddr=", ath79_ethaddr_setup);
924 static int __init ath79_kmac_setup(char *str)
926 ath79_parse_mac_addr(str);
929 __setup("kmac=", ath79_kmac_setup);
931 void __init ath79_init_mac(unsigned char *dst, const unsigned char *src,
936 if (!is_valid_ether_addr(src)) {
937 memset(dst, '\0', ETH_ALEN);
941 t = (((u32) src[3]) << 16) + (((u32) src[4]) << 8) + ((u32) src[5]);
947 dst[3] = (t >> 16) & 0xff;
948 dst[4] = (t >> 8) & 0xff;
952 void __init ath79_init_local_mac(unsigned char *dst, const unsigned char *src)
956 if (!is_valid_ether_addr(src)) {
957 memset(dst, '\0', ETH_ALEN);
961 for (i = 0; i < ETH_ALEN; i++)