2 * Atheros AR71xx SoC platform devices
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
8 * Parts of this file are based on Atheros 2.6.15 BSP
9 * Parts of this file are based on Atheros 2.6.31 BSP
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/etherdevice.h>
20 #include <linux/platform_device.h>
21 #include <linux/serial_8250.h>
22 #include <linux/clk.h>
24 #include <asm/mach-ath79/ath79.h>
25 #include <asm/mach-ath79/ar71xx_regs.h>
26 #include <asm/mach-ath79/irq.h>
31 unsigned char ath79_mac_base[ETH_ALEN] __initdata;
33 static struct resource ath79_mdio0_resources[] = {
36 .flags = IORESOURCE_MEM,
37 .start = AR71XX_GE0_BASE,
38 .end = AR71XX_GE0_BASE + 0x200 - 1,
42 struct ag71xx_mdio_platform_data ath79_mdio0_data;
44 struct platform_device ath79_mdio0_device = {
45 .name = "ag71xx-mdio",
47 .resource = ath79_mdio0_resources,
48 .num_resources = ARRAY_SIZE(ath79_mdio0_resources),
50 .platform_data = &ath79_mdio0_data,
54 static struct resource ath79_mdio1_resources[] = {
57 .flags = IORESOURCE_MEM,
58 .start = AR71XX_GE1_BASE,
59 .end = AR71XX_GE1_BASE + 0x200 - 1,
63 struct ag71xx_mdio_platform_data ath79_mdio1_data;
65 struct platform_device ath79_mdio1_device = {
66 .name = "ag71xx-mdio",
68 .resource = ath79_mdio1_resources,
69 .num_resources = ARRAY_SIZE(ath79_mdio1_resources),
71 .platform_data = &ath79_mdio1_data,
75 static void ath79_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift)
80 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
82 t = __raw_readl(base + cfg_reg);
85 __raw_writel(t, base + cfg_reg);
88 __raw_writel(pll_val, base + pll_reg);
91 __raw_writel(t, base + cfg_reg);
95 __raw_writel(t, base + cfg_reg);
98 printk(KERN_DEBUG "ar71xx: pll_reg %#x: %#x\n",
99 (unsigned int)(base + pll_reg), __raw_readl(base + pll_reg));
104 static void __init ath79_mii_ctrl_set_if(unsigned int reg,
110 base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
112 t = __raw_readl(base + reg);
113 t &= ~(AR71XX_MII_CTRL_IF_MASK);
114 t |= (mii_if & AR71XX_MII_CTRL_IF_MASK);
115 __raw_writel(t, base + reg);
120 static void ath79_mii_ctrl_set_speed(unsigned int reg, unsigned int speed)
123 unsigned int mii_speed;
128 mii_speed = AR71XX_MII_CTRL_SPEED_10;
131 mii_speed = AR71XX_MII_CTRL_SPEED_100;
134 mii_speed = AR71XX_MII_CTRL_SPEED_1000;
140 base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
142 t = __raw_readl(base + reg);
143 t &= ~(AR71XX_MII_CTRL_SPEED_MASK << AR71XX_MII_CTRL_SPEED_SHIFT);
144 t |= mii_speed << AR71XX_MII_CTRL_SPEED_SHIFT;
145 __raw_writel(t, base + reg);
150 static unsigned long ar934x_get_mdio_ref_clock(void)
156 base = ioremap(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
159 t = __raw_readl(base + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
160 if (t & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL) {
161 ret = 100 * 1000 * 1000;
165 clk = clk_get(NULL, "ref");
167 ret = clk_get_rate(clk);
175 void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
177 struct platform_device *mdio_dev;
178 struct ag71xx_mdio_platform_data *mdio_data;
181 if (ath79_soc == ATH79_SOC_AR9341 ||
182 ath79_soc == ATH79_SOC_AR9342 ||
183 ath79_soc == ATH79_SOC_AR9344 ||
184 ath79_soc == ATH79_SOC_QCA9556 ||
185 ath79_soc == ATH79_SOC_QCA9558)
191 printk(KERN_ERR "ar71xx: invalid MDIO id %u\n", id);
196 case ATH79_SOC_AR7241:
197 case ATH79_SOC_AR9330:
198 case ATH79_SOC_AR9331:
199 mdio_dev = &ath79_mdio1_device;
200 mdio_data = &ath79_mdio1_data;
203 case ATH79_SOC_AR9341:
204 case ATH79_SOC_AR9342:
205 case ATH79_SOC_AR9344:
206 case ATH79_SOC_QCA9556:
207 case ATH79_SOC_QCA9558:
209 mdio_dev = &ath79_mdio0_device;
210 mdio_data = &ath79_mdio0_data;
212 mdio_dev = &ath79_mdio1_device;
213 mdio_data = &ath79_mdio1_data;
217 case ATH79_SOC_AR7242:
218 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG,
219 AR7242_PLL_REG_ETH0_INT_CLOCK, 0x62000000,
220 AR71XX_ETH0_PLL_SHIFT);
223 mdio_dev = &ath79_mdio0_device;
224 mdio_data = &ath79_mdio0_data;
228 mdio_data->phy_mask = phy_mask;
231 case ATH79_SOC_AR7240:
232 mdio_data->is_ar7240 = 1;
234 case ATH79_SOC_AR7241:
235 mdio_data->builtin_switch = 1;
238 case ATH79_SOC_AR9330:
239 mdio_data->is_ar9330 = 1;
241 case ATH79_SOC_AR9331:
242 mdio_data->builtin_switch = 1;
245 case ATH79_SOC_AR9341:
246 case ATH79_SOC_AR9342:
247 case ATH79_SOC_AR9344:
249 mdio_data->builtin_switch = 1;
250 mdio_data->ref_clock = ar934x_get_mdio_ref_clock();
251 mdio_data->mdio_clock = 6250000;
253 mdio_data->is_ar934x = 1;
256 case ATH79_SOC_QCA9558:
258 mdio_data->builtin_switch = 1;
259 mdio_data->is_ar934x = 1;
262 case ATH79_SOC_QCA9556:
263 mdio_data->is_ar934x = 1;
270 platform_device_register(mdio_dev);
273 struct ath79_eth_pll_data ath79_eth0_pll_data;
274 struct ath79_eth_pll_data ath79_eth1_pll_data;
276 static u32 ath79_get_eth_pll(unsigned int mac, int speed)
278 struct ath79_eth_pll_data *pll_data;
283 pll_data = &ath79_eth0_pll_data;
286 pll_data = &ath79_eth1_pll_data;
294 pll_val = pll_data->pll_10;
297 pll_val = pll_data->pll_100;
300 pll_val = pll_data->pll_1000;
309 static void ath79_set_speed_ge0(int speed)
311 u32 val = ath79_get_eth_pll(0, speed);
313 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK,
314 val, AR71XX_ETH0_PLL_SHIFT);
315 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
318 static void ath79_set_speed_ge1(int speed)
320 u32 val = ath79_get_eth_pll(1, speed);
322 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK,
323 val, AR71XX_ETH1_PLL_SHIFT);
324 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
327 static void ar7242_set_speed_ge0(int speed)
329 u32 val = ath79_get_eth_pll(0, speed);
332 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
333 __raw_writel(val, base + AR7242_PLL_REG_ETH0_INT_CLOCK);
337 static void ar91xx_set_speed_ge0(int speed)
339 u32 val = ath79_get_eth_pll(0, speed);
341 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH0_INT_CLOCK,
342 val, AR913X_ETH0_PLL_SHIFT);
343 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
346 static void ar91xx_set_speed_ge1(int speed)
348 u32 val = ath79_get_eth_pll(1, speed);
350 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH1_INT_CLOCK,
351 val, AR913X_ETH1_PLL_SHIFT);
352 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
355 static void ar934x_set_speed_ge0(int speed)
358 u32 val = ath79_get_eth_pll(0, speed);
360 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
361 __raw_writel(val, base + AR934X_PLL_ETH_XMII_CONTROL_REG);
365 static void qca955x_set_speed_xmii(int speed)
368 u32 val = ath79_get_eth_pll(0, speed);
370 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
371 __raw_writel(val, base + QCA955X_PLL_ETH_XMII_CONTROL_REG);
375 static void qca955x_set_speed_sgmii(int speed)
378 u32 val = ath79_get_eth_pll(1, speed);
380 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
381 __raw_writel(val, base + QCA955X_PLL_ETH_SGMII_CONTROL_REG);
385 static void ath79_set_speed_dummy(int speed)
389 static void ath79_ddr_no_flush(void)
393 static void ath79_ddr_flush_ge0(void)
395 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE0);
398 static void ath79_ddr_flush_ge1(void)
400 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE1);
403 static void ar724x_ddr_flush_ge0(void)
405 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE0);
408 static void ar724x_ddr_flush_ge1(void)
410 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE1);
413 static void ar91xx_ddr_flush_ge0(void)
415 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE0);
418 static void ar91xx_ddr_flush_ge1(void)
420 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE1);
423 static void ar933x_ddr_flush_ge0(void)
425 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE0);
428 static void ar933x_ddr_flush_ge1(void)
430 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE1);
433 static struct resource ath79_eth0_resources[] = {
436 .flags = IORESOURCE_MEM,
437 .start = AR71XX_GE0_BASE,
438 .end = AR71XX_GE0_BASE + 0x200 - 1,
441 .flags = IORESOURCE_IRQ,
442 .start = ATH79_CPU_IRQ(4),
443 .end = ATH79_CPU_IRQ(4),
447 struct ag71xx_platform_data ath79_eth0_data = {
448 .reset_bit = AR71XX_RESET_GE0_MAC,
451 struct platform_device ath79_eth0_device = {
454 .resource = ath79_eth0_resources,
455 .num_resources = ARRAY_SIZE(ath79_eth0_resources),
457 .platform_data = &ath79_eth0_data,
461 static struct resource ath79_eth1_resources[] = {
464 .flags = IORESOURCE_MEM,
465 .start = AR71XX_GE1_BASE,
466 .end = AR71XX_GE1_BASE + 0x200 - 1,
469 .flags = IORESOURCE_IRQ,
470 .start = ATH79_CPU_IRQ(5),
471 .end = ATH79_CPU_IRQ(5),
475 struct ag71xx_platform_data ath79_eth1_data = {
476 .reset_bit = AR71XX_RESET_GE1_MAC,
479 struct platform_device ath79_eth1_device = {
482 .resource = ath79_eth1_resources,
483 .num_resources = ARRAY_SIZE(ath79_eth1_resources),
485 .platform_data = &ath79_eth1_data,
489 struct ag71xx_switch_platform_data ath79_switch_data;
491 #define AR71XX_PLL_VAL_1000 0x00110000
492 #define AR71XX_PLL_VAL_100 0x00001099
493 #define AR71XX_PLL_VAL_10 0x00991099
495 #define AR724X_PLL_VAL_1000 0x00110000
496 #define AR724X_PLL_VAL_100 0x00001099
497 #define AR724X_PLL_VAL_10 0x00991099
499 #define AR7242_PLL_VAL_1000 0x16000000
500 #define AR7242_PLL_VAL_100 0x00000101
501 #define AR7242_PLL_VAL_10 0x00001616
503 #define AR913X_PLL_VAL_1000 0x1a000000
504 #define AR913X_PLL_VAL_100 0x13000a44
505 #define AR913X_PLL_VAL_10 0x00441099
507 #define AR933X_PLL_VAL_1000 0x00110000
508 #define AR933X_PLL_VAL_100 0x00001099
509 #define AR933X_PLL_VAL_10 0x00991099
511 #define AR934X_PLL_VAL_1000 0x16000000
512 #define AR934X_PLL_VAL_100 0x00000101
513 #define AR934X_PLL_VAL_10 0x00001616
515 static void __init ath79_init_eth_pll_data(unsigned int id)
517 struct ath79_eth_pll_data *pll_data;
518 u32 pll_10, pll_100, pll_1000;
522 pll_data = &ath79_eth0_pll_data;
525 pll_data = &ath79_eth1_pll_data;
532 case ATH79_SOC_AR7130:
533 case ATH79_SOC_AR7141:
534 case ATH79_SOC_AR7161:
535 pll_10 = AR71XX_PLL_VAL_10;
536 pll_100 = AR71XX_PLL_VAL_100;
537 pll_1000 = AR71XX_PLL_VAL_1000;
540 case ATH79_SOC_AR7240:
541 case ATH79_SOC_AR7241:
542 pll_10 = AR724X_PLL_VAL_10;
543 pll_100 = AR724X_PLL_VAL_100;
544 pll_1000 = AR724X_PLL_VAL_1000;
547 case ATH79_SOC_AR7242:
548 pll_10 = AR7242_PLL_VAL_10;
549 pll_100 = AR7242_PLL_VAL_100;
550 pll_1000 = AR7242_PLL_VAL_1000;
553 case ATH79_SOC_AR9130:
554 case ATH79_SOC_AR9132:
555 pll_10 = AR913X_PLL_VAL_10;
556 pll_100 = AR913X_PLL_VAL_100;
557 pll_1000 = AR913X_PLL_VAL_1000;
560 case ATH79_SOC_AR9330:
561 case ATH79_SOC_AR9331:
562 pll_10 = AR933X_PLL_VAL_10;
563 pll_100 = AR933X_PLL_VAL_100;
564 pll_1000 = AR933X_PLL_VAL_1000;
567 case ATH79_SOC_AR9341:
568 case ATH79_SOC_AR9342:
569 case ATH79_SOC_AR9344:
570 case ATH79_SOC_QCA9556:
571 case ATH79_SOC_QCA9558:
572 pll_10 = AR934X_PLL_VAL_10;
573 pll_100 = AR934X_PLL_VAL_100;
574 pll_1000 = AR934X_PLL_VAL_1000;
581 if (!pll_data->pll_10)
582 pll_data->pll_10 = pll_10;
584 if (!pll_data->pll_100)
585 pll_data->pll_100 = pll_100;
587 if (!pll_data->pll_1000)
588 pll_data->pll_1000 = pll_1000;
591 static int __init ath79_setup_phy_if_mode(unsigned int id,
592 struct ag71xx_platform_data *pdata)
599 case ATH79_SOC_AR7130:
600 case ATH79_SOC_AR7141:
601 case ATH79_SOC_AR7161:
602 case ATH79_SOC_AR9130:
603 case ATH79_SOC_AR9132:
604 switch (pdata->phy_if_mode) {
605 case PHY_INTERFACE_MODE_MII:
606 mii_if = AR71XX_MII0_CTRL_IF_MII;
608 case PHY_INTERFACE_MODE_GMII:
609 mii_if = AR71XX_MII0_CTRL_IF_GMII;
611 case PHY_INTERFACE_MODE_RGMII:
612 mii_if = AR71XX_MII0_CTRL_IF_RGMII;
614 case PHY_INTERFACE_MODE_RMII:
615 mii_if = AR71XX_MII0_CTRL_IF_RMII;
620 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII0_CTRL, mii_if);
623 case ATH79_SOC_AR7240:
624 case ATH79_SOC_AR7241:
625 case ATH79_SOC_AR9330:
626 case ATH79_SOC_AR9331:
627 pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
630 case ATH79_SOC_AR7242:
633 case ATH79_SOC_AR9341:
634 case ATH79_SOC_AR9342:
635 case ATH79_SOC_AR9344:
636 switch (pdata->phy_if_mode) {
637 case PHY_INTERFACE_MODE_MII:
638 case PHY_INTERFACE_MODE_GMII:
639 case PHY_INTERFACE_MODE_RGMII:
640 case PHY_INTERFACE_MODE_RMII:
647 case ATH79_SOC_QCA9556:
648 case ATH79_SOC_QCA9558:
649 switch (pdata->phy_if_mode) {
650 case PHY_INTERFACE_MODE_MII:
651 case PHY_INTERFACE_MODE_RGMII:
652 case PHY_INTERFACE_MODE_SGMII:
665 case ATH79_SOC_AR7130:
666 case ATH79_SOC_AR7141:
667 case ATH79_SOC_AR7161:
668 case ATH79_SOC_AR9130:
669 case ATH79_SOC_AR9132:
670 switch (pdata->phy_if_mode) {
671 case PHY_INTERFACE_MODE_RMII:
672 mii_if = AR71XX_MII1_CTRL_IF_RMII;
674 case PHY_INTERFACE_MODE_RGMII:
675 mii_if = AR71XX_MII1_CTRL_IF_RGMII;
680 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII1_CTRL, mii_if);
683 case ATH79_SOC_AR7240:
684 case ATH79_SOC_AR7241:
685 case ATH79_SOC_AR9330:
686 case ATH79_SOC_AR9331:
687 pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
690 case ATH79_SOC_AR7242:
693 case ATH79_SOC_AR9341:
694 case ATH79_SOC_AR9342:
695 case ATH79_SOC_AR9344:
696 switch (pdata->phy_if_mode) {
697 case PHY_INTERFACE_MODE_MII:
698 case PHY_INTERFACE_MODE_GMII:
705 case ATH79_SOC_QCA9556:
706 case ATH79_SOC_QCA9558:
707 switch (pdata->phy_if_mode) {
708 case PHY_INTERFACE_MODE_MII:
709 case PHY_INTERFACE_MODE_RGMII:
710 case PHY_INTERFACE_MODE_SGMII:
726 void __init ath79_setup_ar933x_phy4_switch(bool mac, bool mdio)
731 base = ioremap(AR933X_GMAC_BASE, AR933X_GMAC_SIZE);
733 t = __raw_readl(base + AR933X_GMAC_REG_ETH_CFG);
734 t &= ~(AR933X_ETH_CFG_SW_PHY_SWAP | AR933X_ETH_CFG_SW_PHY_ADDR_SWAP);
736 t |= AR933X_ETH_CFG_SW_PHY_SWAP;
738 t |= AR933X_ETH_CFG_SW_PHY_ADDR_SWAP;
739 __raw_writel(t, base + AR933X_GMAC_REG_ETH_CFG);
744 void __init ath79_setup_ar934x_eth_cfg(u32 mask)
749 base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
751 t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
753 t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 |
754 AR934X_ETH_CFG_MII_GMAC0 |
755 AR934X_ETH_CFG_GMII_GMAC0 |
756 AR934X_ETH_CFG_SW_ONLY_MODE |
757 AR934X_ETH_CFG_SW_PHY_SWAP);
761 __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
763 __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
768 static int ath79_eth_instance __initdata;
769 void __init ath79_register_eth(unsigned int id)
771 struct platform_device *pdev;
772 struct ag71xx_platform_data *pdata;
776 printk(KERN_ERR "ar71xx: invalid ethernet id %d\n", id);
780 ath79_init_eth_pll_data(id);
783 pdev = &ath79_eth0_device;
785 pdev = &ath79_eth1_device;
787 pdata = pdev->dev.platform_data;
789 pdata->max_frame_len = 1540;
790 pdata->desc_pktlen_mask = 0xfff;
792 err = ath79_setup_phy_if_mode(id, pdata);
795 "ar71xx: invalid PHY interface mode for GE%u\n", id);
800 case ATH79_SOC_AR7130:
802 pdata->ddr_flush = ath79_ddr_flush_ge0;
803 pdata->set_speed = ath79_set_speed_ge0;
805 pdata->ddr_flush = ath79_ddr_flush_ge1;
806 pdata->set_speed = ath79_set_speed_ge1;
810 case ATH79_SOC_AR7141:
811 case ATH79_SOC_AR7161:
813 pdata->ddr_flush = ath79_ddr_flush_ge0;
814 pdata->set_speed = ath79_set_speed_ge0;
816 pdata->ddr_flush = ath79_ddr_flush_ge1;
817 pdata->set_speed = ath79_set_speed_ge1;
822 case ATH79_SOC_AR7242:
824 pdata->reset_bit |= AR724X_RESET_GE0_MDIO |
825 AR71XX_RESET_GE0_PHY;
826 pdata->ddr_flush = ar724x_ddr_flush_ge0;
827 pdata->set_speed = ar7242_set_speed_ge0;
829 pdata->reset_bit |= AR724X_RESET_GE1_MDIO |
830 AR71XX_RESET_GE1_PHY;
831 pdata->ddr_flush = ar724x_ddr_flush_ge1;
832 pdata->set_speed = ath79_set_speed_dummy;
835 pdata->is_ar724x = 1;
837 if (!pdata->fifo_cfg1)
838 pdata->fifo_cfg1 = 0x0010ffff;
839 if (!pdata->fifo_cfg2)
840 pdata->fifo_cfg2 = 0x015500aa;
841 if (!pdata->fifo_cfg3)
842 pdata->fifo_cfg3 = 0x01f00140;
845 case ATH79_SOC_AR7241:
847 pdata->reset_bit |= AR724X_RESET_GE0_MDIO;
849 pdata->reset_bit |= AR724X_RESET_GE1_MDIO;
851 case ATH79_SOC_AR7240:
853 pdata->reset_bit |= AR71XX_RESET_GE0_PHY;
854 pdata->ddr_flush = ar724x_ddr_flush_ge0;
855 pdata->set_speed = ath79_set_speed_dummy;
857 pdata->phy_mask = BIT(4);
859 pdata->reset_bit |= AR71XX_RESET_GE1_PHY;
860 pdata->ddr_flush = ar724x_ddr_flush_ge1;
861 pdata->set_speed = ath79_set_speed_dummy;
863 pdata->speed = SPEED_1000;
864 pdata->duplex = DUPLEX_FULL;
865 pdata->switch_data = &ath79_switch_data;
867 ath79_switch_data.phy_poll_mask |= BIT(4);
870 pdata->is_ar724x = 1;
871 if (ath79_soc == ATH79_SOC_AR7240)
872 pdata->is_ar7240 = 1;
874 if (!pdata->fifo_cfg1)
875 pdata->fifo_cfg1 = 0x0010ffff;
876 if (!pdata->fifo_cfg2)
877 pdata->fifo_cfg2 = 0x015500aa;
878 if (!pdata->fifo_cfg3)
879 pdata->fifo_cfg3 = 0x01f00140;
882 case ATH79_SOC_AR9130:
884 pdata->ddr_flush = ar91xx_ddr_flush_ge0;
885 pdata->set_speed = ar91xx_set_speed_ge0;
887 pdata->ddr_flush = ar91xx_ddr_flush_ge1;
888 pdata->set_speed = ar91xx_set_speed_ge1;
890 pdata->is_ar91xx = 1;
893 case ATH79_SOC_AR9132:
895 pdata->ddr_flush = ar91xx_ddr_flush_ge0;
896 pdata->set_speed = ar91xx_set_speed_ge0;
898 pdata->ddr_flush = ar91xx_ddr_flush_ge1;
899 pdata->set_speed = ar91xx_set_speed_ge1;
901 pdata->is_ar91xx = 1;
905 case ATH79_SOC_AR9330:
906 case ATH79_SOC_AR9331:
908 pdata->reset_bit = AR933X_RESET_GE0_MAC |
909 AR933X_RESET_GE0_MDIO;
910 pdata->ddr_flush = ar933x_ddr_flush_ge0;
911 pdata->set_speed = ath79_set_speed_dummy;
913 pdata->phy_mask = BIT(4);
915 pdata->reset_bit = AR933X_RESET_GE1_MAC |
916 AR933X_RESET_GE1_MDIO;
917 pdata->ddr_flush = ar933x_ddr_flush_ge1;
918 pdata->set_speed = ath79_set_speed_dummy;
920 pdata->speed = SPEED_1000;
921 pdata->duplex = DUPLEX_FULL;
922 pdata->switch_data = &ath79_switch_data;
924 ath79_switch_data.phy_poll_mask |= BIT(4);
928 pdata->is_ar724x = 1;
930 if (!pdata->fifo_cfg1)
931 pdata->fifo_cfg1 = 0x0010ffff;
932 if (!pdata->fifo_cfg2)
933 pdata->fifo_cfg2 = 0x015500aa;
934 if (!pdata->fifo_cfg3)
935 pdata->fifo_cfg3 = 0x01f00140;
938 case ATH79_SOC_AR9341:
939 case ATH79_SOC_AR9342:
940 case ATH79_SOC_AR9344:
942 pdata->reset_bit = AR934X_RESET_GE0_MAC |
943 AR934X_RESET_GE0_MDIO;
944 pdata->set_speed = ar934x_set_speed_ge0;
946 pdata->reset_bit = AR934X_RESET_GE1_MAC |
947 AR934X_RESET_GE1_MDIO;
948 pdata->set_speed = ath79_set_speed_dummy;
950 pdata->switch_data = &ath79_switch_data;
952 /* reset the built-in switch */
953 ath79_device_reset_set(AR934X_RESET_ETH_SWITCH);
954 ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH);
957 pdata->ddr_flush = ath79_ddr_no_flush;
959 pdata->is_ar724x = 1;
961 if (!pdata->fifo_cfg1)
962 pdata->fifo_cfg1 = 0x0010ffff;
963 if (!pdata->fifo_cfg2)
964 pdata->fifo_cfg2 = 0x015500aa;
965 if (!pdata->fifo_cfg3)
966 pdata->fifo_cfg3 = 0x01f00140;
969 case ATH79_SOC_QCA9556:
970 case ATH79_SOC_QCA9558:
972 pdata->reset_bit = QCA955X_RESET_GE0_MAC |
973 QCA955X_RESET_GE0_MDIO;
974 pdata->set_speed = qca955x_set_speed_xmii;
976 pdata->reset_bit = QCA955X_RESET_GE1_MAC |
977 QCA955X_RESET_GE1_MDIO;
978 pdata->set_speed = qca955x_set_speed_sgmii;
981 pdata->ddr_flush = ath79_ddr_no_flush;
983 pdata->is_ar724x = 1;
985 if (!pdata->fifo_cfg1)
986 pdata->fifo_cfg1 = 0x0010ffff;
987 if (!pdata->fifo_cfg2)
988 pdata->fifo_cfg2 = 0x015500aa;
989 if (!pdata->fifo_cfg3)
990 pdata->fifo_cfg3 = 0x01f00140;
997 switch (pdata->phy_if_mode) {
998 case PHY_INTERFACE_MODE_GMII:
999 case PHY_INTERFACE_MODE_RGMII:
1000 case PHY_INTERFACE_MODE_SGMII:
1001 if (!pdata->has_gbit) {
1002 printk(KERN_ERR "ar71xx: no gbit available on eth%d\n",
1011 if (!is_valid_ether_addr(pdata->mac_addr)) {
1012 random_ether_addr(pdata->mac_addr);
1014 "ar71xx: using random MAC address for eth%d\n",
1015 ath79_eth_instance);
1018 if (pdata->mii_bus_dev == NULL) {
1019 switch (ath79_soc) {
1020 case ATH79_SOC_AR9341:
1021 case ATH79_SOC_AR9342:
1022 case ATH79_SOC_AR9344:
1024 pdata->mii_bus_dev = &ath79_mdio0_device.dev;
1026 pdata->mii_bus_dev = &ath79_mdio1_device.dev;
1029 case ATH79_SOC_AR7241:
1030 case ATH79_SOC_AR9330:
1031 case ATH79_SOC_AR9331:
1032 pdata->mii_bus_dev = &ath79_mdio1_device.dev;
1035 case ATH79_SOC_QCA9556:
1036 case ATH79_SOC_QCA9558:
1037 /* don't assign any MDIO device by default */
1041 pdata->mii_bus_dev = &ath79_mdio0_device.dev;
1046 /* Reset the device */
1047 ath79_device_reset_set(pdata->reset_bit);
1050 ath79_device_reset_clear(pdata->reset_bit);
1053 platform_device_register(pdev);
1054 ath79_eth_instance++;
1057 void __init ath79_set_mac_base(unsigned char *mac)
1059 memcpy(ath79_mac_base, mac, ETH_ALEN);
1062 void __init ath79_parse_ascii_mac(char *mac_str, u8 *mac)
1066 t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
1067 &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5]);
1070 t = sscanf(mac_str, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
1071 &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5]);
1073 if (t != ETH_ALEN || !is_valid_ether_addr(mac)) {
1074 memset(mac, 0, ETH_ALEN);
1075 printk(KERN_DEBUG "ar71xx: invalid mac address \"%s\"\n",
1080 static void __init ath79_set_mac_base_ascii(char *str)
1084 ath79_parse_ascii_mac(str, mac);
1085 ath79_set_mac_base(mac);
1088 static int __init ath79_ethaddr_setup(char *str)
1090 ath79_set_mac_base_ascii(str);
1093 __setup("ethaddr=", ath79_ethaddr_setup);
1095 static int __init ath79_kmac_setup(char *str)
1097 ath79_set_mac_base_ascii(str);
1100 __setup("kmac=", ath79_kmac_setup);
1102 void __init ath79_init_mac(unsigned char *dst, const unsigned char *src,
1110 if (!src || !is_valid_ether_addr(src)) {
1111 memset(dst, '\0', ETH_ALEN);
1115 t = (((u32) src[3]) << 16) + (((u32) src[4]) << 8) + ((u32) src[5]);
1121 dst[3] = (t >> 16) & 0xff;
1122 dst[4] = (t >> 8) & 0xff;
1126 void __init ath79_init_local_mac(unsigned char *dst, const unsigned char *src)
1133 if (!src || !is_valid_ether_addr(src)) {
1134 memset(dst, '\0', ETH_ALEN);
1138 for (i = 0; i < ETH_ALEN; i++)