2 * Atheros AR71xx SoC platform devices
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
8 * Parts of this file are based on Atheros 2.6.15 BSP
9 * Parts of this file are based on Atheros 2.6.31 BSP
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/etherdevice.h>
20 #include <linux/platform_device.h>
21 #include <linux/serial_8250.h>
23 #include <asm/mach-ath79/ath79.h>
24 #include <asm/mach-ath79/ar71xx_regs.h>
25 #include <asm/mach-ath79/irq.h>
30 unsigned char ath79_mac_base[ETH_ALEN] __initdata;
32 static struct resource ath79_mdio0_resources[] = {
35 .flags = IORESOURCE_MEM,
36 .start = AR71XX_GE0_BASE,
37 .end = AR71XX_GE0_BASE + 0x200 - 1,
41 static struct ag71xx_mdio_platform_data ath79_mdio0_data;
43 struct platform_device ath79_mdio0_device = {
44 .name = "ag71xx-mdio",
46 .resource = ath79_mdio0_resources,
47 .num_resources = ARRAY_SIZE(ath79_mdio0_resources),
49 .platform_data = &ath79_mdio0_data,
53 static struct resource ath79_mdio1_resources[] = {
56 .flags = IORESOURCE_MEM,
57 .start = AR71XX_GE1_BASE,
58 .end = AR71XX_GE1_BASE + 0x200 - 1,
62 static struct ag71xx_mdio_platform_data ath79_mdio1_data;
64 struct platform_device ath79_mdio1_device = {
65 .name = "ag71xx-mdio",
67 .resource = ath79_mdio1_resources,
68 .num_resources = ARRAY_SIZE(ath79_mdio1_resources),
70 .platform_data = &ath79_mdio1_data,
74 static void ath79_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift)
79 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
81 t = __raw_readl(base + cfg_reg);
84 __raw_writel(t, base + cfg_reg);
87 __raw_writel(pll_val, base + pll_reg);
90 __raw_writel(t, base + cfg_reg);
94 __raw_writel(t, base + cfg_reg);
97 printk(KERN_DEBUG "ar71xx: pll_reg %#x: %#x\n",
98 (unsigned int)(base + pll_reg), __raw_readl(base + pll_reg));
103 static void __init ath79_mii_ctrl_set_if(unsigned int reg,
109 base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
111 t = __raw_readl(base + reg);
112 t &= ~(AR71XX_MII_CTRL_IF_MASK);
113 t |= (mii_if & AR71XX_MII_CTRL_IF_MASK);
114 __raw_writel(t, base + reg);
119 static void ath79_mii_ctrl_set_speed(unsigned int reg, unsigned int speed)
122 unsigned int mii_speed;
127 mii_speed = AR71XX_MII_CTRL_SPEED_10;
130 mii_speed = AR71XX_MII_CTRL_SPEED_100;
133 mii_speed = AR71XX_MII_CTRL_SPEED_1000;
139 base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
141 t = __raw_readl(base + reg);
142 t &= ~(AR71XX_MII_CTRL_SPEED_MASK << AR71XX_MII_CTRL_SPEED_SHIFT);
143 t |= mii_speed << AR71XX_MII_CTRL_SPEED_SHIFT;
144 __raw_writel(t, base + reg);
149 void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
151 struct platform_device *mdio_dev;
152 struct ag71xx_mdio_platform_data *mdio_data;
155 if (ath79_soc == ATH79_SOC_AR9341 ||
156 ath79_soc == ATH79_SOC_AR9342 ||
157 ath79_soc == ATH79_SOC_AR9344)
163 printk(KERN_ERR "ar71xx: invalid MDIO id %u\n", id);
168 case ATH79_SOC_AR7241:
169 case ATH79_SOC_AR9330:
170 case ATH79_SOC_AR9331:
171 mdio_dev = &ath79_mdio1_device;
172 mdio_data = &ath79_mdio1_data;
175 case ATH79_SOC_AR9341:
176 case ATH79_SOC_AR9342:
177 case ATH79_SOC_AR9344:
179 mdio_dev = &ath79_mdio0_device;
180 mdio_data = &ath79_mdio0_data;
182 mdio_dev = &ath79_mdio1_device;
183 mdio_data = &ath79_mdio1_data;
187 case ATH79_SOC_AR7242:
188 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG,
189 AR7242_PLL_REG_ETH0_INT_CLOCK, 0x62000000,
190 AR71XX_ETH0_PLL_SHIFT);
193 mdio_dev = &ath79_mdio0_device;
194 mdio_data = &ath79_mdio0_data;
198 mdio_data->phy_mask = phy_mask;
201 case ATH79_SOC_AR7240:
202 case ATH79_SOC_AR7241:
203 case ATH79_SOC_AR9330:
204 case ATH79_SOC_AR9331:
205 mdio_data->is_ar7240 = 1;
208 case ATH79_SOC_AR9341:
209 case ATH79_SOC_AR9342:
210 case ATH79_SOC_AR9344:
212 mdio_data->is_ar7240 = 1;
219 platform_device_register(mdio_dev);
222 struct ath79_eth_pll_data ath79_eth0_pll_data;
223 struct ath79_eth_pll_data ath79_eth1_pll_data;
225 static u32 ath79_get_eth_pll(unsigned int mac, int speed)
227 struct ath79_eth_pll_data *pll_data;
232 pll_data = &ath79_eth0_pll_data;
235 pll_data = &ath79_eth1_pll_data;
243 pll_val = pll_data->pll_10;
246 pll_val = pll_data->pll_100;
249 pll_val = pll_data->pll_1000;
258 static void ath79_set_speed_ge0(int speed)
260 u32 val = ath79_get_eth_pll(0, speed);
262 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK,
263 val, AR71XX_ETH0_PLL_SHIFT);
264 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
267 static void ath79_set_speed_ge1(int speed)
269 u32 val = ath79_get_eth_pll(1, speed);
271 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK,
272 val, AR71XX_ETH1_PLL_SHIFT);
273 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
276 static void ar724x_set_speed_ge0(int speed)
281 static void ar724x_set_speed_ge1(int speed)
286 static void ar7242_set_speed_ge0(int speed)
288 u32 val = ath79_get_eth_pll(0, speed);
291 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
292 __raw_writel(val, base + AR7242_PLL_REG_ETH0_INT_CLOCK);
296 static void ar91xx_set_speed_ge0(int speed)
298 u32 val = ath79_get_eth_pll(0, speed);
300 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH0_INT_CLOCK,
301 val, AR913X_ETH0_PLL_SHIFT);
302 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
305 static void ar91xx_set_speed_ge1(int speed)
307 u32 val = ath79_get_eth_pll(1, speed);
309 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH1_INT_CLOCK,
310 val, AR913X_ETH1_PLL_SHIFT);
311 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
314 static void ar933x_set_speed_ge0(int speed)
319 static void ar933x_set_speed_ge1(int speed)
324 static void ar934x_set_speed_ge0(int speed)
329 static void ar934x_set_speed_ge1(int speed)
334 static void ath79_ddr_no_flush(void)
338 static void ath79_ddr_flush_ge0(void)
340 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE0);
343 static void ath79_ddr_flush_ge1(void)
345 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE1);
348 static void ar724x_ddr_flush_ge0(void)
350 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE0);
353 static void ar724x_ddr_flush_ge1(void)
355 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE1);
358 static void ar91xx_ddr_flush_ge0(void)
360 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE0);
363 static void ar91xx_ddr_flush_ge1(void)
365 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE1);
368 static void ar933x_ddr_flush_ge0(void)
370 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE0);
373 static void ar933x_ddr_flush_ge1(void)
375 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE1);
378 static struct resource ath79_eth0_resources[] = {
381 .flags = IORESOURCE_MEM,
382 .start = AR71XX_GE0_BASE,
383 .end = AR71XX_GE0_BASE + 0x200 - 1,
386 .flags = IORESOURCE_IRQ,
387 .start = ATH79_CPU_IRQ_GE0,
388 .end = ATH79_CPU_IRQ_GE0,
392 struct ag71xx_platform_data ath79_eth0_data = {
393 .reset_bit = AR71XX_RESET_GE0_MAC,
396 struct platform_device ath79_eth0_device = {
399 .resource = ath79_eth0_resources,
400 .num_resources = ARRAY_SIZE(ath79_eth0_resources),
402 .platform_data = &ath79_eth0_data,
406 static struct resource ath79_eth1_resources[] = {
409 .flags = IORESOURCE_MEM,
410 .start = AR71XX_GE1_BASE,
411 .end = AR71XX_GE1_BASE + 0x200 - 1,
414 .flags = IORESOURCE_IRQ,
415 .start = ATH79_CPU_IRQ_GE1,
416 .end = ATH79_CPU_IRQ_GE1,
420 struct ag71xx_platform_data ath79_eth1_data = {
421 .reset_bit = AR71XX_RESET_GE1_MAC,
424 struct platform_device ath79_eth1_device = {
427 .resource = ath79_eth1_resources,
428 .num_resources = ARRAY_SIZE(ath79_eth1_resources),
430 .platform_data = &ath79_eth1_data,
434 struct ag71xx_switch_platform_data ath79_switch_data;
436 #define AR71XX_PLL_VAL_1000 0x00110000
437 #define AR71XX_PLL_VAL_100 0x00001099
438 #define AR71XX_PLL_VAL_10 0x00991099
440 #define AR724X_PLL_VAL_1000 0x00110000
441 #define AR724X_PLL_VAL_100 0x00001099
442 #define AR724X_PLL_VAL_10 0x00991099
444 #define AR7242_PLL_VAL_1000 0x16000000
445 #define AR7242_PLL_VAL_100 0x00000101
446 #define AR7242_PLL_VAL_10 0x00001616
448 #define AR913X_PLL_VAL_1000 0x1a000000
449 #define AR913X_PLL_VAL_100 0x13000a44
450 #define AR913X_PLL_VAL_10 0x00441099
452 #define AR933X_PLL_VAL_1000 0x00110000
453 #define AR933X_PLL_VAL_100 0x00001099
454 #define AR933X_PLL_VAL_10 0x00991099
456 #define AR934X_PLL_VAL_1000 0x00110000
457 #define AR934X_PLL_VAL_100 0x00001099
458 #define AR934X_PLL_VAL_10 0x00991099
460 static void __init ath79_init_eth_pll_data(unsigned int id)
462 struct ath79_eth_pll_data *pll_data;
463 u32 pll_10, pll_100, pll_1000;
467 pll_data = &ath79_eth0_pll_data;
470 pll_data = &ath79_eth1_pll_data;
477 case ATH79_SOC_AR7130:
478 case ATH79_SOC_AR7141:
479 case ATH79_SOC_AR7161:
480 pll_10 = AR71XX_PLL_VAL_10;
481 pll_100 = AR71XX_PLL_VAL_100;
482 pll_1000 = AR71XX_PLL_VAL_1000;
485 case ATH79_SOC_AR7240:
486 case ATH79_SOC_AR7241:
487 pll_10 = AR724X_PLL_VAL_10;
488 pll_100 = AR724X_PLL_VAL_100;
489 pll_1000 = AR724X_PLL_VAL_1000;
492 case ATH79_SOC_AR7242:
493 pll_10 = AR7242_PLL_VAL_10;
494 pll_100 = AR7242_PLL_VAL_100;
495 pll_1000 = AR7242_PLL_VAL_1000;
498 case ATH79_SOC_AR9130:
499 case ATH79_SOC_AR9132:
500 pll_10 = AR913X_PLL_VAL_10;
501 pll_100 = AR913X_PLL_VAL_100;
502 pll_1000 = AR913X_PLL_VAL_1000;
505 case ATH79_SOC_AR9330:
506 case ATH79_SOC_AR9331:
507 pll_10 = AR933X_PLL_VAL_10;
508 pll_100 = AR933X_PLL_VAL_100;
509 pll_1000 = AR933X_PLL_VAL_1000;
512 case ATH79_SOC_AR9341:
513 case ATH79_SOC_AR9342:
514 case ATH79_SOC_AR9344:
515 pll_10 = AR934X_PLL_VAL_10;
516 pll_100 = AR934X_PLL_VAL_100;
517 pll_1000 = AR934X_PLL_VAL_1000;
524 if (!pll_data->pll_10)
525 pll_data->pll_10 = pll_10;
527 if (!pll_data->pll_100)
528 pll_data->pll_100 = pll_100;
530 if (!pll_data->pll_1000)
531 pll_data->pll_1000 = pll_1000;
534 static int __init ath79_setup_phy_if_mode(unsigned int id,
535 struct ag71xx_platform_data *pdata)
542 case ATH79_SOC_AR7130:
543 case ATH79_SOC_AR7141:
544 case ATH79_SOC_AR7161:
545 case ATH79_SOC_AR9130:
546 case ATH79_SOC_AR9132:
547 switch (pdata->phy_if_mode) {
548 case PHY_INTERFACE_MODE_MII:
549 mii_if = AR71XX_MII0_CTRL_IF_MII;
551 case PHY_INTERFACE_MODE_GMII:
552 mii_if = AR71XX_MII0_CTRL_IF_GMII;
554 case PHY_INTERFACE_MODE_RGMII:
555 mii_if = AR71XX_MII0_CTRL_IF_RGMII;
557 case PHY_INTERFACE_MODE_RMII:
558 mii_if = AR71XX_MII0_CTRL_IF_RMII;
563 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII0_CTRL, mii_if);
566 case ATH79_SOC_AR7240:
567 case ATH79_SOC_AR7241:
568 case ATH79_SOC_AR9330:
569 case ATH79_SOC_AR9331:
570 pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
573 case ATH79_SOC_AR7242:
576 case ATH79_SOC_AR9341:
577 case ATH79_SOC_AR9342:
578 case ATH79_SOC_AR9344:
579 switch (pdata->phy_if_mode) {
580 case PHY_INTERFACE_MODE_MII:
581 case PHY_INTERFACE_MODE_GMII:
582 case PHY_INTERFACE_MODE_RGMII:
583 case PHY_INTERFACE_MODE_RMII:
596 case ATH79_SOC_AR7130:
597 case ATH79_SOC_AR7141:
598 case ATH79_SOC_AR7161:
599 case ATH79_SOC_AR9130:
600 case ATH79_SOC_AR9132:
601 switch (pdata->phy_if_mode) {
602 case PHY_INTERFACE_MODE_RMII:
603 mii_if = AR71XX_MII1_CTRL_IF_RMII;
605 case PHY_INTERFACE_MODE_RGMII:
606 mii_if = AR71XX_MII1_CTRL_IF_RGMII;
611 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII1_CTRL, mii_if);
614 case ATH79_SOC_AR7240:
615 case ATH79_SOC_AR7241:
616 case ATH79_SOC_AR9330:
617 case ATH79_SOC_AR9331:
618 pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
621 case ATH79_SOC_AR7242:
624 case ATH79_SOC_AR9341:
625 case ATH79_SOC_AR9342:
626 case ATH79_SOC_AR9344:
627 switch (pdata->phy_if_mode) {
628 case PHY_INTERFACE_MODE_MII:
629 case PHY_INTERFACE_MODE_GMII:
645 static int ath79_eth_instance __initdata;
646 void __init ath79_register_eth(unsigned int id)
648 struct platform_device *pdev;
649 struct ag71xx_platform_data *pdata;
653 printk(KERN_ERR "ar71xx: invalid ethernet id %d\n", id);
657 ath79_init_eth_pll_data(id);
660 pdev = &ath79_eth0_device;
662 pdev = &ath79_eth1_device;
664 pdata = pdev->dev.platform_data;
666 err = ath79_setup_phy_if_mode(id, pdata);
669 "ar71xx: invalid PHY interface mode for GE%u\n", id);
674 case ATH79_SOC_AR7130:
676 pdata->ddr_flush = ath79_ddr_flush_ge0;
677 pdata->set_speed = ath79_set_speed_ge0;
679 pdata->ddr_flush = ath79_ddr_flush_ge1;
680 pdata->set_speed = ath79_set_speed_ge1;
684 case ATH79_SOC_AR7141:
685 case ATH79_SOC_AR7161:
687 pdata->ddr_flush = ath79_ddr_flush_ge0;
688 pdata->set_speed = ath79_set_speed_ge0;
690 pdata->ddr_flush = ath79_ddr_flush_ge1;
691 pdata->set_speed = ath79_set_speed_ge1;
696 case ATH79_SOC_AR7242:
698 pdata->reset_bit |= AR724X_RESET_GE0_MDIO |
699 AR71XX_RESET_GE0_PHY;
700 pdata->ddr_flush = ar724x_ddr_flush_ge0;
701 pdata->set_speed = ar7242_set_speed_ge0;
703 pdata->reset_bit |= AR724X_RESET_GE1_MDIO |
704 AR71XX_RESET_GE1_PHY;
705 pdata->ddr_flush = ar724x_ddr_flush_ge1;
706 pdata->set_speed = ar724x_set_speed_ge1;
709 pdata->is_ar724x = 1;
711 if (!pdata->fifo_cfg1)
712 pdata->fifo_cfg1 = 0x0010ffff;
713 if (!pdata->fifo_cfg2)
714 pdata->fifo_cfg2 = 0x015500aa;
715 if (!pdata->fifo_cfg3)
716 pdata->fifo_cfg3 = 0x01f00140;
719 case ATH79_SOC_AR7241:
721 pdata->reset_bit |= AR724X_RESET_GE0_MDIO;
723 pdata->reset_bit |= AR724X_RESET_GE1_MDIO;
725 case ATH79_SOC_AR7240:
727 pdata->reset_bit |= AR71XX_RESET_GE0_PHY;
728 pdata->ddr_flush = ar724x_ddr_flush_ge0;
729 pdata->set_speed = ar724x_set_speed_ge0;
731 pdata->phy_mask = BIT(4);
733 pdata->reset_bit |= AR71XX_RESET_GE1_PHY;
734 pdata->ddr_flush = ar724x_ddr_flush_ge1;
735 pdata->set_speed = ar724x_set_speed_ge1;
737 pdata->speed = SPEED_1000;
738 pdata->duplex = DUPLEX_FULL;
739 pdata->switch_data = &ath79_switch_data;
742 pdata->is_ar724x = 1;
743 if (ath79_soc == ATH79_SOC_AR7240)
744 pdata->is_ar7240 = 1;
746 if (!pdata->fifo_cfg1)
747 pdata->fifo_cfg1 = 0x0010ffff;
748 if (!pdata->fifo_cfg2)
749 pdata->fifo_cfg2 = 0x015500aa;
750 if (!pdata->fifo_cfg3)
751 pdata->fifo_cfg3 = 0x01f00140;
754 case ATH79_SOC_AR9130:
756 pdata->ddr_flush = ar91xx_ddr_flush_ge0;
757 pdata->set_speed = ar91xx_set_speed_ge0;
759 pdata->ddr_flush = ar91xx_ddr_flush_ge1;
760 pdata->set_speed = ar91xx_set_speed_ge1;
762 pdata->is_ar91xx = 1;
765 case ATH79_SOC_AR9132:
767 pdata->ddr_flush = ar91xx_ddr_flush_ge0;
768 pdata->set_speed = ar91xx_set_speed_ge0;
770 pdata->ddr_flush = ar91xx_ddr_flush_ge1;
771 pdata->set_speed = ar91xx_set_speed_ge1;
773 pdata->is_ar91xx = 1;
777 case ATH79_SOC_AR9330:
778 case ATH79_SOC_AR9331:
780 pdata->reset_bit = AR933X_RESET_GE0_MAC |
781 AR933X_RESET_GE0_MDIO;
782 pdata->ddr_flush = ar933x_ddr_flush_ge0;
783 pdata->set_speed = ar933x_set_speed_ge0;
785 pdata->phy_mask = BIT(4);
787 pdata->reset_bit = AR933X_RESET_GE1_MAC |
788 AR933X_RESET_GE1_MDIO;
789 pdata->ddr_flush = ar933x_ddr_flush_ge1;
790 pdata->set_speed = ar933x_set_speed_ge1;
792 pdata->speed = SPEED_1000;
793 pdata->duplex = DUPLEX_FULL;
794 pdata->switch_data = &ath79_switch_data;
798 pdata->is_ar724x = 1;
800 if (!pdata->fifo_cfg1)
801 pdata->fifo_cfg1 = 0x0010ffff;
802 if (!pdata->fifo_cfg2)
803 pdata->fifo_cfg2 = 0x015500aa;
804 if (!pdata->fifo_cfg3)
805 pdata->fifo_cfg3 = 0x01f00140;
808 case ATH79_SOC_AR9341:
809 case ATH79_SOC_AR9342:
810 case ATH79_SOC_AR9344:
812 pdata->reset_bit = AR934X_RESET_GE0_MAC |
813 AR934X_RESET_GE0_MDIO;
814 pdata->set_speed = ar934x_set_speed_ge0;
816 pdata->reset_bit = AR934X_RESET_GE1_MAC |
817 AR934X_RESET_GE1_MDIO;
818 pdata->set_speed = ar934x_set_speed_ge1;
820 pdata->switch_data = &ath79_switch_data;
823 pdata->ddr_flush = ath79_ddr_no_flush;
825 pdata->is_ar724x = 1;
827 if (!pdata->fifo_cfg1)
828 pdata->fifo_cfg1 = 0x0010ffff;
829 if (!pdata->fifo_cfg2)
830 pdata->fifo_cfg2 = 0x015500aa;
831 if (!pdata->fifo_cfg3)
832 pdata->fifo_cfg3 = 0x01f00140;
839 switch (pdata->phy_if_mode) {
840 case PHY_INTERFACE_MODE_GMII:
841 case PHY_INTERFACE_MODE_RGMII:
842 if (!pdata->has_gbit) {
843 printk(KERN_ERR "ar71xx: no gbit available on eth%d\n",
852 if (!is_valid_ether_addr(pdata->mac_addr)) {
853 random_ether_addr(pdata->mac_addr);
855 "ar71xx: using random MAC address for eth%d\n",
859 if (pdata->mii_bus_dev == NULL) {
861 case ATH79_SOC_AR9341:
862 case ATH79_SOC_AR9342:
863 case ATH79_SOC_AR9344:
865 pdata->mii_bus_dev = &ath79_mdio0_device.dev;
867 pdata->mii_bus_dev = &ath79_mdio1_device.dev;
870 case ATH79_SOC_AR7241:
871 case ATH79_SOC_AR9330:
872 case ATH79_SOC_AR9331:
873 pdata->mii_bus_dev = &ath79_mdio1_device.dev;
877 pdata->mii_bus_dev = &ath79_mdio0_device.dev;
882 /* Reset the device */
883 ath79_device_reset_set(pdata->reset_bit);
886 ath79_device_reset_clear(pdata->reset_bit);
889 platform_device_register(pdev);
890 ath79_eth_instance++;
893 void __init ath79_set_mac_base(unsigned char *mac)
895 memcpy(ath79_mac_base, mac, ETH_ALEN);
898 void __init ath79_parse_mac_addr(char *mac_str)
903 t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
904 &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
907 t = sscanf(mac_str, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
908 &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
911 ath79_set_mac_base(tmp);
913 printk(KERN_DEBUG "ar71xx: failed to parse mac address "
914 "\"%s\"\n", mac_str);
917 static int __init ath79_ethaddr_setup(char *str)
919 ath79_parse_mac_addr(str);
922 __setup("ethaddr=", ath79_ethaddr_setup);
924 static int __init ath79_kmac_setup(char *str)
926 ath79_parse_mac_addr(str);
929 __setup("kmac=", ath79_kmac_setup);
931 void __init ath79_init_mac(unsigned char *dst, const unsigned char *src,
936 if (!is_valid_ether_addr(src)) {
937 memset(dst, '\0', ETH_ALEN);
941 t = (((u32) src[3]) << 16) + (((u32) src[4]) << 8) + ((u32) src[5]);
947 dst[3] = (t >> 16) & 0xff;
948 dst[4] = (t >> 8) & 0xff;
952 void __init ath79_init_local_mac(unsigned char *dst, const unsigned char *src)
956 if (!is_valid_ether_addr(src)) {
957 memset(dst, '\0', ETH_ALEN);
961 for (i = 0; i < ETH_ALEN; i++)