2 * Atheros AR71xx SoC platform devices
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
8 * Parts of this file are based on Atheros 2.6.15 BSP
9 * Parts of this file are based on Atheros 2.6.31 BSP
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/etherdevice.h>
20 #include <linux/platform_device.h>
21 #include <linux/serial_8250.h>
23 #include <asm/mach-ath79/ath79.h>
24 #include <asm/mach-ath79/ar71xx_regs.h>
25 #include <asm/mach-ath79/irq.h>
30 unsigned char ath79_mac_base[ETH_ALEN] __initdata;
32 static struct resource ath79_mdio0_resources[] = {
35 .flags = IORESOURCE_MEM,
36 .start = AR71XX_GE0_BASE,
37 .end = AR71XX_GE0_BASE + 0x200 - 1,
41 static struct ag71xx_mdio_platform_data ath79_mdio0_data;
43 struct platform_device ath79_mdio0_device = {
44 .name = "ag71xx-mdio",
46 .resource = ath79_mdio0_resources,
47 .num_resources = ARRAY_SIZE(ath79_mdio0_resources),
49 .platform_data = &ath79_mdio0_data,
53 static struct resource ath79_mdio1_resources[] = {
56 .flags = IORESOURCE_MEM,
57 .start = AR71XX_GE1_BASE,
58 .end = AR71XX_GE1_BASE + 0x200 - 1,
62 static struct ag71xx_mdio_platform_data ath79_mdio1_data;
64 struct platform_device ath79_mdio1_device = {
65 .name = "ag71xx-mdio",
67 .resource = ath79_mdio1_resources,
68 .num_resources = ARRAY_SIZE(ath79_mdio1_resources),
70 .platform_data = &ath79_mdio1_data,
74 static void ath79_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift)
79 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
81 t = __raw_readl(base + cfg_reg);
84 __raw_writel(t, base + cfg_reg);
87 __raw_writel(pll_val, base + pll_reg);
90 __raw_writel(t, base + cfg_reg);
94 __raw_writel(t, base + cfg_reg);
97 printk(KERN_DEBUG "ar71xx: pll_reg %#x: %#x\n",
98 (unsigned int)(base + pll_reg), __raw_readl(base + pll_reg));
103 static void __init ath79_mii_ctrl_set_if(unsigned int reg,
109 base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
111 t = __raw_readl(base + reg);
112 t &= ~(AR71XX_MII_CTRL_IF_MASK);
113 t |= (mii_if & AR71XX_MII_CTRL_IF_MASK);
114 __raw_writel(t, base + reg);
119 static void ath79_mii_ctrl_set_speed(unsigned int reg, unsigned int speed)
122 unsigned int mii_speed;
127 mii_speed = AR71XX_MII_CTRL_SPEED_10;
130 mii_speed = AR71XX_MII_CTRL_SPEED_100;
133 mii_speed = AR71XX_MII_CTRL_SPEED_1000;
139 base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
141 t = __raw_readl(base + reg);
142 t &= ~(AR71XX_MII_CTRL_SPEED_MASK << AR71XX_MII_CTRL_SPEED_SHIFT);
143 t |= mii_speed << AR71XX_MII_CTRL_SPEED_SHIFT;
144 __raw_writel(t, base + reg);
149 void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
151 struct platform_device *mdio_dev;
152 struct ag71xx_mdio_platform_data *mdio_data;
155 if (ath79_soc == ATH79_SOC_AR9341 ||
156 ath79_soc == ATH79_SOC_AR9342 ||
157 ath79_soc == ATH79_SOC_AR9344)
163 printk(KERN_ERR "ar71xx: invalid MDIO id %u\n", id);
168 case ATH79_SOC_AR7241:
169 case ATH79_SOC_AR9330:
170 case ATH79_SOC_AR9331:
171 mdio_dev = &ath79_mdio1_device;
172 mdio_data = &ath79_mdio1_data;
175 case ATH79_SOC_AR9341:
176 case ATH79_SOC_AR9342:
177 case ATH79_SOC_AR9344:
179 mdio_dev = &ath79_mdio0_device;
180 mdio_data = &ath79_mdio0_data;
182 mdio_dev = &ath79_mdio1_device;
183 mdio_data = &ath79_mdio1_data;
187 case ATH79_SOC_AR7242:
188 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG,
189 AR7242_PLL_REG_ETH0_INT_CLOCK, 0x62000000,
190 AR71XX_ETH0_PLL_SHIFT);
193 mdio_dev = &ath79_mdio0_device;
194 mdio_data = &ath79_mdio0_data;
198 mdio_data->phy_mask = phy_mask;
201 case ATH79_SOC_AR7240:
202 case ATH79_SOC_AR7241:
203 case ATH79_SOC_AR9330:
204 case ATH79_SOC_AR9331:
205 mdio_data->is_ar7240 = 1;
208 case ATH79_SOC_AR9341:
209 case ATH79_SOC_AR9342:
210 case ATH79_SOC_AR9344:
212 mdio_data->is_ar7240 = 1;
219 platform_device_register(mdio_dev);
222 struct ath79_eth_pll_data ath79_eth0_pll_data;
223 struct ath79_eth_pll_data ath79_eth1_pll_data;
225 static u32 ath79_get_eth_pll(unsigned int mac, int speed)
227 struct ath79_eth_pll_data *pll_data;
232 pll_data = &ath79_eth0_pll_data;
235 pll_data = &ath79_eth1_pll_data;
243 pll_val = pll_data->pll_10;
246 pll_val = pll_data->pll_100;
249 pll_val = pll_data->pll_1000;
258 static void ath79_set_speed_ge0(int speed)
260 u32 val = ath79_get_eth_pll(0, speed);
262 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK,
263 val, AR71XX_ETH0_PLL_SHIFT);
264 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
267 static void ath79_set_speed_ge1(int speed)
269 u32 val = ath79_get_eth_pll(1, speed);
271 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK,
272 val, AR71XX_ETH1_PLL_SHIFT);
273 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
276 static void ar724x_set_speed_ge0(int speed)
281 static void ar724x_set_speed_ge1(int speed)
286 static void ar7242_set_speed_ge0(int speed)
288 u32 val = ath79_get_eth_pll(0, speed);
291 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
292 __raw_writel(val, base + AR7242_PLL_REG_ETH0_INT_CLOCK);
296 static void ar91xx_set_speed_ge0(int speed)
298 u32 val = ath79_get_eth_pll(0, speed);
300 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH0_INT_CLOCK,
301 val, AR913X_ETH0_PLL_SHIFT);
302 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
305 static void ar91xx_set_speed_ge1(int speed)
307 u32 val = ath79_get_eth_pll(1, speed);
309 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH1_INT_CLOCK,
310 val, AR913X_ETH1_PLL_SHIFT);
311 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
314 static void ar933x_set_speed_ge0(int speed)
319 static void ar933x_set_speed_ge1(int speed)
324 static void ar934x_set_speed_ge0(int speed)
329 static void ar934x_set_speed_ge1(int speed)
334 static void ath79_ddr_flush_ge0(void)
336 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE0);
339 static void ath79_ddr_flush_ge1(void)
341 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE1);
344 static void ar724x_ddr_flush_ge0(void)
346 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE0);
349 static void ar724x_ddr_flush_ge1(void)
351 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE1);
354 static void ar91xx_ddr_flush_ge0(void)
356 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE0);
359 static void ar91xx_ddr_flush_ge1(void)
361 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE1);
364 static void ar933x_ddr_flush_ge0(void)
366 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE0);
369 static void ar933x_ddr_flush_ge1(void)
371 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE1);
374 static void ar934x_ddr_flush_ge0(void)
376 ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_GE0);
379 static void ar934x_ddr_flush_ge1(void)
381 ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_GE1);
384 static struct resource ath79_eth0_resources[] = {
387 .flags = IORESOURCE_MEM,
388 .start = AR71XX_GE0_BASE,
389 .end = AR71XX_GE0_BASE + 0x200 - 1,
392 .flags = IORESOURCE_IRQ,
393 .start = ATH79_CPU_IRQ_GE0,
394 .end = ATH79_CPU_IRQ_GE0,
398 struct ag71xx_platform_data ath79_eth0_data = {
399 .reset_bit = AR71XX_RESET_GE0_MAC,
402 struct platform_device ath79_eth0_device = {
405 .resource = ath79_eth0_resources,
406 .num_resources = ARRAY_SIZE(ath79_eth0_resources),
408 .platform_data = &ath79_eth0_data,
412 static struct resource ath79_eth1_resources[] = {
415 .flags = IORESOURCE_MEM,
416 .start = AR71XX_GE1_BASE,
417 .end = AR71XX_GE1_BASE + 0x200 - 1,
420 .flags = IORESOURCE_IRQ,
421 .start = ATH79_CPU_IRQ_GE1,
422 .end = ATH79_CPU_IRQ_GE1,
426 struct ag71xx_platform_data ath79_eth1_data = {
427 .reset_bit = AR71XX_RESET_GE1_MAC,
430 struct platform_device ath79_eth1_device = {
433 .resource = ath79_eth1_resources,
434 .num_resources = ARRAY_SIZE(ath79_eth1_resources),
436 .platform_data = &ath79_eth1_data,
440 struct ag71xx_switch_platform_data ath79_switch_data;
442 #define AR71XX_PLL_VAL_1000 0x00110000
443 #define AR71XX_PLL_VAL_100 0x00001099
444 #define AR71XX_PLL_VAL_10 0x00991099
446 #define AR724X_PLL_VAL_1000 0x00110000
447 #define AR724X_PLL_VAL_100 0x00001099
448 #define AR724X_PLL_VAL_10 0x00991099
450 #define AR7242_PLL_VAL_1000 0x16000000
451 #define AR7242_PLL_VAL_100 0x00000101
452 #define AR7242_PLL_VAL_10 0x00001616
454 #define AR913X_PLL_VAL_1000 0x1a000000
455 #define AR913X_PLL_VAL_100 0x13000a44
456 #define AR913X_PLL_VAL_10 0x00441099
458 #define AR933X_PLL_VAL_1000 0x00110000
459 #define AR933X_PLL_VAL_100 0x00001099
460 #define AR933X_PLL_VAL_10 0x00991099
462 #define AR934X_PLL_VAL_1000 0x00110000
463 #define AR934X_PLL_VAL_100 0x00001099
464 #define AR934X_PLL_VAL_10 0x00991099
466 static void __init ath79_init_eth_pll_data(unsigned int id)
468 struct ath79_eth_pll_data *pll_data;
469 u32 pll_10, pll_100, pll_1000;
473 pll_data = &ath79_eth0_pll_data;
476 pll_data = &ath79_eth1_pll_data;
483 case ATH79_SOC_AR7130:
484 case ATH79_SOC_AR7141:
485 case ATH79_SOC_AR7161:
486 pll_10 = AR71XX_PLL_VAL_10;
487 pll_100 = AR71XX_PLL_VAL_100;
488 pll_1000 = AR71XX_PLL_VAL_1000;
491 case ATH79_SOC_AR7240:
492 case ATH79_SOC_AR7241:
493 pll_10 = AR724X_PLL_VAL_10;
494 pll_100 = AR724X_PLL_VAL_100;
495 pll_1000 = AR724X_PLL_VAL_1000;
498 case ATH79_SOC_AR7242:
499 pll_10 = AR7242_PLL_VAL_10;
500 pll_100 = AR7242_PLL_VAL_100;
501 pll_1000 = AR7242_PLL_VAL_1000;
504 case ATH79_SOC_AR9130:
505 case ATH79_SOC_AR9132:
506 pll_10 = AR913X_PLL_VAL_10;
507 pll_100 = AR913X_PLL_VAL_100;
508 pll_1000 = AR913X_PLL_VAL_1000;
511 case ATH79_SOC_AR9330:
512 case ATH79_SOC_AR9331:
513 pll_10 = AR933X_PLL_VAL_10;
514 pll_100 = AR933X_PLL_VAL_100;
515 pll_1000 = AR933X_PLL_VAL_1000;
518 case ATH79_SOC_AR9341:
519 case ATH79_SOC_AR9342:
520 case ATH79_SOC_AR9344:
521 pll_10 = AR934X_PLL_VAL_10;
522 pll_100 = AR934X_PLL_VAL_100;
523 pll_1000 = AR934X_PLL_VAL_1000;
530 if (!pll_data->pll_10)
531 pll_data->pll_10 = pll_10;
533 if (!pll_data->pll_100)
534 pll_data->pll_100 = pll_100;
536 if (!pll_data->pll_1000)
537 pll_data->pll_1000 = pll_1000;
540 static int __init ath79_setup_phy_if_mode(unsigned int id,
541 struct ag71xx_platform_data *pdata)
548 case ATH79_SOC_AR7130:
549 case ATH79_SOC_AR7141:
550 case ATH79_SOC_AR7161:
551 case ATH79_SOC_AR9130:
552 case ATH79_SOC_AR9132:
553 switch (pdata->phy_if_mode) {
554 case PHY_INTERFACE_MODE_MII:
555 mii_if = AR71XX_MII0_CTRL_IF_MII;
557 case PHY_INTERFACE_MODE_GMII:
558 mii_if = AR71XX_MII0_CTRL_IF_GMII;
560 case PHY_INTERFACE_MODE_RGMII:
561 mii_if = AR71XX_MII0_CTRL_IF_RGMII;
563 case PHY_INTERFACE_MODE_RMII:
564 mii_if = AR71XX_MII0_CTRL_IF_RMII;
569 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII0_CTRL, mii_if);
572 case ATH79_SOC_AR7240:
573 case ATH79_SOC_AR7241:
574 case ATH79_SOC_AR9330:
575 case ATH79_SOC_AR9331:
576 pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
579 case ATH79_SOC_AR7242:
582 case ATH79_SOC_AR9341:
583 case ATH79_SOC_AR9342:
584 case ATH79_SOC_AR9344:
585 switch (pdata->phy_if_mode) {
586 case PHY_INTERFACE_MODE_MII:
587 case PHY_INTERFACE_MODE_GMII:
588 case PHY_INTERFACE_MODE_RGMII:
589 case PHY_INTERFACE_MODE_RMII:
602 case ATH79_SOC_AR7130:
603 case ATH79_SOC_AR7141:
604 case ATH79_SOC_AR7161:
605 case ATH79_SOC_AR9130:
606 case ATH79_SOC_AR9132:
607 switch (pdata->phy_if_mode) {
608 case PHY_INTERFACE_MODE_RMII:
609 mii_if = AR71XX_MII1_CTRL_IF_RMII;
611 case PHY_INTERFACE_MODE_RGMII:
612 mii_if = AR71XX_MII1_CTRL_IF_RGMII;
617 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII1_CTRL, mii_if);
620 case ATH79_SOC_AR7240:
621 case ATH79_SOC_AR7241:
622 case ATH79_SOC_AR9330:
623 case ATH79_SOC_AR9331:
624 pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
627 case ATH79_SOC_AR7242:
630 case ATH79_SOC_AR9341:
631 case ATH79_SOC_AR9342:
632 case ATH79_SOC_AR9344:
633 switch (pdata->phy_if_mode) {
634 case PHY_INTERFACE_MODE_MII:
635 case PHY_INTERFACE_MODE_GMII:
651 static int ath79_eth_instance __initdata;
652 void __init ath79_register_eth(unsigned int id)
654 struct platform_device *pdev;
655 struct ag71xx_platform_data *pdata;
659 printk(KERN_ERR "ar71xx: invalid ethernet id %d\n", id);
663 ath79_init_eth_pll_data(id);
666 pdev = &ath79_eth0_device;
668 pdev = &ath79_eth1_device;
670 pdata = pdev->dev.platform_data;
672 err = ath79_setup_phy_if_mode(id, pdata);
675 "ar71xx: invalid PHY interface mode for GE%u\n", id);
680 case ATH79_SOC_AR7130:
682 pdata->ddr_flush = ath79_ddr_flush_ge0;
683 pdata->set_speed = ath79_set_speed_ge0;
685 pdata->ddr_flush = ath79_ddr_flush_ge1;
686 pdata->set_speed = ath79_set_speed_ge1;
690 case ATH79_SOC_AR7141:
691 case ATH79_SOC_AR7161:
693 pdata->ddr_flush = ath79_ddr_flush_ge0;
694 pdata->set_speed = ath79_set_speed_ge0;
696 pdata->ddr_flush = ath79_ddr_flush_ge1;
697 pdata->set_speed = ath79_set_speed_ge1;
702 case ATH79_SOC_AR7242:
704 pdata->reset_bit |= AR724X_RESET_GE0_MDIO |
705 AR71XX_RESET_GE0_PHY;
706 pdata->ddr_flush = ar724x_ddr_flush_ge0;
707 pdata->set_speed = ar7242_set_speed_ge0;
709 pdata->reset_bit |= AR724X_RESET_GE1_MDIO |
710 AR71XX_RESET_GE1_PHY;
711 pdata->ddr_flush = ar724x_ddr_flush_ge1;
712 pdata->set_speed = ar724x_set_speed_ge1;
715 pdata->is_ar724x = 1;
717 if (!pdata->fifo_cfg1)
718 pdata->fifo_cfg1 = 0x0010ffff;
719 if (!pdata->fifo_cfg2)
720 pdata->fifo_cfg2 = 0x015500aa;
721 if (!pdata->fifo_cfg3)
722 pdata->fifo_cfg3 = 0x01f00140;
725 case ATH79_SOC_AR7241:
727 pdata->reset_bit |= AR724X_RESET_GE0_MDIO;
729 pdata->reset_bit |= AR724X_RESET_GE1_MDIO;
731 case ATH79_SOC_AR7240:
733 pdata->reset_bit |= AR71XX_RESET_GE0_PHY;
734 pdata->ddr_flush = ar724x_ddr_flush_ge0;
735 pdata->set_speed = ar724x_set_speed_ge0;
737 pdata->phy_mask = BIT(4);
739 pdata->reset_bit |= AR71XX_RESET_GE1_PHY;
740 pdata->ddr_flush = ar724x_ddr_flush_ge1;
741 pdata->set_speed = ar724x_set_speed_ge1;
743 pdata->speed = SPEED_1000;
744 pdata->duplex = DUPLEX_FULL;
745 pdata->switch_data = &ath79_switch_data;
748 pdata->is_ar724x = 1;
749 if (ath79_soc == ATH79_SOC_AR7240)
750 pdata->is_ar7240 = 1;
752 if (!pdata->fifo_cfg1)
753 pdata->fifo_cfg1 = 0x0010ffff;
754 if (!pdata->fifo_cfg2)
755 pdata->fifo_cfg2 = 0x015500aa;
756 if (!pdata->fifo_cfg3)
757 pdata->fifo_cfg3 = 0x01f00140;
760 case ATH79_SOC_AR9130:
762 pdata->ddr_flush = ar91xx_ddr_flush_ge0;
763 pdata->set_speed = ar91xx_set_speed_ge0;
765 pdata->ddr_flush = ar91xx_ddr_flush_ge1;
766 pdata->set_speed = ar91xx_set_speed_ge1;
768 pdata->is_ar91xx = 1;
771 case ATH79_SOC_AR9132:
773 pdata->ddr_flush = ar91xx_ddr_flush_ge0;
774 pdata->set_speed = ar91xx_set_speed_ge0;
776 pdata->ddr_flush = ar91xx_ddr_flush_ge1;
777 pdata->set_speed = ar91xx_set_speed_ge1;
779 pdata->is_ar91xx = 1;
783 case ATH79_SOC_AR9330:
784 case ATH79_SOC_AR9331:
786 pdata->reset_bit = AR933X_RESET_GE0_MAC |
787 AR933X_RESET_GE0_MDIO;
788 pdata->ddr_flush = ar933x_ddr_flush_ge0;
789 pdata->set_speed = ar933x_set_speed_ge0;
791 pdata->phy_mask = BIT(4);
793 pdata->reset_bit = AR933X_RESET_GE1_MAC |
794 AR933X_RESET_GE1_MDIO;
795 pdata->ddr_flush = ar933x_ddr_flush_ge1;
796 pdata->set_speed = ar933x_set_speed_ge1;
798 pdata->speed = SPEED_1000;
799 pdata->duplex = DUPLEX_FULL;
800 pdata->switch_data = &ath79_switch_data;
804 pdata->is_ar724x = 1;
806 if (!pdata->fifo_cfg1)
807 pdata->fifo_cfg1 = 0x0010ffff;
808 if (!pdata->fifo_cfg2)
809 pdata->fifo_cfg2 = 0x015500aa;
810 if (!pdata->fifo_cfg3)
811 pdata->fifo_cfg3 = 0x01f00140;
814 case ATH79_SOC_AR9341:
815 case ATH79_SOC_AR9342:
816 case ATH79_SOC_AR9344:
818 pdata->reset_bit = AR934X_RESET_GE0_MAC |
819 AR934X_RESET_GE0_MDIO;
820 pdata->ddr_flush =ar934x_ddr_flush_ge0;
821 pdata->set_speed = ar934x_set_speed_ge0;
823 pdata->reset_bit = AR934X_RESET_GE1_MAC |
824 AR934X_RESET_GE1_MDIO;
825 pdata->ddr_flush = ar934x_ddr_flush_ge1;
826 pdata->set_speed = ar934x_set_speed_ge1;
828 pdata->switch_data = &ath79_switch_data;
832 pdata->is_ar724x = 1;
834 if (!pdata->fifo_cfg1)
835 pdata->fifo_cfg1 = 0x0010ffff;
836 if (!pdata->fifo_cfg2)
837 pdata->fifo_cfg2 = 0x015500aa;
838 if (!pdata->fifo_cfg3)
839 pdata->fifo_cfg3 = 0x01f00140;
846 switch (pdata->phy_if_mode) {
847 case PHY_INTERFACE_MODE_GMII:
848 case PHY_INTERFACE_MODE_RGMII:
849 if (!pdata->has_gbit) {
850 printk(KERN_ERR "ar71xx: no gbit available on eth%d\n",
859 if (!is_valid_ether_addr(pdata->mac_addr)) {
860 random_ether_addr(pdata->mac_addr);
862 "ar71xx: using random MAC address for eth%d\n",
866 if (pdata->mii_bus_dev == NULL) {
868 case ATH79_SOC_AR9341:
869 case ATH79_SOC_AR9342:
870 case ATH79_SOC_AR9344:
872 pdata->mii_bus_dev = &ath79_mdio0_device.dev;
874 pdata->mii_bus_dev = &ath79_mdio1_device.dev;
877 case ATH79_SOC_AR7241:
878 case ATH79_SOC_AR9330:
879 case ATH79_SOC_AR9331:
880 pdata->mii_bus_dev = &ath79_mdio1_device.dev;
884 pdata->mii_bus_dev = &ath79_mdio0_device.dev;
889 /* Reset the device */
890 ath79_device_reset_set(pdata->reset_bit);
893 ath79_device_reset_clear(pdata->reset_bit);
896 platform_device_register(pdev);
897 ath79_eth_instance++;
900 void __init ath79_set_mac_base(unsigned char *mac)
902 memcpy(ath79_mac_base, mac, ETH_ALEN);
905 void __init ath79_parse_mac_addr(char *mac_str)
910 t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
911 &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
914 t = sscanf(mac_str, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
915 &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
918 ath79_set_mac_base(tmp);
920 printk(KERN_DEBUG "ar71xx: failed to parse mac address "
921 "\"%s\"\n", mac_str);
924 static int __init ath79_ethaddr_setup(char *str)
926 ath79_parse_mac_addr(str);
929 __setup("ethaddr=", ath79_ethaddr_setup);
931 static int __init ath79_kmac_setup(char *str)
933 ath79_parse_mac_addr(str);
936 __setup("kmac=", ath79_kmac_setup);
938 void __init ath79_init_mac(unsigned char *dst, const unsigned char *src,
943 if (!is_valid_ether_addr(src)) {
944 memset(dst, '\0', ETH_ALEN);
948 t = (((u32) src[3]) << 16) + (((u32) src[4]) << 8) + ((u32) src[5]);
954 dst[3] = (t >> 16) & 0xff;
955 dst[4] = (t >> 8) & 0xff;
959 void __init ath79_init_local_mac(unsigned char *dst, const unsigned char *src)
963 if (!is_valid_ether_addr(src)) {
964 memset(dst, '\0', ETH_ALEN);
968 for (i = 0; i < ETH_ALEN; i++)