target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c

   1 /*
   2  *  Atheros AR71xx SoC platform devices
   3  *
   4  *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
   5  *  Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
   6  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   7  *
   8  *  Parts of this file are based on Atheros 2.6.15 BSP
   9  *  Parts of this file are based on Atheros 2.6.31 BSP
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License version 2 as published
  13  *  by the Free Software Foundation.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/delay.h>
  19 #include <linux/etherdevice.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/serial_8250.h>
  22 #include <linux/clk.h>
  23 #include <linux/sizes.h>
  24
  25 #include <asm/mach-ath79/ath79.h>
  26 #include <asm/mach-ath79/ar71xx_regs.h>
  27 #include <asm/mach-ath79/irq.h>
  28
  29 #include "common.h"
  30 #include "dev-eth.h"
  31
  32 unsigned char ath79_mac_base[ETH_ALEN] __initdata;
  33
  34 static struct resource ath79_mdio0_resources[] = {
  35         {
  36                 .name   = "mdio_base",
  37                 .flags  = IORESOURCE_MEM,
  38                 .start  = AR71XX_GE0_BASE,
  39                 .end    = AR71XX_GE0_BASE + 0x200 - 1,
  40         }
  41 };
  42
  43 struct ag71xx_mdio_platform_data ath79_mdio0_data;
  44
  45 struct platform_device ath79_mdio0_device = {
  46         .name           = "ag71xx-mdio",
  47         .id             = 0,
  48         .resource       = ath79_mdio0_resources,
  49         .num_resources  = ARRAY_SIZE(ath79_mdio0_resources),
  50         .dev = {
  51                 .platform_data = &ath79_mdio0_data,
  52         },
  53 };
  54
  55 static struct resource ath79_mdio1_resources[] = {
  56         {
  57                 .name   = "mdio_base",
  58                 .flags  = IORESOURCE_MEM,
  59                 .start  = AR71XX_GE1_BASE,
  60                 .end    = AR71XX_GE1_BASE + 0x200 - 1,
  61         }
  62 };
  63
  64 struct ag71xx_mdio_platform_data ath79_mdio1_data;
  65
  66 struct platform_device ath79_mdio1_device = {
  67         .name           = "ag71xx-mdio",
  68         .id             = 1,
  69         .resource       = ath79_mdio1_resources,
  70         .num_resources  = ARRAY_SIZE(ath79_mdio1_resources),
  71         .dev = {
  72                 .platform_data = &ath79_mdio1_data,
  73         },
  74 };
  75
  76 static void ath79_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift)
  77 {
  78         void __iomem *base;
  79         u32 t;
  80
  81         base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
  82
  83         t = __raw_readl(base + cfg_reg);
  84         t &= ~(3 << shift);
  85         t |=  (2 << shift);
  86         __raw_writel(t, base + cfg_reg);
  87         udelay(100);
  88
  89         __raw_writel(pll_val, base + pll_reg);
  90
  91         t |= (3 << shift);
  92         __raw_writel(t, base + cfg_reg);
  93         udelay(100);
  94
  95         t &= ~(3 << shift);
  96         __raw_writel(t, base + cfg_reg);
  97         udelay(100);
  98
  99         printk(KERN_DEBUG "ar71xx: pll_reg %#x: %#x\n",
 100                 (unsigned int)(base + pll_reg), __raw_readl(base + pll_reg));
 101
 102         iounmap(base);
 103 }
 104
 105 static void __init ath79_mii_ctrl_set_if(unsigned int reg,
 106                                           unsigned int mii_if)
 107 {
 108         void __iomem *base;
 109         u32 t;
 110
 111         base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
 112
 113         t = __raw_readl(base + reg);
 114         t &= ~(AR71XX_MII_CTRL_IF_MASK);
 115         t |= (mii_if & AR71XX_MII_CTRL_IF_MASK);
 116         __raw_writel(t, base + reg);
 117
 118         iounmap(base);
 119 }
 120
 121 static void ath79_mii_ctrl_set_speed(unsigned int reg, unsigned int speed)
 122 {
 123         void __iomem *base;
 124         unsigned int mii_speed;
 125         u32 t;
 126
 127         switch (speed) {
 128         case SPEED_10:
 129                 mii_speed =  AR71XX_MII_CTRL_SPEED_10;
 130                 break;
 131         case SPEED_100:
 132                 mii_speed =  AR71XX_MII_CTRL_SPEED_100;
 133                 break;
 134         case SPEED_1000:
 135                 mii_speed =  AR71XX_MII_CTRL_SPEED_1000;
 136                 break;
 137         default:
 138                 BUG();
 139         }
 140
 141         base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
 142
 143         t = __raw_readl(base + reg);
 144         t &= ~(AR71XX_MII_CTRL_SPEED_MASK << AR71XX_MII_CTRL_SPEED_SHIFT);
 145         t |= mii_speed  << AR71XX_MII_CTRL_SPEED_SHIFT;
 146         __raw_writel(t, base + reg);
 147
 148         iounmap(base);
 149 }
 150
 151 static unsigned long ar934x_get_mdio_ref_clock(void)
 152 {
 153         void __iomem *base;
 154         unsigned long ret;
 155         u32 t;
 156
 157         base = ioremap(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
 158
 159         ret = 0;
 160         t = __raw_readl(base + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
 161         if (t & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL) {
 162                 ret = 100 * 1000 * 1000;
 163         } else {
 164                 struct clk *clk;
 165
 166                 clk = clk_get(NULL, "ref");
 167                 if (!IS_ERR(clk))
 168                         ret = clk_get_rate(clk);
 169         }
 170
 171         iounmap(base);
 172
 173         return ret;
 174 }
 175
 176 void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
 177 {
 178         struct platform_device *mdio_dev;
 179         struct ag71xx_mdio_platform_data *mdio_data;
 180         unsigned int max_id;
 181
 182         if (ath79_soc == ATH79_SOC_AR9341 ||
 183             ath79_soc == ATH79_SOC_AR9342 ||
 184             ath79_soc == ATH79_SOC_AR9344 ||
 185             ath79_soc == ATH79_SOC_QCA9556 ||
 186             ath79_soc == ATH79_SOC_QCA9558 ||
 187             ath79_soc == ATH79_SOC_QCA956X)
 188                 max_id = 1;
 189         else
 190                 max_id = 0;
 191
 192         if (id > max_id) {
 193                 printk(KERN_ERR "ar71xx: invalid MDIO id %u\n", id);
 194                 return;
 195         }
 196
 197         switch (ath79_soc) {
 198         case ATH79_SOC_AR7241:
 199         case ATH79_SOC_AR9330:
 200         case ATH79_SOC_AR9331:
 201         case ATH79_SOC_QCA9533:
 202         case ATH79_SOC_TP9343:
 203                 mdio_dev = &ath79_mdio1_device;
 204                 mdio_data = &ath79_mdio1_data;
 205                 break;
 206
 207         case ATH79_SOC_AR9341:
 208         case ATH79_SOC_AR9342:
 209         case ATH79_SOC_AR9344:
 210         case ATH79_SOC_QCA9556:
 211         case ATH79_SOC_QCA9558:
 212         case ATH79_SOC_QCA956X:
 213                 if (id == 0) {
 214                         mdio_dev = &ath79_mdio0_device;
 215                         mdio_data = &ath79_mdio0_data;
 216                 } else {
 217                         mdio_dev = &ath79_mdio1_device;
 218                         mdio_data = &ath79_mdio1_data;
 219                 }
 220                 break;
 221
 222         case ATH79_SOC_AR7242:
 223                 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG,
 224                                AR7242_PLL_REG_ETH0_INT_CLOCK, 0x62000000,
 225                                AR71XX_ETH0_PLL_SHIFT);
 226                 /* fall through */
 227         default:
 228                 mdio_dev = &ath79_mdio0_device;
 229                 mdio_data = &ath79_mdio0_data;
 230                 break;
 231         }
 232
 233         mdio_data->phy_mask = phy_mask;
 234
 235         switch (ath79_soc) {
 236         case ATH79_SOC_AR7240:
 237                 mdio_data->is_ar7240 = 1;
 238                 /* fall through */
 239         case ATH79_SOC_AR7241:
 240                 mdio_data->builtin_switch = 1;
 241                 break;
 242
 243         case ATH79_SOC_AR9330:
 244                 mdio_data->is_ar9330 = 1;
 245                 /* fall through */
 246         case ATH79_SOC_AR9331:
 247                 mdio_data->builtin_switch = 1;
 248                 break;
 249
 250         case ATH79_SOC_AR9341:
 251         case ATH79_SOC_AR9342:
 252         case ATH79_SOC_AR9344:
 253                 if (id == 1) {
 254                         mdio_data->builtin_switch = 1;
 255                         mdio_data->ref_clock = ar934x_get_mdio_ref_clock();
 256                         mdio_data->mdio_clock = 6250000;
 257                 }
 258                 mdio_data->is_ar934x = 1;
 259                 break;
 260
 261         case ATH79_SOC_QCA9533:
 262         case ATH79_SOC_TP9343:
 263                 mdio_data->builtin_switch = 1;
 264                 break;
 265
 266         case ATH79_SOC_QCA9556:
 267         case ATH79_SOC_QCA9558:
 268                 mdio_data->is_ar934x = 1;
 269                 break;
 270
 271         case ATH79_SOC_QCA956X:
 272                 if (id == 1)
 273                         mdio_data->builtin_switch = 1;
 274                 mdio_data->is_ar934x = 1;
 275                 break;
 276
 277         default:
 278                 break;
 279         }
 280
 281         platform_device_register(mdio_dev);
 282 }
 283
 284 struct ath79_eth_pll_data ath79_eth0_pll_data;
 285 struct ath79_eth_pll_data ath79_eth1_pll_data;
 286
 287 static u32 ath79_get_eth_pll(unsigned int mac, int speed)
 288 {
 289         struct ath79_eth_pll_data *pll_data;
 290         u32 pll_val;
 291
 292         switch (mac) {
 293         case 0:
 294                 pll_data = &ath79_eth0_pll_data;
 295                 break;
 296         case 1:
 297                 pll_data = &ath79_eth1_pll_data;
 298                 break;
 299         default:
 300                 BUG();
 301         }
 302
 303         switch (speed) {
 304         case SPEED_10:
 305                 pll_val = pll_data->pll_10;
 306                 break;
 307         case SPEED_100:
 308                 pll_val = pll_data->pll_100;
 309                 break;
 310         case SPEED_1000:
 311                 pll_val = pll_data->pll_1000;
 312                 break;
 313         default:
 314                 BUG();
 315         }
 316
 317         return pll_val;
 318 }
 319
 320 static void ath79_set_speed_ge0(int speed)
 321 {
 322         u32 val = ath79_get_eth_pll(0, speed);
 323
 324         ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK,
 325                         val, AR71XX_ETH0_PLL_SHIFT);
 326         ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
 327 }
 328
 329 static void ath79_set_speed_ge1(int speed)
 330 {
 331         u32 val = ath79_get_eth_pll(1, speed);
 332
 333         ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK,
 334                          val, AR71XX_ETH1_PLL_SHIFT);
 335         ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
 336 }
 337
 338 static void ar7242_set_speed_ge0(int speed)
 339 {
 340         u32 val = ath79_get_eth_pll(0, speed);
 341         void __iomem *base;
 342
 343         base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
 344         __raw_writel(val, base + AR7242_PLL_REG_ETH0_INT_CLOCK);
 345         iounmap(base);
 346 }
 347
 348 static void ar91xx_set_speed_ge0(int speed)
 349 {
 350         u32 val = ath79_get_eth_pll(0, speed);
 351
 352         ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH0_INT_CLOCK,
 353                          val, AR913X_ETH0_PLL_SHIFT);
 354         ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
 355 }
 356
 357 static void ar91xx_set_speed_ge1(int speed)
 358 {
 359         u32 val = ath79_get_eth_pll(1, speed);
 360
 361         ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH1_INT_CLOCK,
 362                          val, AR913X_ETH1_PLL_SHIFT);
 363         ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
 364 }
 365
 366 static void ar934x_set_speed_ge0(int speed)
 367 {
 368         void __iomem *base;
 369         u32 val = ath79_get_eth_pll(0, speed);
 370
 371         base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
 372         __raw_writel(val, base + AR934X_PLL_ETH_XMII_CONTROL_REG);
 373         iounmap(base);
 374 }
 375
 376 static void qca955x_set_speed_xmii(int speed)
 377 {
 378         void __iomem *base;
 379         u32 val = ath79_get_eth_pll(0, speed);
 380
 381         base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
 382         __raw_writel(val, base + QCA955X_PLL_ETH_XMII_CONTROL_REG);
 383         iounmap(base);
 384 }
 385
 386 static void qca955x_set_speed_sgmii(int id, int speed)
 387 {
 388         void __iomem *base;
 389         u32 val = ath79_get_eth_pll(id, speed);
 390
 391         base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
 392         __raw_writel(val, base + QCA955X_PLL_ETH_SGMII_CONTROL_REG);
 393         iounmap(base);
 394 }
 395
 396 static void qca9556_set_speed_sgmii(int speed)
 397 {
 398         qca955x_set_speed_sgmii(0, speed);
 399 }
 400
 401 static void qca9558_set_speed_sgmii(int speed)
 402 {
 403         qca955x_set_speed_sgmii(1, speed);
 404 }
 405
 406 static void qca956x_set_speed_sgmii(int speed)
 407 {
 408         void __iomem *base;
 409         u32 val = ath79_get_eth_pll(0, speed);
 410
 411         base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
 412         __raw_writel(val, base + QCA955X_PLL_ETH_SGMII_CONTROL_REG);
 413         iounmap(base);
 414 }
 415
 416 static void ath79_set_speed_dummy(int speed)
 417 {
 418 }
 419
 420 static void ath79_ddr_flush_ge0(void)
 421 {
 422         ath79_ddr_wb_flush(0);
 423 }
 424
 425 static void ath79_ddr_flush_ge1(void)
 426 {
 427         ath79_ddr_wb_flush(1);
 428 }
 429
 430 static struct resource ath79_eth0_resources[] = {
 431         {
 432                 .name   = "mac_base",
 433                 .flags  = IORESOURCE_MEM,
 434                 .start  = AR71XX_GE0_BASE,
 435                 .end    = AR71XX_GE0_BASE + 0x200 - 1,
 436         }, {
 437                 .name   = "mac_irq",
 438                 .flags  = IORESOURCE_IRQ,
 439                 .start  = ATH79_CPU_IRQ(4),
 440                 .end    = ATH79_CPU_IRQ(4),
 441         },
 442 };
 443
 444 struct ag71xx_platform_data ath79_eth0_data = {
 445         .reset_bit      = AR71XX_RESET_GE0_MAC,
 446 };
 447
 448 struct platform_device ath79_eth0_device = {
 449         .name           = "ag71xx",
 450         .id             = 0,
 451         .resource       = ath79_eth0_resources,
 452         .num_resources  = ARRAY_SIZE(ath79_eth0_resources),
 453         .dev = {
 454                 .platform_data = &ath79_eth0_data,
 455         },
 456 };
 457
 458 static struct resource ath79_eth1_resources[] = {
 459         {
 460                 .name   = "mac_base",
 461                 .flags  = IORESOURCE_MEM,
 462                 .start  = AR71XX_GE1_BASE,
 463                 .end    = AR71XX_GE1_BASE + 0x200 - 1,
 464         }, {
 465                 .name   = "mac_irq",
 466                 .flags  = IORESOURCE_IRQ,
 467                 .start  = ATH79_CPU_IRQ(5),
 468                 .end    = ATH79_CPU_IRQ(5),
 469         },
 470 };
 471
 472 struct ag71xx_platform_data ath79_eth1_data = {
 473         .reset_bit      = AR71XX_RESET_GE1_MAC,
 474 };
 475
 476 struct platform_device ath79_eth1_device = {
 477         .name           = "ag71xx",
 478         .id             = 1,
 479         .resource       = ath79_eth1_resources,
 480         .num_resources  = ARRAY_SIZE(ath79_eth1_resources),
 481         .dev = {
 482                 .platform_data = &ath79_eth1_data,
 483         },
 484 };
 485
 486 struct ag71xx_switch_platform_data ath79_switch_data;
 487
 488 #define AR71XX_PLL_VAL_1000     0x00110000
 489 #define AR71XX_PLL_VAL_100      0x00001099
 490 #define AR71XX_PLL_VAL_10       0x00991099
 491
 492 #define AR724X_PLL_VAL_1000     0x00110000
 493 #define AR724X_PLL_VAL_100      0x00001099
 494 #define AR724X_PLL_VAL_10       0x00991099
 495
 496 #define AR7242_PLL_VAL_1000     0x16000000
 497 #define AR7242_PLL_VAL_100      0x00000101
 498 #define AR7242_PLL_VAL_10       0x00001616
 499
 500 #define AR913X_PLL_VAL_1000     0x1a000000
 501 #define AR913X_PLL_VAL_100      0x13000a44
 502 #define AR913X_PLL_VAL_10       0x00441099
 503
 504 #define AR933X_PLL_VAL_1000     0x00110000
 505 #define AR933X_PLL_VAL_100      0x00001099
 506 #define AR933X_PLL_VAL_10       0x00991099
 507
 508 #define AR934X_PLL_VAL_1000     0x16000000
 509 #define AR934X_PLL_VAL_100      0x00000101
 510 #define AR934X_PLL_VAL_10       0x00001616
 511
 512 #define QCA956X_PLL_VAL_1000    0x03000000
 513 #define QCA956X_PLL_VAL_100     0x00000101
 514 #define QCA956X_PLL_VAL_10      0x00001919
 515
 516 static void __init ath79_init_eth_pll_data(unsigned int id)
 517 {
 518         struct ath79_eth_pll_data *pll_data;
 519         u32 pll_10, pll_100, pll_1000;
 520
 521         switch (id) {
 522         case 0:
 523                 pll_data = &ath79_eth0_pll_data;
 524                 break;
 525         case 1:
 526                 pll_data = &ath79_eth1_pll_data;
 527                 break;
 528         default:
 529                 BUG();
 530         }
 531
 532         switch (ath79_soc) {
 533         case ATH79_SOC_AR7130:
 534         case ATH79_SOC_AR7141:
 535         case ATH79_SOC_AR7161:
 536                 pll_10 = AR71XX_PLL_VAL_10;
 537                 pll_100 = AR71XX_PLL_VAL_100;
 538                 pll_1000 = AR71XX_PLL_VAL_1000;
 539                 break;
 540
 541         case ATH79_SOC_AR7240:
 542         case ATH79_SOC_AR7241:
 543                 pll_10 = AR724X_PLL_VAL_10;
 544                 pll_100 = AR724X_PLL_VAL_100;
 545                 pll_1000 = AR724X_PLL_VAL_1000;
 546                 break;
 547
 548         case ATH79_SOC_AR7242:
 549                 pll_10 = AR7242_PLL_VAL_10;
 550                 pll_100 = AR7242_PLL_VAL_100;
 551                 pll_1000 = AR7242_PLL_VAL_1000;
 552                 break;
 553
 554         case ATH79_SOC_AR9130:
 555         case ATH79_SOC_AR9132:
 556                 pll_10 = AR913X_PLL_VAL_10;
 557                 pll_100 = AR913X_PLL_VAL_100;
 558                 pll_1000 = AR913X_PLL_VAL_1000;
 559                 break;
 560
 561         case ATH79_SOC_AR9330:
 562         case ATH79_SOC_AR9331:
 563                 pll_10 = AR933X_PLL_VAL_10;
 564                 pll_100 = AR933X_PLL_VAL_100;
 565                 pll_1000 = AR933X_PLL_VAL_1000;
 566                 break;
 567
 568         case ATH79_SOC_AR9341:
 569         case ATH79_SOC_AR9342:
 570         case ATH79_SOC_AR9344:
 571         case ATH79_SOC_QCA9533:
 572         case ATH79_SOC_QCA9556:
 573         case ATH79_SOC_QCA9558:
 574         case ATH79_SOC_TP9343:
 575                 pll_10 = AR934X_PLL_VAL_10;
 576                 pll_100 = AR934X_PLL_VAL_100;
 577                 pll_1000 = AR934X_PLL_VAL_1000;
 578                 break;
 579
 580         case ATH79_SOC_QCA956X:
 581                 pll_10 = QCA956X_PLL_VAL_10;
 582                 pll_100 = QCA956X_PLL_VAL_100;
 583                 pll_1000 = QCA956X_PLL_VAL_1000;
 584                 break;
 585
 586         default:
 587                 BUG();
 588         }
 589
 590         if (!pll_data->pll_10)
 591                 pll_data->pll_10 = pll_10;
 592
 593         if (!pll_data->pll_100)
 594                 pll_data->pll_100 = pll_100;
 595
 596         if (!pll_data->pll_1000)
 597                 pll_data->pll_1000 = pll_1000;
 598 }
 599
 600 static int __init ath79_setup_phy_if_mode(unsigned int id,
 601                                            struct ag71xx_platform_data *pdata)
 602 {
 603         unsigned int mii_if;
 604
 605         switch (id) {
 606         case 0:
 607                 switch (ath79_soc) {
 608                 case ATH79_SOC_AR7130:
 609                 case ATH79_SOC_AR7141:
 610                 case ATH79_SOC_AR7161:
 611                 case ATH79_SOC_AR9130:
 612                 case ATH79_SOC_AR9132:
 613                         switch (pdata->phy_if_mode) {
 614                         case PHY_INTERFACE_MODE_MII:
 615                                 mii_if = AR71XX_MII0_CTRL_IF_MII;
 616                                 break;
 617                         case PHY_INTERFACE_MODE_GMII:
 618                                 mii_if = AR71XX_MII0_CTRL_IF_GMII;
 619                                 break;
 620                         case PHY_INTERFACE_MODE_RGMII:
 621                                 mii_if = AR71XX_MII0_CTRL_IF_RGMII;
 622                                 break;
 623                         case PHY_INTERFACE_MODE_RMII:
 624                                 mii_if = AR71XX_MII0_CTRL_IF_RMII;
 625                                 break;
 626                         default:
 627                                 return -EINVAL;
 628                         }
 629                         ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII0_CTRL, mii_if);
 630                         break;
 631
 632                 case ATH79_SOC_AR7240:
 633                 case ATH79_SOC_AR7241:
 634                 case ATH79_SOC_AR9330:
 635                 case ATH79_SOC_AR9331:
 636                 case ATH79_SOC_QCA9533:
 637                 case ATH79_SOC_TP9343:
 638                         pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
 639                         break;
 640
 641                 case ATH79_SOC_AR7242:
 642                         /* FIXME */
 643
 644                 case ATH79_SOC_AR9341:
 645                 case ATH79_SOC_AR9342:
 646                 case ATH79_SOC_AR9344:
 647                         switch (pdata->phy_if_mode) {
 648                         case PHY_INTERFACE_MODE_MII:
 649                         case PHY_INTERFACE_MODE_GMII:
 650                         case PHY_INTERFACE_MODE_RGMII:
 651                         case PHY_INTERFACE_MODE_RMII:
 652                                 break;
 653                         default:
 654                                 return -EINVAL;
 655                         }
 656                         break;
 657
 658                 case ATH79_SOC_QCA9556:
 659                 case ATH79_SOC_QCA9558:
 660                 case ATH79_SOC_QCA956X:
 661                         switch (pdata->phy_if_mode) {
 662                         case PHY_INTERFACE_MODE_MII:
 663                         case PHY_INTERFACE_MODE_RGMII:
 664                         case PHY_INTERFACE_MODE_SGMII:
 665                                 break;
 666                         default:
 667                                 return -EINVAL;
 668                         }
 669                         break;
 670
 671                 default:
 672                         BUG();
 673                 }
 674                 break;
 675         case 1:
 676                 switch (ath79_soc) {
 677                 case ATH79_SOC_AR7130:
 678                 case ATH79_SOC_AR7141:
 679                 case ATH79_SOC_AR7161:
 680                 case ATH79_SOC_AR9130:
 681                 case ATH79_SOC_AR9132:
 682                         switch (pdata->phy_if_mode) {
 683                         case PHY_INTERFACE_MODE_RMII:
 684                                 mii_if = AR71XX_MII1_CTRL_IF_RMII;
 685                                 break;
 686                         case PHY_INTERFACE_MODE_RGMII:
 687                                 mii_if = AR71XX_MII1_CTRL_IF_RGMII;
 688                                 break;
 689                         default:
 690                                 return -EINVAL;
 691                         }
 692                         ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII1_CTRL, mii_if);
 693                         break;
 694
 695                 case ATH79_SOC_AR7240:
 696                 case ATH79_SOC_AR7241:
 697                 case ATH79_SOC_AR9330:
 698                 case ATH79_SOC_AR9331:
 699                 case ATH79_SOC_TP9343:
 700                         pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
 701                         break;
 702
 703                 case ATH79_SOC_AR7242:
 704                         /* FIXME */
 705
 706                 case ATH79_SOC_AR9341:
 707                 case ATH79_SOC_AR9342:
 708                 case ATH79_SOC_AR9344:
 709                 case ATH79_SOC_QCA9533:
 710                 case ATH79_SOC_QCA956X:
 711                         switch (pdata->phy_if_mode) {
 712                         case PHY_INTERFACE_MODE_MII:
 713                         case PHY_INTERFACE_MODE_GMII:
 714                                 break;
 715                         default:
 716                                 return -EINVAL;
 717                         }
 718                         break;
 719
 720                 case ATH79_SOC_QCA9556:
 721                 case ATH79_SOC_QCA9558:
 722                         switch (pdata->phy_if_mode) {
 723                         case PHY_INTERFACE_MODE_MII:
 724                         case PHY_INTERFACE_MODE_RGMII:
 725                         case PHY_INTERFACE_MODE_SGMII:
 726                                 break;
 727                         default:
 728                                 return -EINVAL;
 729                         }
 730                         break;
 731
 732                 default:
 733                         BUG();
 734                 }
 735                 break;
 736         }
 737
 738         return 0;
 739 }
 740
 741 void __init ath79_setup_ar933x_phy4_switch(bool mac, bool mdio)
 742 {
 743         void __iomem *base;
 744         u32 t;
 745
 746         base = ioremap(AR933X_GMAC_BASE, AR933X_GMAC_SIZE);
 747
 748         t = __raw_readl(base + AR933X_GMAC_REG_ETH_CFG);
 749         t &= ~(AR933X_ETH_CFG_SW_PHY_SWAP | AR933X_ETH_CFG_SW_PHY_ADDR_SWAP);
 750         if (mac)
 751                 t |= AR933X_ETH_CFG_SW_PHY_SWAP;
 752         if (mdio)
 753                 t |= AR933X_ETH_CFG_SW_PHY_ADDR_SWAP;
 754         __raw_writel(t, base + AR933X_GMAC_REG_ETH_CFG);
 755
 756         iounmap(base);
 757 }
 758
 759 void __init ath79_setup_ar934x_eth_cfg(u32 mask)
 760 {
 761         void __iomem *base;
 762         u32 t;
 763
 764         base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
 765
 766         t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
 767
 768         t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 |
 769                AR934X_ETH_CFG_MII_GMAC0 |
 770                AR934X_ETH_CFG_GMII_GMAC0 |
 771                AR934X_ETH_CFG_SW_ONLY_MODE |
 772                AR934X_ETH_CFG_SW_PHY_SWAP);
 773
 774         t |= mask;
 775
 776         __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
 777         /* flush write */
 778         __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
 779
 780         iounmap(base);
 781 }
 782
 783 void __init ath79_setup_ar934x_eth_rx_delay(unsigned int rxd,
 784                                             unsigned int rxdv)
 785 {
 786         void __iomem *base;
 787         u32 t;
 788
 789         rxd &= AR934X_ETH_CFG_RXD_DELAY_MASK;
 790         rxdv &= AR934X_ETH_CFG_RDV_DELAY_MASK;
 791
 792         base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
 793
 794         t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
 795
 796         t &= ~(AR934X_ETH_CFG_RXD_DELAY_MASK << AR934X_ETH_CFG_RXD_DELAY_SHIFT |
 797                AR934X_ETH_CFG_RDV_DELAY_MASK << AR934X_ETH_CFG_RDV_DELAY_SHIFT);
 798
 799         t |= (rxd << AR934X_ETH_CFG_RXD_DELAY_SHIFT |
 800               rxdv << AR934X_ETH_CFG_RDV_DELAY_SHIFT);
 801
 802         __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
 803         /* flush write */
 804         __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
 805
 806         iounmap(base);
 807 }
 808
 809 void __init ath79_setup_qca955x_eth_cfg(u32 mask)
 810 {
 811         void __iomem *base;
 812         u32 t;
 813
 814         base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
 815
 816         t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);
 817
 818         t &= ~(QCA955X_ETH_CFG_RGMII_EN | QCA955X_ETH_CFG_GE0_SGMII);
 819
 820         t |= mask;
 821
 822         __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
 823
 824         iounmap(base);
 825 }
 826
 827 void __init ath79_setup_qca956x_eth_cfg(u32 mask)
 828 {
 829         void __iomem *base;
 830         u32 t;
 831
 832         base = ioremap(QCA956X_GMAC_BASE, QCA956X_GMAC_SIZE);
 833
 834         t = __raw_readl(base + QCA956X_GMAC_REG_ETH_CFG);
 835
 836         t &= ~(QCA956X_ETH_CFG_SW_ONLY_MODE |
 837                QCA956X_ETH_CFG_SW_PHY_SWAP);
 838
 839         t |= mask;
 840
 841         __raw_writel(t, base + QCA956X_GMAC_REG_ETH_CFG);
 842         /* flush write */
 843         __raw_readl(base + QCA956X_GMAC_REG_ETH_CFG);
 844
 845         iounmap(base);
 846 }
 847
 848 static int ath79_eth_instance __initdata;
 849 void __init ath79_register_eth(unsigned int id)
 850 {
 851         struct platform_device *pdev;
 852         struct ag71xx_platform_data *pdata;
 853         int err;
 854
 855         if (id > 1) {
 856                 printk(KERN_ERR "ar71xx: invalid ethernet id %d\n", id);
 857                 return;
 858         }
 859
 860         ath79_init_eth_pll_data(id);
 861
 862         if (id == 0)
 863                 pdev = &ath79_eth0_device;
 864         else
 865                 pdev = &ath79_eth1_device;
 866
 867         pdata = pdev->dev.platform_data;
 868
 869         pdata->max_frame_len = 1540;
 870         pdata->desc_pktlen_mask = 0xfff;
 871
 872         err = ath79_setup_phy_if_mode(id, pdata);
 873         if (err) {
 874                 printk(KERN_ERR
 875                        "ar71xx: invalid PHY interface mode for GE%u\n", id);
 876                 return;
 877         }
 878
 879         if (id == 0)
 880                 pdata->ddr_flush = ath79_ddr_flush_ge0;
 881         else
 882                 pdata->ddr_flush = ath79_ddr_flush_ge1;
 883
 884         switch (ath79_soc) {
 885         case ATH79_SOC_AR7130:
 886                 if (id == 0)
 887                         pdata->set_speed = ath79_set_speed_ge0;
 888                 else
 889                         pdata->set_speed = ath79_set_speed_ge1;
 890                 break;
 891
 892         case ATH79_SOC_AR7141:
 893         case ATH79_SOC_AR7161:
 894                 if (id == 0)
 895                         pdata->set_speed = ath79_set_speed_ge0;
 896                 else
 897                         pdata->set_speed = ath79_set_speed_ge1;
 898                 pdata->has_gbit = 1;
 899                 break;
 900
 901         case ATH79_SOC_AR7242:
 902                 if (id == 0) {
 903                         pdata->reset_bit |= AR724X_RESET_GE0_MDIO |
 904                                             AR71XX_RESET_GE0_PHY;
 905                         pdata->set_speed = ar7242_set_speed_ge0;
 906                 } else {
 907                         pdata->reset_bit |= AR724X_RESET_GE1_MDIO |
 908                                             AR71XX_RESET_GE1_PHY;
 909                         pdata->set_speed = ath79_set_speed_dummy;
 910                 }
 911                 pdata->has_gbit = 1;
 912                 pdata->is_ar724x = 1;
 913                 break;
 914
 915         case ATH79_SOC_AR7241:
 916                 if (id == 0)
 917                         pdata->reset_bit |= AR724X_RESET_GE0_MDIO;
 918                 else
 919                         pdata->reset_bit |= AR724X_RESET_GE1_MDIO;
 920                 /* fall through */
 921         case ATH79_SOC_AR7240:
 922                 if (id == 0) {
 923                         pdata->reset_bit |= AR71XX_RESET_GE0_PHY;
 924                         pdata->set_speed = ath79_set_speed_dummy;
 925
 926                         pdata->phy_mask = BIT(4);
 927                 } else {
 928                         pdata->reset_bit |= AR71XX_RESET_GE1_PHY;
 929                         pdata->set_speed = ath79_set_speed_dummy;
 930
 931                         pdata->speed = SPEED_1000;
 932                         pdata->duplex = DUPLEX_FULL;
 933                         pdata->switch_data = &ath79_switch_data;
 934                         pdata->use_flow_control = 1;
 935
 936                         ath79_switch_data.phy_poll_mask |= BIT(4);
 937                 }
 938                 pdata->has_gbit = 1;
 939                 pdata->is_ar724x = 1;
 940                 if (ath79_soc == ATH79_SOC_AR7240)
 941                         pdata->is_ar7240 = 1;
 942                 break;
 943
 944         case ATH79_SOC_AR9132:
 945                 pdata->has_gbit = 1;
 946                 /* fall through */
 947         case ATH79_SOC_AR9130:
 948                 if (id == 0)
 949                         pdata->set_speed = ar91xx_set_speed_ge0;
 950                 else
 951                         pdata->set_speed = ar91xx_set_speed_ge1;
 952                 pdata->is_ar91xx = 1;
 953                 break;
 954
 955         case ATH79_SOC_AR9330:
 956         case ATH79_SOC_AR9331:
 957                 if (id == 0) {
 958                         pdata->reset_bit = AR933X_RESET_GE0_MAC |
 959                                            AR933X_RESET_GE0_MDIO;
 960                         pdata->set_speed = ath79_set_speed_dummy;
 961
 962                         pdata->phy_mask = BIT(4);
 963                 } else {
 964                         pdata->reset_bit = AR933X_RESET_GE1_MAC |
 965                                            AR933X_RESET_GE1_MDIO;
 966                         pdata->set_speed = ath79_set_speed_dummy;
 967
 968                         pdata->speed = SPEED_1000;
 969                         pdata->has_gbit = 1;
 970                         pdata->duplex = DUPLEX_FULL;
 971                         pdata->switch_data = &ath79_switch_data;
 972                         pdata->use_flow_control = 1;
 973
 974                         ath79_switch_data.phy_poll_mask |= BIT(4);
 975                 }
 976
 977                 pdata->is_ar724x = 1;
 978                 break;
 979
 980         case ATH79_SOC_AR9341:
 981         case ATH79_SOC_AR9342:
 982         case ATH79_SOC_AR9344:
 983         case ATH79_SOC_QCA9533:
 984                 if (id == 0) {
 985                         pdata->reset_bit = AR934X_RESET_GE0_MAC |
 986                                            AR934X_RESET_GE0_MDIO;
 987                         pdata->set_speed = ar934x_set_speed_ge0;
 988
 989                         if (ath79_soc == ATH79_SOC_QCA9533)
 990                                 pdata->disable_inline_checksum_engine = 1;
 991                 } else {
 992                         pdata->reset_bit = AR934X_RESET_GE1_MAC |
 993                                            AR934X_RESET_GE1_MDIO;
 994                         pdata->set_speed = ath79_set_speed_dummy;
 995
 996                         pdata->switch_data = &ath79_switch_data;
 997
 998                         /* reset the built-in switch */
 999                         ath79_device_reset_set(AR934X_RESET_ETH_SWITCH);
1000                         ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH);
1001                 }
1002
1003                 pdata->has_gbit = 1;
1004                 pdata->is_ar724x = 1;
1005
1006                 pdata->max_frame_len = SZ_16K - 1;
1007                 pdata->desc_pktlen_mask = SZ_16K - 1;
1008                 break;
1009
1010         case ATH79_SOC_TP9343:
1011                 if (id == 0) {
1012                         pdata->reset_bit = AR933X_RESET_GE0_MAC |
1013                                            AR933X_RESET_GE0_MDIO;
1014                         pdata->set_speed = ath79_set_speed_dummy;
1015
1016                         if (!pdata->phy_mask)
1017                                 pdata->phy_mask = BIT(4);
1018                 } else {
1019                         pdata->reset_bit = AR933X_RESET_GE1_MAC |
1020                                            AR933X_RESET_GE1_MDIO;
1021                         pdata->set_speed = ath79_set_speed_dummy;
1022
1023                         pdata->speed = SPEED_1000;
1024                         pdata->duplex = DUPLEX_FULL;
1025                         pdata->switch_data = &ath79_switch_data;
1026                         pdata->use_flow_control = 1;
1027
1028                         ath79_switch_data.phy_poll_mask |= BIT(4);
1029                 }
1030
1031                 pdata->has_gbit = 1;
1032                 pdata->is_ar724x = 1;
1033                 break;
1034
1035         case ATH79_SOC_QCA9556:
1036         case ATH79_SOC_QCA9558:
1037                 if (id == 0) {
1038                         pdata->reset_bit = QCA955X_RESET_GE0_MAC |
1039                                            QCA955X_RESET_GE0_MDIO;
1040                         pdata->set_speed = qca955x_set_speed_xmii;
1041
1042                         /* QCA9556 only has SGMII interface */
1043                         if (ath79_soc == ATH79_SOC_QCA9556)
1044                                 pdata->set_speed = qca9556_set_speed_sgmii;
1045                 } else {
1046                         pdata->reset_bit = QCA955X_RESET_GE1_MAC |
1047                                            QCA955X_RESET_GE1_MDIO;
1048                         pdata->set_speed = qca9558_set_speed_sgmii;
1049                 }
1050
1051                 pdata->has_gbit = 1;
1052                 pdata->is_ar724x = 1;
1053
1054                 /*
1055                  * Limit the maximum frame length to 4095 bytes.
1056                  * Although the documentation says that the hardware
1057                  * limit is 16383 bytes but that does not work in
1058                  * practice. It seems that the hardware only updates
1059                  * the lowest 12 bits of the packet length field
1060                  * in the RX descriptor.
1061                  */
1062                 pdata->max_frame_len = SZ_4K - 1;
1063                 pdata->desc_pktlen_mask = SZ_16K - 1;
1064                 break;
1065
1066         case ATH79_SOC_QCA956X:
1067                 if (id == 0) {
1068                         pdata->reset_bit = QCA955X_RESET_GE0_MAC |
1069                                            QCA955X_RESET_GE0_MDIO;
1070
1071                         if (pdata->phy_if_mode == PHY_INTERFACE_MODE_SGMII)
1072                                 pdata->set_speed = qca956x_set_speed_sgmii;
1073                         else
1074                                 pdata->set_speed = ar934x_set_speed_ge0;
1075
1076                         pdata->disable_inline_checksum_engine = 1;
1077                 } else {
1078                         pdata->reset_bit = QCA955X_RESET_GE1_MAC |
1079                                            QCA955X_RESET_GE1_MDIO;
1080
1081                         pdata->set_speed = ath79_set_speed_dummy;
1082
1083                         pdata->switch_data = &ath79_switch_data;
1084
1085                         pdata->speed = SPEED_1000;
1086                         pdata->duplex = DUPLEX_FULL;
1087                         pdata->use_flow_control = 1;
1088
1089                         /* reset the built-in switch */
1090                         ath79_device_reset_set(AR934X_RESET_ETH_SWITCH);
1091                         ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH);
1092                 }
1093
1094                 pdata->has_gbit = 1;
1095                 pdata->is_ar724x = 1;
1096                 break;
1097
1098         default:
1099                 BUG();
1100         }
1101
1102         switch (pdata->phy_if_mode) {
1103         case PHY_INTERFACE_MODE_GMII:
1104         case PHY_INTERFACE_MODE_RGMII:
1105         case PHY_INTERFACE_MODE_SGMII:
1106                 if (!pdata->has_gbit) {
1107                         printk(KERN_ERR "ar71xx: no gbit available on eth%d\n",
1108                                         id);
1109                         return;
1110                 }
1111                 /* fallthrough */
1112         default:
1113                 break;
1114         }
1115
1116         if (!is_valid_ether_addr(pdata->mac_addr)) {
1117                 random_ether_addr(pdata->mac_addr);
1118                 printk(KERN_DEBUG
1119                         "ar71xx: using random MAC address for eth%d\n",
1120                         ath79_eth_instance);
1121         }
1122
1123         if (pdata->mii_bus_dev == NULL) {
1124                 switch (ath79_soc) {
1125                 case ATH79_SOC_AR9341:
1126                 case ATH79_SOC_AR9342:
1127                 case ATH79_SOC_AR9344:
1128                         if (id == 0)
1129                                 pdata->mii_bus_dev = &ath79_mdio0_device.dev;
1130                         else
1131                                 pdata->mii_bus_dev = &ath79_mdio1_device.dev;
1132                         break;
1133
1134                 case ATH79_SOC_AR7241:
1135                 case ATH79_SOC_AR9330:
1136                 case ATH79_SOC_AR9331:
1137                 case ATH79_SOC_QCA9533:
1138                 case ATH79_SOC_TP9343:
1139                         pdata->mii_bus_dev = &ath79_mdio1_device.dev;
1140                         break;
1141
1142                 case ATH79_SOC_QCA9556:
1143                 case ATH79_SOC_QCA9558:
1144                         /* don't assign any MDIO device by default */
1145                         break;
1146
1147                 case ATH79_SOC_QCA956X:
1148                         if (pdata->phy_if_mode != PHY_INTERFACE_MODE_SGMII)
1149                                 pdata->mii_bus_dev = &ath79_mdio1_device.dev;
1150                         break;
1151
1152                 default:
1153                         pdata->mii_bus_dev = &ath79_mdio0_device.dev;
1154                         break;
1155                 }
1156         }
1157
1158         /* Reset the device */
1159         ath79_device_reset_set(pdata->reset_bit);
1160         msleep(100);
1161
1162         ath79_device_reset_clear(pdata->reset_bit);
1163         msleep(100);
1164
1165         platform_device_register(pdev);
1166         ath79_eth_instance++;
1167 }
1168
1169 void __init ath79_set_mac_base(unsigned char *mac)
1170 {
1171         memcpy(ath79_mac_base, mac, ETH_ALEN);
1172 }
1173
1174 void __init ath79_parse_ascii_mac(char *mac_str, u8 *mac)
1175 {
1176         int t;
1177
1178         t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
1179                    &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5]);
1180
1181         if (t != ETH_ALEN)
1182                 t = sscanf(mac_str, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
1183                         &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5]);
1184
1185         if (t != ETH_ALEN || !is_valid_ether_addr(mac)) {
1186                 memset(mac, 0, ETH_ALEN);
1187                 printk(KERN_DEBUG "ar71xx: invalid mac address \"%s\"\n",
1188                        mac_str);
1189         }
1190 }
1191
1192 void __init ath79_extract_mac_reverse(u8 *ptr, u8 *out)
1193 {
1194         int i;
1195
1196         for (i = 0; i < ETH_ALEN; i++) {
1197                 out[i] = ptr[ETH_ALEN-i-1];
1198         }
1199 }
1200
1201 static void __init ath79_set_mac_base_ascii(char *str)
1202 {
1203         u8 mac[ETH_ALEN];
1204
1205         ath79_parse_ascii_mac(str, mac);
1206         ath79_set_mac_base(mac);
1207 }
1208
1209 static int __init ath79_ethaddr_setup(char *str)
1210 {
1211         ath79_set_mac_base_ascii(str);
1212         return 1;
1213 }
1214 __setup("ethaddr=", ath79_ethaddr_setup);
1215
1216 static int __init ath79_kmac_setup(char *str)
1217 {
1218         ath79_set_mac_base_ascii(str);
1219         return 1;
1220 }
1221 __setup("kmac=", ath79_kmac_setup);
1222
1223 void __init ath79_init_mac(unsigned char *dst, const unsigned char *src,
1224                             int offset)
1225 {
1226         int t;
1227
1228         if (!dst)
1229                 return;
1230
1231         if (!src || !is_valid_ether_addr(src)) {
1232                 memset(dst, '\0', ETH_ALEN);
1233                 return;
1234         }
1235
1236         t = (((u32) src[3]) << 16) + (((u32) src[4]) << 8) + ((u32) src[5]);
1237         t += offset;
1238
1239         dst[0] = src[0];
1240         dst[1] = src[1];
1241         dst[2] = src[2];
1242         dst[3] = (t >> 16) & 0xff;
1243         dst[4] = (t >> 8) & 0xff;
1244         dst[5] = t & 0xff;
1245 }
1246
1247 void __init ath79_init_local_mac(unsigned char *dst, const unsigned char *src)
1248 {
1249         int i;
1250
1251         if (!dst)
1252                 return;
1253
1254         if (!src || !is_valid_ether_addr(src)) {
1255                 memset(dst, '\0', ETH_ALEN);
1256                 return;
1257         }
1258
1259         for (i = 0; i < ETH_ALEN; i++)
1260                 dst[i] = src[i];
1261         dst[0] |= 0x02;
1262 }