2 * Atheros AR71xx SoC platform devices
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
8 * Parts of this file are based on Atheros 2.6.15 BSP
9 * Parts of this file are based on Atheros 2.6.31 BSP
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/etherdevice.h>
20 #include <linux/platform_device.h>
21 #include <linux/serial_8250.h>
22 #include <linux/clk.h>
23 #include <linux/sizes.h>
25 #include <asm/mach-ath79/ath79.h>
26 #include <asm/mach-ath79/ar71xx_regs.h>
27 #include <asm/mach-ath79/irq.h>
32 unsigned char ath79_mac_base[ETH_ALEN] __initdata;
34 static struct resource ath79_mdio0_resources[] = {
37 .flags = IORESOURCE_MEM,
38 .start = AR71XX_GE0_BASE,
39 .end = AR71XX_GE0_BASE + 0x200 - 1,
43 struct ag71xx_mdio_platform_data ath79_mdio0_data;
45 struct platform_device ath79_mdio0_device = {
46 .name = "ag71xx-mdio",
48 .resource = ath79_mdio0_resources,
49 .num_resources = ARRAY_SIZE(ath79_mdio0_resources),
51 .platform_data = &ath79_mdio0_data,
55 static struct resource ath79_mdio1_resources[] = {
58 .flags = IORESOURCE_MEM,
59 .start = AR71XX_GE1_BASE,
60 .end = AR71XX_GE1_BASE + 0x200 - 1,
64 struct ag71xx_mdio_platform_data ath79_mdio1_data;
66 struct platform_device ath79_mdio1_device = {
67 .name = "ag71xx-mdio",
69 .resource = ath79_mdio1_resources,
70 .num_resources = ARRAY_SIZE(ath79_mdio1_resources),
72 .platform_data = &ath79_mdio1_data,
76 static void ath79_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift)
81 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
83 t = __raw_readl(base + cfg_reg);
86 __raw_writel(t, base + cfg_reg);
89 __raw_writel(pll_val, base + pll_reg);
92 __raw_writel(t, base + cfg_reg);
96 __raw_writel(t, base + cfg_reg);
99 printk(KERN_DEBUG "ar71xx: pll_reg %#x: %#x\n",
100 (unsigned int)(base + pll_reg), __raw_readl(base + pll_reg));
105 static void __init ath79_mii_ctrl_set_if(unsigned int reg,
111 base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
113 t = __raw_readl(base + reg);
114 t &= ~(AR71XX_MII_CTRL_IF_MASK);
115 t |= (mii_if & AR71XX_MII_CTRL_IF_MASK);
116 __raw_writel(t, base + reg);
121 static void ath79_mii_ctrl_set_speed(unsigned int reg, unsigned int speed)
124 unsigned int mii_speed;
129 mii_speed = AR71XX_MII_CTRL_SPEED_10;
132 mii_speed = AR71XX_MII_CTRL_SPEED_100;
135 mii_speed = AR71XX_MII_CTRL_SPEED_1000;
141 base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
143 t = __raw_readl(base + reg);
144 t &= ~(AR71XX_MII_CTRL_SPEED_MASK << AR71XX_MII_CTRL_SPEED_SHIFT);
145 t |= mii_speed << AR71XX_MII_CTRL_SPEED_SHIFT;
146 __raw_writel(t, base + reg);
151 static unsigned long ar934x_get_mdio_ref_clock(void)
157 base = ioremap(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
160 t = __raw_readl(base + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
161 if (t & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL) {
162 ret = 100 * 1000 * 1000;
166 clk = clk_get(NULL, "ref");
168 ret = clk_get_rate(clk);
176 void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
178 struct platform_device *mdio_dev;
179 struct ag71xx_mdio_platform_data *mdio_data;
182 if (ath79_soc == ATH79_SOC_AR9341 ||
183 ath79_soc == ATH79_SOC_AR9342 ||
184 ath79_soc == ATH79_SOC_AR9344 ||
185 ath79_soc == ATH79_SOC_QCA9556 ||
186 ath79_soc == ATH79_SOC_QCA9558 ||
187 ath79_soc == ATH79_SOC_QCA956X)
193 printk(KERN_ERR "ar71xx: invalid MDIO id %u\n", id);
198 case ATH79_SOC_AR7241:
199 case ATH79_SOC_AR9330:
200 case ATH79_SOC_AR9331:
201 case ATH79_SOC_QCA9533:
202 case ATH79_SOC_TP9343:
203 mdio_dev = &ath79_mdio1_device;
204 mdio_data = &ath79_mdio1_data;
207 case ATH79_SOC_AR9341:
208 case ATH79_SOC_AR9342:
209 case ATH79_SOC_AR9344:
210 case ATH79_SOC_QCA9556:
211 case ATH79_SOC_QCA9558:
212 case ATH79_SOC_QCA956X:
214 mdio_dev = &ath79_mdio0_device;
215 mdio_data = &ath79_mdio0_data;
217 mdio_dev = &ath79_mdio1_device;
218 mdio_data = &ath79_mdio1_data;
222 case ATH79_SOC_AR7242:
223 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG,
224 AR7242_PLL_REG_ETH0_INT_CLOCK, 0x62000000,
225 AR71XX_ETH0_PLL_SHIFT);
228 mdio_dev = &ath79_mdio0_device;
229 mdio_data = &ath79_mdio0_data;
233 mdio_data->phy_mask = phy_mask;
236 case ATH79_SOC_AR7240:
237 mdio_data->is_ar7240 = 1;
239 case ATH79_SOC_AR7241:
240 mdio_data->builtin_switch = 1;
243 case ATH79_SOC_AR9330:
244 mdio_data->is_ar9330 = 1;
246 case ATH79_SOC_AR9331:
247 mdio_data->builtin_switch = 1;
250 case ATH79_SOC_AR9341:
251 case ATH79_SOC_AR9342:
252 case ATH79_SOC_AR9344:
254 mdio_data->builtin_switch = 1;
255 mdio_data->ref_clock = ar934x_get_mdio_ref_clock();
256 mdio_data->mdio_clock = 6250000;
258 mdio_data->is_ar934x = 1;
261 case ATH79_SOC_QCA9533:
262 case ATH79_SOC_TP9343:
263 mdio_data->builtin_switch = 1;
266 case ATH79_SOC_QCA9556:
267 case ATH79_SOC_QCA9558:
268 mdio_data->is_ar934x = 1;
271 case ATH79_SOC_QCA956X:
273 mdio_data->builtin_switch = 1;
274 mdio_data->is_ar934x = 1;
281 platform_device_register(mdio_dev);
284 struct ath79_eth_pll_data ath79_eth0_pll_data;
285 struct ath79_eth_pll_data ath79_eth1_pll_data;
287 static u32 ath79_get_eth_pll(unsigned int mac, int speed)
289 struct ath79_eth_pll_data *pll_data;
294 pll_data = &ath79_eth0_pll_data;
297 pll_data = &ath79_eth1_pll_data;
305 pll_val = pll_data->pll_10;
308 pll_val = pll_data->pll_100;
311 pll_val = pll_data->pll_1000;
320 static void ath79_set_speed_ge0(int speed)
322 u32 val = ath79_get_eth_pll(0, speed);
324 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK,
325 val, AR71XX_ETH0_PLL_SHIFT);
326 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
329 static void ath79_set_speed_ge1(int speed)
331 u32 val = ath79_get_eth_pll(1, speed);
333 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK,
334 val, AR71XX_ETH1_PLL_SHIFT);
335 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
338 static void ar7242_set_speed_ge0(int speed)
340 u32 val = ath79_get_eth_pll(0, speed);
343 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
344 __raw_writel(val, base + AR7242_PLL_REG_ETH0_INT_CLOCK);
348 static void ar91xx_set_speed_ge0(int speed)
350 u32 val = ath79_get_eth_pll(0, speed);
352 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH0_INT_CLOCK,
353 val, AR913X_ETH0_PLL_SHIFT);
354 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
357 static void ar91xx_set_speed_ge1(int speed)
359 u32 val = ath79_get_eth_pll(1, speed);
361 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH1_INT_CLOCK,
362 val, AR913X_ETH1_PLL_SHIFT);
363 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
366 static void ar934x_set_speed_ge0(int speed)
369 u32 val = ath79_get_eth_pll(0, speed);
371 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
372 __raw_writel(val, base + AR934X_PLL_ETH_XMII_CONTROL_REG);
376 static void qca955x_set_speed_xmii(int speed)
379 u32 val = ath79_get_eth_pll(0, speed);
381 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
382 __raw_writel(val, base + QCA955X_PLL_ETH_XMII_CONTROL_REG);
386 static void qca955x_set_speed_sgmii(int id, int speed)
389 u32 val = ath79_get_eth_pll(id, speed);
391 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
392 __raw_writel(val, base + QCA955X_PLL_ETH_SGMII_CONTROL_REG);
396 static void qca9556_set_speed_sgmii(int speed)
398 qca955x_set_speed_sgmii(0, speed);
401 static void qca9558_set_speed_sgmii(int speed)
403 qca955x_set_speed_sgmii(1, speed);
406 static void qca956x_set_speed_sgmii(int speed)
409 u32 val = ath79_get_eth_pll(0, speed);
411 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
412 __raw_writel(val, base + QCA955X_PLL_ETH_SGMII_CONTROL_REG);
416 static void ath79_set_speed_dummy(int speed)
420 static void ath79_ddr_flush_ge0(void)
422 ath79_ddr_wb_flush(0);
425 static void ath79_ddr_flush_ge1(void)
427 ath79_ddr_wb_flush(1);
430 static struct resource ath79_eth0_resources[] = {
433 .flags = IORESOURCE_MEM,
434 .start = AR71XX_GE0_BASE,
435 .end = AR71XX_GE0_BASE + 0x200 - 1,
438 .flags = IORESOURCE_IRQ,
439 .start = ATH79_CPU_IRQ(4),
440 .end = ATH79_CPU_IRQ(4),
444 struct ag71xx_platform_data ath79_eth0_data = {
445 .reset_bit = AR71XX_RESET_GE0_MAC,
448 struct platform_device ath79_eth0_device = {
451 .resource = ath79_eth0_resources,
452 .num_resources = ARRAY_SIZE(ath79_eth0_resources),
454 .platform_data = &ath79_eth0_data,
458 static struct resource ath79_eth1_resources[] = {
461 .flags = IORESOURCE_MEM,
462 .start = AR71XX_GE1_BASE,
463 .end = AR71XX_GE1_BASE + 0x200 - 1,
466 .flags = IORESOURCE_IRQ,
467 .start = ATH79_CPU_IRQ(5),
468 .end = ATH79_CPU_IRQ(5),
472 struct ag71xx_platform_data ath79_eth1_data = {
473 .reset_bit = AR71XX_RESET_GE1_MAC,
476 struct platform_device ath79_eth1_device = {
479 .resource = ath79_eth1_resources,
480 .num_resources = ARRAY_SIZE(ath79_eth1_resources),
482 .platform_data = &ath79_eth1_data,
486 struct ag71xx_switch_platform_data ath79_switch_data;
488 #define AR71XX_PLL_VAL_1000 0x00110000
489 #define AR71XX_PLL_VAL_100 0x00001099
490 #define AR71XX_PLL_VAL_10 0x00991099
492 #define AR724X_PLL_VAL_1000 0x00110000
493 #define AR724X_PLL_VAL_100 0x00001099
494 #define AR724X_PLL_VAL_10 0x00991099
496 #define AR7242_PLL_VAL_1000 0x16000000
497 #define AR7242_PLL_VAL_100 0x00000101
498 #define AR7242_PLL_VAL_10 0x00001616
500 #define AR913X_PLL_VAL_1000 0x1a000000
501 #define AR913X_PLL_VAL_100 0x13000a44
502 #define AR913X_PLL_VAL_10 0x00441099
504 #define AR933X_PLL_VAL_1000 0x00110000
505 #define AR933X_PLL_VAL_100 0x00001099
506 #define AR933X_PLL_VAL_10 0x00991099
508 #define AR934X_PLL_VAL_1000 0x16000000
509 #define AR934X_PLL_VAL_100 0x00000101
510 #define AR934X_PLL_VAL_10 0x00001616
512 #define QCA956X_PLL_VAL_1000 0x03000000
513 #define QCA956X_PLL_VAL_100 0x00000101
514 #define QCA956X_PLL_VAL_10 0x00001919
516 static void __init ath79_init_eth_pll_data(unsigned int id)
518 struct ath79_eth_pll_data *pll_data;
519 u32 pll_10, pll_100, pll_1000;
523 pll_data = &ath79_eth0_pll_data;
526 pll_data = &ath79_eth1_pll_data;
533 case ATH79_SOC_AR7130:
534 case ATH79_SOC_AR7141:
535 case ATH79_SOC_AR7161:
536 pll_10 = AR71XX_PLL_VAL_10;
537 pll_100 = AR71XX_PLL_VAL_100;
538 pll_1000 = AR71XX_PLL_VAL_1000;
541 case ATH79_SOC_AR7240:
542 case ATH79_SOC_AR7241:
543 pll_10 = AR724X_PLL_VAL_10;
544 pll_100 = AR724X_PLL_VAL_100;
545 pll_1000 = AR724X_PLL_VAL_1000;
548 case ATH79_SOC_AR7242:
549 pll_10 = AR7242_PLL_VAL_10;
550 pll_100 = AR7242_PLL_VAL_100;
551 pll_1000 = AR7242_PLL_VAL_1000;
554 case ATH79_SOC_AR9130:
555 case ATH79_SOC_AR9132:
556 pll_10 = AR913X_PLL_VAL_10;
557 pll_100 = AR913X_PLL_VAL_100;
558 pll_1000 = AR913X_PLL_VAL_1000;
561 case ATH79_SOC_AR9330:
562 case ATH79_SOC_AR9331:
563 pll_10 = AR933X_PLL_VAL_10;
564 pll_100 = AR933X_PLL_VAL_100;
565 pll_1000 = AR933X_PLL_VAL_1000;
568 case ATH79_SOC_AR9341:
569 case ATH79_SOC_AR9342:
570 case ATH79_SOC_AR9344:
571 case ATH79_SOC_QCA9533:
572 case ATH79_SOC_QCA9556:
573 case ATH79_SOC_QCA9558:
574 case ATH79_SOC_TP9343:
575 pll_10 = AR934X_PLL_VAL_10;
576 pll_100 = AR934X_PLL_VAL_100;
577 pll_1000 = AR934X_PLL_VAL_1000;
580 case ATH79_SOC_QCA956X:
581 pll_10 = QCA956X_PLL_VAL_10;
582 pll_100 = QCA956X_PLL_VAL_100;
583 pll_1000 = QCA956X_PLL_VAL_1000;
590 if (!pll_data->pll_10)
591 pll_data->pll_10 = pll_10;
593 if (!pll_data->pll_100)
594 pll_data->pll_100 = pll_100;
596 if (!pll_data->pll_1000)
597 pll_data->pll_1000 = pll_1000;
600 static int __init ath79_setup_phy_if_mode(unsigned int id,
601 struct ag71xx_platform_data *pdata)
608 case ATH79_SOC_AR7130:
609 case ATH79_SOC_AR7141:
610 case ATH79_SOC_AR7161:
611 case ATH79_SOC_AR9130:
612 case ATH79_SOC_AR9132:
613 switch (pdata->phy_if_mode) {
614 case PHY_INTERFACE_MODE_MII:
615 mii_if = AR71XX_MII0_CTRL_IF_MII;
617 case PHY_INTERFACE_MODE_GMII:
618 mii_if = AR71XX_MII0_CTRL_IF_GMII;
620 case PHY_INTERFACE_MODE_RGMII:
621 mii_if = AR71XX_MII0_CTRL_IF_RGMII;
623 case PHY_INTERFACE_MODE_RMII:
624 mii_if = AR71XX_MII0_CTRL_IF_RMII;
629 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII0_CTRL, mii_if);
632 case ATH79_SOC_AR7240:
633 case ATH79_SOC_AR7241:
634 case ATH79_SOC_AR9330:
635 case ATH79_SOC_AR9331:
636 case ATH79_SOC_QCA9533:
637 case ATH79_SOC_TP9343:
638 pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
641 case ATH79_SOC_AR7242:
644 case ATH79_SOC_AR9341:
645 case ATH79_SOC_AR9342:
646 case ATH79_SOC_AR9344:
647 switch (pdata->phy_if_mode) {
648 case PHY_INTERFACE_MODE_MII:
649 case PHY_INTERFACE_MODE_GMII:
650 case PHY_INTERFACE_MODE_RGMII:
651 case PHY_INTERFACE_MODE_RMII:
658 case ATH79_SOC_QCA9556:
659 case ATH79_SOC_QCA9558:
660 case ATH79_SOC_QCA956X:
661 switch (pdata->phy_if_mode) {
662 case PHY_INTERFACE_MODE_MII:
663 case PHY_INTERFACE_MODE_RGMII:
664 case PHY_INTERFACE_MODE_SGMII:
677 case ATH79_SOC_AR7130:
678 case ATH79_SOC_AR7141:
679 case ATH79_SOC_AR7161:
680 case ATH79_SOC_AR9130:
681 case ATH79_SOC_AR9132:
682 switch (pdata->phy_if_mode) {
683 case PHY_INTERFACE_MODE_RMII:
684 mii_if = AR71XX_MII1_CTRL_IF_RMII;
686 case PHY_INTERFACE_MODE_RGMII:
687 mii_if = AR71XX_MII1_CTRL_IF_RGMII;
692 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII1_CTRL, mii_if);
695 case ATH79_SOC_AR7240:
696 case ATH79_SOC_AR7241:
697 case ATH79_SOC_AR9330:
698 case ATH79_SOC_AR9331:
699 case ATH79_SOC_TP9343:
700 pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
703 case ATH79_SOC_AR7242:
706 case ATH79_SOC_AR9341:
707 case ATH79_SOC_AR9342:
708 case ATH79_SOC_AR9344:
709 case ATH79_SOC_QCA9533:
710 case ATH79_SOC_QCA956X:
711 switch (pdata->phy_if_mode) {
712 case PHY_INTERFACE_MODE_MII:
713 case PHY_INTERFACE_MODE_GMII:
720 case ATH79_SOC_QCA9556:
721 case ATH79_SOC_QCA9558:
722 switch (pdata->phy_if_mode) {
723 case PHY_INTERFACE_MODE_MII:
724 case PHY_INTERFACE_MODE_RGMII:
725 case PHY_INTERFACE_MODE_SGMII:
741 void __init ath79_setup_ar933x_phy4_switch(bool mac, bool mdio)
746 base = ioremap(AR933X_GMAC_BASE, AR933X_GMAC_SIZE);
748 t = __raw_readl(base + AR933X_GMAC_REG_ETH_CFG);
749 t &= ~(AR933X_ETH_CFG_SW_PHY_SWAP | AR933X_ETH_CFG_SW_PHY_ADDR_SWAP);
751 t |= AR933X_ETH_CFG_SW_PHY_SWAP;
753 t |= AR933X_ETH_CFG_SW_PHY_ADDR_SWAP;
754 __raw_writel(t, base + AR933X_GMAC_REG_ETH_CFG);
759 void __init ath79_setup_ar934x_eth_cfg(u32 mask)
764 base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
766 t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
768 t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 |
769 AR934X_ETH_CFG_MII_GMAC0 |
770 AR934X_ETH_CFG_GMII_GMAC0 |
771 AR934X_ETH_CFG_SW_ONLY_MODE |
772 AR934X_ETH_CFG_SW_PHY_SWAP);
776 __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
778 __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
783 void __init ath79_setup_ar934x_eth_rx_delay(unsigned int rxd,
789 rxd &= AR934X_ETH_CFG_RXD_DELAY_MASK;
790 rxdv &= AR934X_ETH_CFG_RDV_DELAY_MASK;
792 base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
794 t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
796 t &= ~(AR934X_ETH_CFG_RXD_DELAY_MASK << AR934X_ETH_CFG_RXD_DELAY_SHIFT |
797 AR934X_ETH_CFG_RDV_DELAY_MASK << AR934X_ETH_CFG_RDV_DELAY_SHIFT);
799 t |= (rxd << AR934X_ETH_CFG_RXD_DELAY_SHIFT |
800 rxdv << AR934X_ETH_CFG_RDV_DELAY_SHIFT);
802 __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
804 __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
809 void __init ath79_setup_qca955x_eth_cfg(u32 mask)
814 base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
816 t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);
818 t &= ~(QCA955X_ETH_CFG_RGMII_EN | QCA955X_ETH_CFG_GE0_SGMII);
822 __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
827 void __init ath79_setup_qca956x_eth_cfg(u32 mask)
832 base = ioremap(QCA956X_GMAC_BASE, QCA956X_GMAC_SIZE);
834 t = __raw_readl(base + QCA956X_GMAC_REG_ETH_CFG);
836 t &= ~(QCA956X_ETH_CFG_SW_ONLY_MODE |
837 QCA956X_ETH_CFG_SW_PHY_SWAP);
841 __raw_writel(t, base + QCA956X_GMAC_REG_ETH_CFG);
843 __raw_readl(base + QCA956X_GMAC_REG_ETH_CFG);
848 static int ath79_eth_instance __initdata;
849 void __init ath79_register_eth(unsigned int id)
851 struct platform_device *pdev;
852 struct ag71xx_platform_data *pdata;
856 printk(KERN_ERR "ar71xx: invalid ethernet id %d\n", id);
860 ath79_init_eth_pll_data(id);
863 pdev = &ath79_eth0_device;
865 pdev = &ath79_eth1_device;
867 pdata = pdev->dev.platform_data;
869 pdata->max_frame_len = 1540;
870 pdata->desc_pktlen_mask = 0xfff;
872 err = ath79_setup_phy_if_mode(id, pdata);
875 "ar71xx: invalid PHY interface mode for GE%u\n", id);
880 pdata->ddr_flush = ath79_ddr_flush_ge0;
882 pdata->ddr_flush = ath79_ddr_flush_ge1;
885 case ATH79_SOC_AR7130:
887 pdata->set_speed = ath79_set_speed_ge0;
889 pdata->set_speed = ath79_set_speed_ge1;
892 case ATH79_SOC_AR7141:
893 case ATH79_SOC_AR7161:
895 pdata->set_speed = ath79_set_speed_ge0;
897 pdata->set_speed = ath79_set_speed_ge1;
901 case ATH79_SOC_AR7242:
903 pdata->reset_bit |= AR724X_RESET_GE0_MDIO |
904 AR71XX_RESET_GE0_PHY;
905 pdata->set_speed = ar7242_set_speed_ge0;
907 pdata->reset_bit |= AR724X_RESET_GE1_MDIO |
908 AR71XX_RESET_GE1_PHY;
909 pdata->set_speed = ath79_set_speed_dummy;
912 pdata->is_ar724x = 1;
915 case ATH79_SOC_AR7241:
917 pdata->reset_bit |= AR724X_RESET_GE0_MDIO;
919 pdata->reset_bit |= AR724X_RESET_GE1_MDIO;
921 case ATH79_SOC_AR7240:
923 pdata->reset_bit |= AR71XX_RESET_GE0_PHY;
924 pdata->set_speed = ath79_set_speed_dummy;
926 pdata->phy_mask = BIT(4);
928 pdata->reset_bit |= AR71XX_RESET_GE1_PHY;
929 pdata->set_speed = ath79_set_speed_dummy;
931 pdata->speed = SPEED_1000;
932 pdata->duplex = DUPLEX_FULL;
933 pdata->switch_data = &ath79_switch_data;
934 pdata->use_flow_control = 1;
936 ath79_switch_data.phy_poll_mask |= BIT(4);
939 pdata->is_ar724x = 1;
940 if (ath79_soc == ATH79_SOC_AR7240)
941 pdata->is_ar7240 = 1;
944 case ATH79_SOC_AR9132:
947 case ATH79_SOC_AR9130:
949 pdata->set_speed = ar91xx_set_speed_ge0;
951 pdata->set_speed = ar91xx_set_speed_ge1;
952 pdata->is_ar91xx = 1;
955 case ATH79_SOC_AR9330:
956 case ATH79_SOC_AR9331:
958 pdata->reset_bit = AR933X_RESET_GE0_MAC |
959 AR933X_RESET_GE0_MDIO;
960 pdata->set_speed = ath79_set_speed_dummy;
962 pdata->phy_mask = BIT(4);
964 pdata->reset_bit = AR933X_RESET_GE1_MAC |
965 AR933X_RESET_GE1_MDIO;
966 pdata->set_speed = ath79_set_speed_dummy;
968 pdata->speed = SPEED_1000;
970 pdata->duplex = DUPLEX_FULL;
971 pdata->switch_data = &ath79_switch_data;
972 pdata->use_flow_control = 1;
974 ath79_switch_data.phy_poll_mask |= BIT(4);
977 pdata->is_ar724x = 1;
980 case ATH79_SOC_AR9341:
981 case ATH79_SOC_AR9342:
982 case ATH79_SOC_AR9344:
983 case ATH79_SOC_QCA9533:
985 pdata->reset_bit = AR934X_RESET_GE0_MAC |
986 AR934X_RESET_GE0_MDIO;
987 pdata->set_speed = ar934x_set_speed_ge0;
989 if (ath79_soc == ATH79_SOC_QCA9533)
990 pdata->disable_inline_checksum_engine = 1;
992 pdata->reset_bit = AR934X_RESET_GE1_MAC |
993 AR934X_RESET_GE1_MDIO;
994 pdata->set_speed = ath79_set_speed_dummy;
996 pdata->switch_data = &ath79_switch_data;
998 /* reset the built-in switch */
999 ath79_device_reset_set(AR934X_RESET_ETH_SWITCH);
1000 ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH);
1003 pdata->has_gbit = 1;
1004 pdata->is_ar724x = 1;
1006 pdata->max_frame_len = SZ_16K - 1;
1007 pdata->desc_pktlen_mask = SZ_16K - 1;
1010 case ATH79_SOC_TP9343:
1012 pdata->reset_bit = AR933X_RESET_GE0_MAC |
1013 AR933X_RESET_GE0_MDIO;
1014 pdata->set_speed = ath79_set_speed_dummy;
1016 if (!pdata->phy_mask)
1017 pdata->phy_mask = BIT(4);
1019 pdata->reset_bit = AR933X_RESET_GE1_MAC |
1020 AR933X_RESET_GE1_MDIO;
1021 pdata->set_speed = ath79_set_speed_dummy;
1023 pdata->speed = SPEED_1000;
1024 pdata->duplex = DUPLEX_FULL;
1025 pdata->switch_data = &ath79_switch_data;
1026 pdata->use_flow_control = 1;
1028 ath79_switch_data.phy_poll_mask |= BIT(4);
1031 pdata->has_gbit = 1;
1032 pdata->is_ar724x = 1;
1035 case ATH79_SOC_QCA9556:
1036 case ATH79_SOC_QCA9558:
1038 pdata->reset_bit = QCA955X_RESET_GE0_MAC |
1039 QCA955X_RESET_GE0_MDIO;
1040 pdata->set_speed = qca955x_set_speed_xmii;
1042 /* QCA9556 only has SGMII interface */
1043 if (ath79_soc == ATH79_SOC_QCA9556)
1044 pdata->set_speed = qca9556_set_speed_sgmii;
1046 pdata->reset_bit = QCA955X_RESET_GE1_MAC |
1047 QCA955X_RESET_GE1_MDIO;
1048 pdata->set_speed = qca9558_set_speed_sgmii;
1051 pdata->has_gbit = 1;
1052 pdata->is_ar724x = 1;
1055 * Limit the maximum frame length to 4095 bytes.
1056 * Although the documentation says that the hardware
1057 * limit is 16383 bytes but that does not work in
1058 * practice. It seems that the hardware only updates
1059 * the lowest 12 bits of the packet length field
1060 * in the RX descriptor.
1062 pdata->max_frame_len = SZ_4K - 1;
1063 pdata->desc_pktlen_mask = SZ_16K - 1;
1066 case ATH79_SOC_QCA956X:
1068 pdata->reset_bit = QCA955X_RESET_GE0_MAC |
1069 QCA955X_RESET_GE0_MDIO;
1071 if (pdata->phy_if_mode == PHY_INTERFACE_MODE_SGMII)
1072 pdata->set_speed = qca956x_set_speed_sgmii;
1074 pdata->set_speed = ar934x_set_speed_ge0;
1076 pdata->disable_inline_checksum_engine = 1;
1078 pdata->reset_bit = QCA955X_RESET_GE1_MAC |
1079 QCA955X_RESET_GE1_MDIO;
1081 pdata->set_speed = ath79_set_speed_dummy;
1083 pdata->switch_data = &ath79_switch_data;
1085 pdata->speed = SPEED_1000;
1086 pdata->duplex = DUPLEX_FULL;
1087 pdata->use_flow_control = 1;
1089 /* reset the built-in switch */
1090 ath79_device_reset_set(AR934X_RESET_ETH_SWITCH);
1091 ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH);
1094 pdata->has_gbit = 1;
1095 pdata->is_ar724x = 1;
1102 switch (pdata->phy_if_mode) {
1103 case PHY_INTERFACE_MODE_GMII:
1104 case PHY_INTERFACE_MODE_RGMII:
1105 case PHY_INTERFACE_MODE_SGMII:
1106 if (!pdata->has_gbit) {
1107 printk(KERN_ERR "ar71xx: no gbit available on eth%d\n",
1116 if (!is_valid_ether_addr(pdata->mac_addr)) {
1117 random_ether_addr(pdata->mac_addr);
1119 "ar71xx: using random MAC address for eth%d\n",
1120 ath79_eth_instance);
1123 if (pdata->mii_bus_dev == NULL) {
1124 switch (ath79_soc) {
1125 case ATH79_SOC_AR9341:
1126 case ATH79_SOC_AR9342:
1127 case ATH79_SOC_AR9344:
1129 pdata->mii_bus_dev = &ath79_mdio0_device.dev;
1131 pdata->mii_bus_dev = &ath79_mdio1_device.dev;
1134 case ATH79_SOC_AR7241:
1135 case ATH79_SOC_AR9330:
1136 case ATH79_SOC_AR9331:
1137 case ATH79_SOC_QCA9533:
1138 case ATH79_SOC_TP9343:
1139 pdata->mii_bus_dev = &ath79_mdio1_device.dev;
1142 case ATH79_SOC_QCA9556:
1143 case ATH79_SOC_QCA9558:
1144 /* don't assign any MDIO device by default */
1147 case ATH79_SOC_QCA956X:
1148 if (pdata->phy_if_mode != PHY_INTERFACE_MODE_SGMII)
1149 pdata->mii_bus_dev = &ath79_mdio1_device.dev;
1153 pdata->mii_bus_dev = &ath79_mdio0_device.dev;
1158 /* Reset the device */
1159 ath79_device_reset_set(pdata->reset_bit);
1162 ath79_device_reset_clear(pdata->reset_bit);
1165 platform_device_register(pdev);
1166 ath79_eth_instance++;
1169 void __init ath79_set_mac_base(unsigned char *mac)
1171 memcpy(ath79_mac_base, mac, ETH_ALEN);
1174 void __init ath79_parse_ascii_mac(char *mac_str, u8 *mac)
1178 t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
1179 &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5]);
1182 t = sscanf(mac_str, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
1183 &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5]);
1185 if (t != ETH_ALEN || !is_valid_ether_addr(mac)) {
1186 memset(mac, 0, ETH_ALEN);
1187 printk(KERN_DEBUG "ar71xx: invalid mac address \"%s\"\n",
1192 void __init ath79_extract_mac_reverse(u8 *ptr, u8 *out)
1196 for (i = 0; i < ETH_ALEN; i++) {
1197 out[i] = ptr[ETH_ALEN-i-1];
1201 static void __init ath79_set_mac_base_ascii(char *str)
1205 ath79_parse_ascii_mac(str, mac);
1206 ath79_set_mac_base(mac);
1209 static int __init ath79_ethaddr_setup(char *str)
1211 ath79_set_mac_base_ascii(str);
1214 __setup("ethaddr=", ath79_ethaddr_setup);
1216 static int __init ath79_kmac_setup(char *str)
1218 ath79_set_mac_base_ascii(str);
1221 __setup("kmac=", ath79_kmac_setup);
1223 void __init ath79_init_mac(unsigned char *dst, const unsigned char *src,
1231 if (!src || !is_valid_ether_addr(src)) {
1232 memset(dst, '\0', ETH_ALEN);
1236 t = (((u32) src[3]) << 16) + (((u32) src[4]) << 8) + ((u32) src[5]);
1242 dst[3] = (t >> 16) & 0xff;
1243 dst[4] = (t >> 8) & 0xff;
1247 void __init ath79_init_local_mac(unsigned char *dst, const unsigned char *src)
1254 if (!src || !is_valid_ether_addr(src)) {
1255 memset(dst, '\0', ETH_ALEN);
1259 for (i = 0; i < ETH_ALEN; i++)