2 * Atheros AR71xx SoC platform devices
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
8 * Parts of this file are based on Atheros 2.6.15 BSP
9 * Parts of this file are based on Atheros 2.6.31 BSP
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/etherdevice.h>
20 #include <linux/platform_device.h>
21 #include <linux/serial_8250.h>
22 #include <linux/clk.h>
23 #include <linux/sizes.h>
25 #include <asm/mach-ath79/ath79.h>
26 #include <asm/mach-ath79/ar71xx_regs.h>
27 #include <asm/mach-ath79/irq.h>
32 unsigned char ath79_mac_base[ETH_ALEN] __initdata;
34 static struct resource ath79_mdio0_resources[] = {
37 .flags = IORESOURCE_MEM,
38 .start = AR71XX_GE0_BASE,
39 .end = AR71XX_GE0_BASE + 0x200 - 1,
43 struct ag71xx_mdio_platform_data ath79_mdio0_data;
45 struct platform_device ath79_mdio0_device = {
46 .name = "ag71xx-mdio",
48 .resource = ath79_mdio0_resources,
49 .num_resources = ARRAY_SIZE(ath79_mdio0_resources),
51 .platform_data = &ath79_mdio0_data,
55 static struct resource ath79_mdio1_resources[] = {
58 .flags = IORESOURCE_MEM,
59 .start = AR71XX_GE1_BASE,
60 .end = AR71XX_GE1_BASE + 0x200 - 1,
64 struct ag71xx_mdio_platform_data ath79_mdio1_data;
66 struct platform_device ath79_mdio1_device = {
67 .name = "ag71xx-mdio",
69 .resource = ath79_mdio1_resources,
70 .num_resources = ARRAY_SIZE(ath79_mdio1_resources),
72 .platform_data = &ath79_mdio1_data,
76 static void ath79_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift)
81 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
83 t = __raw_readl(base + cfg_reg);
86 __raw_writel(t, base + cfg_reg);
89 __raw_writel(pll_val, base + pll_reg);
92 __raw_writel(t, base + cfg_reg);
96 __raw_writel(t, base + cfg_reg);
99 printk(KERN_DEBUG "ar71xx: pll_reg %#x: %#x\n",
100 (unsigned int)(base + pll_reg), __raw_readl(base + pll_reg));
105 static void __init ath79_mii_ctrl_set_if(unsigned int reg,
111 base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
113 t = __raw_readl(base + reg);
114 t &= ~(AR71XX_MII_CTRL_IF_MASK);
115 t |= (mii_if & AR71XX_MII_CTRL_IF_MASK);
116 __raw_writel(t, base + reg);
121 static void ath79_mii_ctrl_set_speed(unsigned int reg, unsigned int speed)
124 unsigned int mii_speed;
129 mii_speed = AR71XX_MII_CTRL_SPEED_10;
132 mii_speed = AR71XX_MII_CTRL_SPEED_100;
135 mii_speed = AR71XX_MII_CTRL_SPEED_1000;
141 base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
143 t = __raw_readl(base + reg);
144 t &= ~(AR71XX_MII_CTRL_SPEED_MASK << AR71XX_MII_CTRL_SPEED_SHIFT);
145 t |= mii_speed << AR71XX_MII_CTRL_SPEED_SHIFT;
146 __raw_writel(t, base + reg);
151 static unsigned long ar934x_get_mdio_ref_clock(void)
157 base = ioremap(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
160 t = __raw_readl(base + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
161 if (t & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL) {
162 ret = 100 * 1000 * 1000;
166 clk = clk_get(NULL, "ref");
168 ret = clk_get_rate(clk);
176 void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
178 struct platform_device *mdio_dev;
179 struct ag71xx_mdio_platform_data *mdio_data;
182 if (ath79_soc == ATH79_SOC_AR9341 ||
183 ath79_soc == ATH79_SOC_AR9342 ||
184 ath79_soc == ATH79_SOC_AR9344 ||
185 ath79_soc == ATH79_SOC_QCA9556 ||
186 ath79_soc == ATH79_SOC_QCA9558)
192 printk(KERN_ERR "ar71xx: invalid MDIO id %u\n", id);
197 case ATH79_SOC_AR7241:
198 case ATH79_SOC_AR9330:
199 case ATH79_SOC_AR9331:
200 mdio_dev = &ath79_mdio1_device;
201 mdio_data = &ath79_mdio1_data;
204 case ATH79_SOC_AR9341:
205 case ATH79_SOC_AR9342:
206 case ATH79_SOC_AR9344:
207 case ATH79_SOC_QCA9556:
208 case ATH79_SOC_QCA9558:
210 mdio_dev = &ath79_mdio0_device;
211 mdio_data = &ath79_mdio0_data;
213 mdio_dev = &ath79_mdio1_device;
214 mdio_data = &ath79_mdio1_data;
218 case ATH79_SOC_AR7242:
219 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG,
220 AR7242_PLL_REG_ETH0_INT_CLOCK, 0x62000000,
221 AR71XX_ETH0_PLL_SHIFT);
224 mdio_dev = &ath79_mdio0_device;
225 mdio_data = &ath79_mdio0_data;
229 mdio_data->phy_mask = phy_mask;
232 case ATH79_SOC_AR7240:
233 mdio_data->is_ar7240 = 1;
235 case ATH79_SOC_AR7241:
236 mdio_data->builtin_switch = 1;
239 case ATH79_SOC_AR9330:
240 mdio_data->is_ar9330 = 1;
242 case ATH79_SOC_AR9331:
243 mdio_data->builtin_switch = 1;
246 case ATH79_SOC_AR9341:
247 case ATH79_SOC_AR9342:
248 case ATH79_SOC_AR9344:
250 mdio_data->builtin_switch = 1;
251 mdio_data->ref_clock = ar934x_get_mdio_ref_clock();
252 mdio_data->mdio_clock = 6250000;
254 mdio_data->is_ar934x = 1;
257 case ATH79_SOC_QCA9556:
258 case ATH79_SOC_QCA9558:
259 mdio_data->is_ar934x = 1;
266 platform_device_register(mdio_dev);
269 struct ath79_eth_pll_data ath79_eth0_pll_data;
270 struct ath79_eth_pll_data ath79_eth1_pll_data;
272 static u32 ath79_get_eth_pll(unsigned int mac, int speed)
274 struct ath79_eth_pll_data *pll_data;
279 pll_data = &ath79_eth0_pll_data;
282 pll_data = &ath79_eth1_pll_data;
290 pll_val = pll_data->pll_10;
293 pll_val = pll_data->pll_100;
296 pll_val = pll_data->pll_1000;
305 static void ath79_set_speed_ge0(int speed)
307 u32 val = ath79_get_eth_pll(0, speed);
309 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK,
310 val, AR71XX_ETH0_PLL_SHIFT);
311 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
314 static void ath79_set_speed_ge1(int speed)
316 u32 val = ath79_get_eth_pll(1, speed);
318 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK,
319 val, AR71XX_ETH1_PLL_SHIFT);
320 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
323 static void ar7242_set_speed_ge0(int speed)
325 u32 val = ath79_get_eth_pll(0, speed);
328 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
329 __raw_writel(val, base + AR7242_PLL_REG_ETH0_INT_CLOCK);
333 static void ar91xx_set_speed_ge0(int speed)
335 u32 val = ath79_get_eth_pll(0, speed);
337 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH0_INT_CLOCK,
338 val, AR913X_ETH0_PLL_SHIFT);
339 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
342 static void ar91xx_set_speed_ge1(int speed)
344 u32 val = ath79_get_eth_pll(1, speed);
346 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH1_INT_CLOCK,
347 val, AR913X_ETH1_PLL_SHIFT);
348 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
351 static void ar934x_set_speed_ge0(int speed)
354 u32 val = ath79_get_eth_pll(0, speed);
356 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
357 __raw_writel(val, base + AR934X_PLL_ETH_XMII_CONTROL_REG);
361 static void qca955x_set_speed_xmii(int speed)
364 u32 val = ath79_get_eth_pll(0, speed);
366 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
367 __raw_writel(val, base + QCA955X_PLL_ETH_XMII_CONTROL_REG);
371 static void qca955x_set_speed_sgmii(int speed)
374 u32 val = ath79_get_eth_pll(1, speed);
376 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
377 __raw_writel(val, base + QCA955X_PLL_ETH_SGMII_CONTROL_REG);
381 static void ath79_set_speed_dummy(int speed)
385 static void ath79_ddr_no_flush(void)
389 static void ath79_ddr_flush_ge0(void)
391 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE0);
394 static void ath79_ddr_flush_ge1(void)
396 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_GE1);
399 static void ar724x_ddr_flush_ge0(void)
401 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE0);
404 static void ar724x_ddr_flush_ge1(void)
406 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_GE1);
409 static void ar91xx_ddr_flush_ge0(void)
411 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE0);
414 static void ar91xx_ddr_flush_ge1(void)
416 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_GE1);
419 static void ar933x_ddr_flush_ge0(void)
421 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE0);
424 static void ar933x_ddr_flush_ge1(void)
426 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_GE1);
429 static struct resource ath79_eth0_resources[] = {
432 .flags = IORESOURCE_MEM,
433 .start = AR71XX_GE0_BASE,
434 .end = AR71XX_GE0_BASE + 0x200 - 1,
437 .flags = IORESOURCE_IRQ,
438 .start = ATH79_CPU_IRQ(4),
439 .end = ATH79_CPU_IRQ(4),
443 struct ag71xx_platform_data ath79_eth0_data = {
444 .reset_bit = AR71XX_RESET_GE0_MAC,
447 struct platform_device ath79_eth0_device = {
450 .resource = ath79_eth0_resources,
451 .num_resources = ARRAY_SIZE(ath79_eth0_resources),
453 .platform_data = &ath79_eth0_data,
457 static struct resource ath79_eth1_resources[] = {
460 .flags = IORESOURCE_MEM,
461 .start = AR71XX_GE1_BASE,
462 .end = AR71XX_GE1_BASE + 0x200 - 1,
465 .flags = IORESOURCE_IRQ,
466 .start = ATH79_CPU_IRQ(5),
467 .end = ATH79_CPU_IRQ(5),
471 struct ag71xx_platform_data ath79_eth1_data = {
472 .reset_bit = AR71XX_RESET_GE1_MAC,
475 struct platform_device ath79_eth1_device = {
478 .resource = ath79_eth1_resources,
479 .num_resources = ARRAY_SIZE(ath79_eth1_resources),
481 .platform_data = &ath79_eth1_data,
485 struct ag71xx_switch_platform_data ath79_switch_data;
487 #define AR71XX_PLL_VAL_1000 0x00110000
488 #define AR71XX_PLL_VAL_100 0x00001099
489 #define AR71XX_PLL_VAL_10 0x00991099
491 #define AR724X_PLL_VAL_1000 0x00110000
492 #define AR724X_PLL_VAL_100 0x00001099
493 #define AR724X_PLL_VAL_10 0x00991099
495 #define AR7242_PLL_VAL_1000 0x16000000
496 #define AR7242_PLL_VAL_100 0x00000101
497 #define AR7242_PLL_VAL_10 0x00001616
499 #define AR913X_PLL_VAL_1000 0x1a000000
500 #define AR913X_PLL_VAL_100 0x13000a44
501 #define AR913X_PLL_VAL_10 0x00441099
503 #define AR933X_PLL_VAL_1000 0x00110000
504 #define AR933X_PLL_VAL_100 0x00001099
505 #define AR933X_PLL_VAL_10 0x00991099
507 #define AR934X_PLL_VAL_1000 0x16000000
508 #define AR934X_PLL_VAL_100 0x00000101
509 #define AR934X_PLL_VAL_10 0x00001616
511 static void __init ath79_init_eth_pll_data(unsigned int id)
513 struct ath79_eth_pll_data *pll_data;
514 u32 pll_10, pll_100, pll_1000;
518 pll_data = &ath79_eth0_pll_data;
521 pll_data = &ath79_eth1_pll_data;
528 case ATH79_SOC_AR7130:
529 case ATH79_SOC_AR7141:
530 case ATH79_SOC_AR7161:
531 pll_10 = AR71XX_PLL_VAL_10;
532 pll_100 = AR71XX_PLL_VAL_100;
533 pll_1000 = AR71XX_PLL_VAL_1000;
536 case ATH79_SOC_AR7240:
537 case ATH79_SOC_AR7241:
538 pll_10 = AR724X_PLL_VAL_10;
539 pll_100 = AR724X_PLL_VAL_100;
540 pll_1000 = AR724X_PLL_VAL_1000;
543 case ATH79_SOC_AR7242:
544 pll_10 = AR7242_PLL_VAL_10;
545 pll_100 = AR7242_PLL_VAL_100;
546 pll_1000 = AR7242_PLL_VAL_1000;
549 case ATH79_SOC_AR9130:
550 case ATH79_SOC_AR9132:
551 pll_10 = AR913X_PLL_VAL_10;
552 pll_100 = AR913X_PLL_VAL_100;
553 pll_1000 = AR913X_PLL_VAL_1000;
556 case ATH79_SOC_AR9330:
557 case ATH79_SOC_AR9331:
558 pll_10 = AR933X_PLL_VAL_10;
559 pll_100 = AR933X_PLL_VAL_100;
560 pll_1000 = AR933X_PLL_VAL_1000;
563 case ATH79_SOC_AR9341:
564 case ATH79_SOC_AR9342:
565 case ATH79_SOC_AR9344:
566 case ATH79_SOC_QCA9556:
567 case ATH79_SOC_QCA9558:
568 pll_10 = AR934X_PLL_VAL_10;
569 pll_100 = AR934X_PLL_VAL_100;
570 pll_1000 = AR934X_PLL_VAL_1000;
577 if (!pll_data->pll_10)
578 pll_data->pll_10 = pll_10;
580 if (!pll_data->pll_100)
581 pll_data->pll_100 = pll_100;
583 if (!pll_data->pll_1000)
584 pll_data->pll_1000 = pll_1000;
587 static int __init ath79_setup_phy_if_mode(unsigned int id,
588 struct ag71xx_platform_data *pdata)
595 case ATH79_SOC_AR7130:
596 case ATH79_SOC_AR7141:
597 case ATH79_SOC_AR7161:
598 case ATH79_SOC_AR9130:
599 case ATH79_SOC_AR9132:
600 switch (pdata->phy_if_mode) {
601 case PHY_INTERFACE_MODE_MII:
602 mii_if = AR71XX_MII0_CTRL_IF_MII;
604 case PHY_INTERFACE_MODE_GMII:
605 mii_if = AR71XX_MII0_CTRL_IF_GMII;
607 case PHY_INTERFACE_MODE_RGMII:
608 mii_if = AR71XX_MII0_CTRL_IF_RGMII;
610 case PHY_INTERFACE_MODE_RMII:
611 mii_if = AR71XX_MII0_CTRL_IF_RMII;
616 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII0_CTRL, mii_if);
619 case ATH79_SOC_AR7240:
620 case ATH79_SOC_AR7241:
621 case ATH79_SOC_AR9330:
622 case ATH79_SOC_AR9331:
623 pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
626 case ATH79_SOC_AR7242:
629 case ATH79_SOC_AR9341:
630 case ATH79_SOC_AR9342:
631 case ATH79_SOC_AR9344:
632 switch (pdata->phy_if_mode) {
633 case PHY_INTERFACE_MODE_MII:
634 case PHY_INTERFACE_MODE_GMII:
635 case PHY_INTERFACE_MODE_RGMII:
636 case PHY_INTERFACE_MODE_RMII:
643 case ATH79_SOC_QCA9556:
644 case ATH79_SOC_QCA9558:
645 switch (pdata->phy_if_mode) {
646 case PHY_INTERFACE_MODE_MII:
647 case PHY_INTERFACE_MODE_RGMII:
648 case PHY_INTERFACE_MODE_SGMII:
661 case ATH79_SOC_AR7130:
662 case ATH79_SOC_AR7141:
663 case ATH79_SOC_AR7161:
664 case ATH79_SOC_AR9130:
665 case ATH79_SOC_AR9132:
666 switch (pdata->phy_if_mode) {
667 case PHY_INTERFACE_MODE_RMII:
668 mii_if = AR71XX_MII1_CTRL_IF_RMII;
670 case PHY_INTERFACE_MODE_RGMII:
671 mii_if = AR71XX_MII1_CTRL_IF_RGMII;
676 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII1_CTRL, mii_if);
679 case ATH79_SOC_AR7240:
680 case ATH79_SOC_AR7241:
681 case ATH79_SOC_AR9330:
682 case ATH79_SOC_AR9331:
683 pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
686 case ATH79_SOC_AR7242:
689 case ATH79_SOC_AR9341:
690 case ATH79_SOC_AR9342:
691 case ATH79_SOC_AR9344:
692 switch (pdata->phy_if_mode) {
693 case PHY_INTERFACE_MODE_MII:
694 case PHY_INTERFACE_MODE_GMII:
701 case ATH79_SOC_QCA9556:
702 case ATH79_SOC_QCA9558:
703 switch (pdata->phy_if_mode) {
704 case PHY_INTERFACE_MODE_MII:
705 case PHY_INTERFACE_MODE_RGMII:
706 case PHY_INTERFACE_MODE_SGMII:
722 void __init ath79_setup_ar933x_phy4_switch(bool mac, bool mdio)
727 base = ioremap(AR933X_GMAC_BASE, AR933X_GMAC_SIZE);
729 t = __raw_readl(base + AR933X_GMAC_REG_ETH_CFG);
730 t &= ~(AR933X_ETH_CFG_SW_PHY_SWAP | AR933X_ETH_CFG_SW_PHY_ADDR_SWAP);
732 t |= AR933X_ETH_CFG_SW_PHY_SWAP;
734 t |= AR933X_ETH_CFG_SW_PHY_ADDR_SWAP;
735 __raw_writel(t, base + AR933X_GMAC_REG_ETH_CFG);
740 void __init ath79_setup_ar934x_eth_cfg(u32 mask)
745 base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
747 t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
749 t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 |
750 AR934X_ETH_CFG_MII_GMAC0 |
751 AR934X_ETH_CFG_GMII_GMAC0 |
752 AR934X_ETH_CFG_SW_ONLY_MODE |
753 AR934X_ETH_CFG_SW_PHY_SWAP);
757 __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
759 __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
764 static int ath79_eth_instance __initdata;
765 void __init ath79_register_eth(unsigned int id)
767 struct platform_device *pdev;
768 struct ag71xx_platform_data *pdata;
772 printk(KERN_ERR "ar71xx: invalid ethernet id %d\n", id);
776 ath79_init_eth_pll_data(id);
779 pdev = &ath79_eth0_device;
781 pdev = &ath79_eth1_device;
783 pdata = pdev->dev.platform_data;
785 pdata->max_frame_len = 1540;
786 pdata->desc_pktlen_mask = 0xfff;
788 err = ath79_setup_phy_if_mode(id, pdata);
791 "ar71xx: invalid PHY interface mode for GE%u\n", id);
796 case ATH79_SOC_AR7130:
798 pdata->ddr_flush = ath79_ddr_flush_ge0;
799 pdata->set_speed = ath79_set_speed_ge0;
801 pdata->ddr_flush = ath79_ddr_flush_ge1;
802 pdata->set_speed = ath79_set_speed_ge1;
806 case ATH79_SOC_AR7141:
807 case ATH79_SOC_AR7161:
809 pdata->ddr_flush = ath79_ddr_flush_ge0;
810 pdata->set_speed = ath79_set_speed_ge0;
812 pdata->ddr_flush = ath79_ddr_flush_ge1;
813 pdata->set_speed = ath79_set_speed_ge1;
818 case ATH79_SOC_AR7242:
820 pdata->reset_bit |= AR724X_RESET_GE0_MDIO |
821 AR71XX_RESET_GE0_PHY;
822 pdata->ddr_flush = ar724x_ddr_flush_ge0;
823 pdata->set_speed = ar7242_set_speed_ge0;
825 pdata->reset_bit |= AR724X_RESET_GE1_MDIO |
826 AR71XX_RESET_GE1_PHY;
827 pdata->ddr_flush = ar724x_ddr_flush_ge1;
828 pdata->set_speed = ath79_set_speed_dummy;
831 pdata->is_ar724x = 1;
833 if (!pdata->fifo_cfg1)
834 pdata->fifo_cfg1 = 0x0010ffff;
835 if (!pdata->fifo_cfg2)
836 pdata->fifo_cfg2 = 0x015500aa;
837 if (!pdata->fifo_cfg3)
838 pdata->fifo_cfg3 = 0x01f00140;
841 case ATH79_SOC_AR7241:
843 pdata->reset_bit |= AR724X_RESET_GE0_MDIO;
845 pdata->reset_bit |= AR724X_RESET_GE1_MDIO;
847 case ATH79_SOC_AR7240:
849 pdata->reset_bit |= AR71XX_RESET_GE0_PHY;
850 pdata->ddr_flush = ar724x_ddr_flush_ge0;
851 pdata->set_speed = ath79_set_speed_dummy;
853 pdata->phy_mask = BIT(4);
855 pdata->reset_bit |= AR71XX_RESET_GE1_PHY;
856 pdata->ddr_flush = ar724x_ddr_flush_ge1;
857 pdata->set_speed = ath79_set_speed_dummy;
859 pdata->speed = SPEED_1000;
860 pdata->duplex = DUPLEX_FULL;
861 pdata->switch_data = &ath79_switch_data;
863 ath79_switch_data.phy_poll_mask |= BIT(4);
866 pdata->is_ar724x = 1;
867 if (ath79_soc == ATH79_SOC_AR7240)
868 pdata->is_ar7240 = 1;
870 if (!pdata->fifo_cfg1)
871 pdata->fifo_cfg1 = 0x0010ffff;
872 if (!pdata->fifo_cfg2)
873 pdata->fifo_cfg2 = 0x015500aa;
874 if (!pdata->fifo_cfg3)
875 pdata->fifo_cfg3 = 0x01f00140;
878 case ATH79_SOC_AR9130:
880 pdata->ddr_flush = ar91xx_ddr_flush_ge0;
881 pdata->set_speed = ar91xx_set_speed_ge0;
883 pdata->ddr_flush = ar91xx_ddr_flush_ge1;
884 pdata->set_speed = ar91xx_set_speed_ge1;
886 pdata->is_ar91xx = 1;
889 case ATH79_SOC_AR9132:
891 pdata->ddr_flush = ar91xx_ddr_flush_ge0;
892 pdata->set_speed = ar91xx_set_speed_ge0;
894 pdata->ddr_flush = ar91xx_ddr_flush_ge1;
895 pdata->set_speed = ar91xx_set_speed_ge1;
897 pdata->is_ar91xx = 1;
901 case ATH79_SOC_AR9330:
902 case ATH79_SOC_AR9331:
904 pdata->reset_bit = AR933X_RESET_GE0_MAC |
905 AR933X_RESET_GE0_MDIO;
906 pdata->ddr_flush = ar933x_ddr_flush_ge0;
907 pdata->set_speed = ath79_set_speed_dummy;
909 pdata->phy_mask = BIT(4);
911 pdata->reset_bit = AR933X_RESET_GE1_MAC |
912 AR933X_RESET_GE1_MDIO;
913 pdata->ddr_flush = ar933x_ddr_flush_ge1;
914 pdata->set_speed = ath79_set_speed_dummy;
916 pdata->speed = SPEED_1000;
917 pdata->duplex = DUPLEX_FULL;
918 pdata->switch_data = &ath79_switch_data;
920 ath79_switch_data.phy_poll_mask |= BIT(4);
924 pdata->is_ar724x = 1;
926 if (!pdata->fifo_cfg1)
927 pdata->fifo_cfg1 = 0x0010ffff;
928 if (!pdata->fifo_cfg2)
929 pdata->fifo_cfg2 = 0x015500aa;
930 if (!pdata->fifo_cfg3)
931 pdata->fifo_cfg3 = 0x01f00140;
934 case ATH79_SOC_AR9341:
935 case ATH79_SOC_AR9342:
936 case ATH79_SOC_AR9344:
938 pdata->reset_bit = AR934X_RESET_GE0_MAC |
939 AR934X_RESET_GE0_MDIO;
940 pdata->set_speed = ar934x_set_speed_ge0;
942 pdata->reset_bit = AR934X_RESET_GE1_MAC |
943 AR934X_RESET_GE1_MDIO;
944 pdata->set_speed = ath79_set_speed_dummy;
946 pdata->switch_data = &ath79_switch_data;
948 /* reset the built-in switch */
949 ath79_device_reset_set(AR934X_RESET_ETH_SWITCH);
950 ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH);
953 pdata->ddr_flush = ath79_ddr_no_flush;
955 pdata->is_ar724x = 1;
957 pdata->max_frame_len = SZ_16K - 1;
958 pdata->desc_pktlen_mask = SZ_16K - 1;
960 if (!pdata->fifo_cfg1)
961 pdata->fifo_cfg1 = 0x0010ffff;
962 if (!pdata->fifo_cfg2)
963 pdata->fifo_cfg2 = 0x015500aa;
964 if (!pdata->fifo_cfg3)
965 pdata->fifo_cfg3 = 0x01f00140;
968 case ATH79_SOC_QCA9556:
969 case ATH79_SOC_QCA9558:
971 pdata->reset_bit = QCA955X_RESET_GE0_MAC |
972 QCA955X_RESET_GE0_MDIO;
973 pdata->set_speed = qca955x_set_speed_xmii;
975 pdata->reset_bit = QCA955X_RESET_GE1_MAC |
976 QCA955X_RESET_GE1_MDIO;
977 pdata->set_speed = qca955x_set_speed_sgmii;
980 pdata->ddr_flush = ath79_ddr_no_flush;
982 pdata->is_ar724x = 1;
984 if (!pdata->fifo_cfg1)
985 pdata->fifo_cfg1 = 0x0010ffff;
986 if (!pdata->fifo_cfg2)
987 pdata->fifo_cfg2 = 0x015500aa;
988 if (!pdata->fifo_cfg3)
989 pdata->fifo_cfg3 = 0x01f00140;
996 switch (pdata->phy_if_mode) {
997 case PHY_INTERFACE_MODE_GMII:
998 case PHY_INTERFACE_MODE_RGMII:
999 case PHY_INTERFACE_MODE_SGMII:
1000 if (!pdata->has_gbit) {
1001 printk(KERN_ERR "ar71xx: no gbit available on eth%d\n",
1010 if (!is_valid_ether_addr(pdata->mac_addr)) {
1011 random_ether_addr(pdata->mac_addr);
1013 "ar71xx: using random MAC address for eth%d\n",
1014 ath79_eth_instance);
1017 if (pdata->mii_bus_dev == NULL) {
1018 switch (ath79_soc) {
1019 case ATH79_SOC_AR9341:
1020 case ATH79_SOC_AR9342:
1021 case ATH79_SOC_AR9344:
1023 pdata->mii_bus_dev = &ath79_mdio0_device.dev;
1025 pdata->mii_bus_dev = &ath79_mdio1_device.dev;
1028 case ATH79_SOC_AR7241:
1029 case ATH79_SOC_AR9330:
1030 case ATH79_SOC_AR9331:
1031 pdata->mii_bus_dev = &ath79_mdio1_device.dev;
1034 case ATH79_SOC_QCA9556:
1035 case ATH79_SOC_QCA9558:
1036 /* don't assign any MDIO device by default */
1040 pdata->mii_bus_dev = &ath79_mdio0_device.dev;
1045 /* Reset the device */
1046 ath79_device_reset_set(pdata->reset_bit);
1049 ath79_device_reset_clear(pdata->reset_bit);
1052 platform_device_register(pdev);
1053 ath79_eth_instance++;
1056 void __init ath79_set_mac_base(unsigned char *mac)
1058 memcpy(ath79_mac_base, mac, ETH_ALEN);
1061 void __init ath79_parse_ascii_mac(char *mac_str, u8 *mac)
1065 t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
1066 &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5]);
1069 t = sscanf(mac_str, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
1070 &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5]);
1072 if (t != ETH_ALEN || !is_valid_ether_addr(mac)) {
1073 memset(mac, 0, ETH_ALEN);
1074 printk(KERN_DEBUG "ar71xx: invalid mac address \"%s\"\n",
1079 static void __init ath79_set_mac_base_ascii(char *str)
1083 ath79_parse_ascii_mac(str, mac);
1084 ath79_set_mac_base(mac);
1087 static int __init ath79_ethaddr_setup(char *str)
1089 ath79_set_mac_base_ascii(str);
1092 __setup("ethaddr=", ath79_ethaddr_setup);
1094 static int __init ath79_kmac_setup(char *str)
1096 ath79_set_mac_base_ascii(str);
1099 __setup("kmac=", ath79_kmac_setup);
1101 void __init ath79_init_mac(unsigned char *dst, const unsigned char *src,
1109 if (!src || !is_valid_ether_addr(src)) {
1110 memset(dst, '\0', ETH_ALEN);
1114 t = (((u32) src[3]) << 16) + (((u32) src[4]) << 8) + ((u32) src[5]);
1120 dst[3] = (t >> 16) & 0xff;
1121 dst[4] = (t >> 8) & 0xff;
1125 void __init ath79_init_local_mac(unsigned char *dst, const unsigned char *src)
1132 if (!src || !is_valid_ether_addr(src)) {
1133 memset(dst, '\0', ETH_ALEN);
1137 for (i = 0; i < ETH_ALEN; i++)