target/linux/ar71xx/files/arch/mips/ar71xx/setup.c

   1 /*
   2  *  Atheros AR71xx SoC specific setup
   3  *
   4  *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
   5  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  *  Parts of this file are based on Atheros' 2.6.15 BSP
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms of the GNU General Public License version 2 as published
  11  *  by the Free Software Foundation.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/init.h>
  17 #include <linux/types.h>
  18 #include <linux/pci.h>
  19 #include <linux/serial_8250.h>
  20 #include <linux/bootmem.h>
  21
  22 #include <asm/bootinfo.h>
  23 #include <asm/traps.h>
  24 #include <asm/time.h>           /* for mips_hpt_frequency */
  25 #include <asm/reboot.h>         /* for _machine_{restart,halt} */
  26 #include <asm/mips_machine.h>
  27
  28 #include <asm/mach-ar71xx/ar71xx.h>
  29 #include <asm/mach-ar71xx/pci.h>
  30
  31 #include "devices.h"
  32
  33 #define AR71XX_SYS_TYPE_LEN     64
  34 #define AR71XX_BASE_FREQ        40000000
  35 #define AR91XX_BASE_FREQ        5000000
  36 #define AR724X_BASE_FREQ        5000000
  37
  38 enum ar71xx_mach_type ar71xx_mach;
  39
  40 u32 ar71xx_cpu_freq;
  41 EXPORT_SYMBOL_GPL(ar71xx_cpu_freq);
  42
  43 u32 ar71xx_ahb_freq;
  44 EXPORT_SYMBOL_GPL(ar71xx_ahb_freq);
  45
  46 u32 ar71xx_ddr_freq;
  47 EXPORT_SYMBOL_GPL(ar71xx_ddr_freq);
  48
  49 enum ar71xx_soc_type ar71xx_soc;
  50 EXPORT_SYMBOL_GPL(ar71xx_soc);
  51
  52 int (*ar71xx_pci_bios_init)(unsigned nr_irqs,
  53                              struct ar71xx_pci_irq *map) __initdata;
  54
  55 int (*ar71xx_pci_be_handler)(int is_fixup);
  56
  57 static char ar71xx_sys_type[AR71XX_SYS_TYPE_LEN];
  58
  59 static void ar71xx_restart(char *command)
  60 {
  61         ar71xx_device_stop(RESET_MODULE_FULL_CHIP);
  62         for (;;)
  63                 if (cpu_wait)
  64                         cpu_wait();
  65 }
  66
  67 static void ar71xx_halt(void)
  68 {
  69         while (1)
  70                 cpu_wait();
  71 }
  72
  73 static int ar71xx_be_handler(struct pt_regs *regs, int is_fixup)
  74 {
  75         int err = 0;
  76
  77         if (ar71xx_pci_be_handler)
  78                 err = ar71xx_pci_be_handler(is_fixup);
  79
  80         return (is_fixup && !err) ? MIPS_BE_FIXUP : MIPS_BE_FATAL;
  81 }
  82
  83 int __init ar71xx_pci_init(unsigned nr_irqs, struct ar71xx_pci_irq *map)
  84 {
  85         if (!ar71xx_pci_bios_init)
  86                 return 0;
  87
  88         return ar71xx_pci_bios_init(nr_irqs, map);
  89 }
  90
  91 static void __init ar71xx_detect_mem_size(void)
  92 {
  93         unsigned long size;
  94
  95         for (size = AR71XX_MEM_SIZE_MIN; size < AR71XX_MEM_SIZE_MAX;
  96              size <<= 1 ) {
  97                 if (!memcmp(ar71xx_detect_mem_size,
  98                             ar71xx_detect_mem_size + size, 1024))
  99                         break;
 100         }
 101
 102         add_memory_region(0, size, BOOT_MEM_RAM);
 103 }
 104
 105 static void __init ar71xx_detect_sys_type(void)
 106 {
 107         char *chip = "????";
 108         u32 id;
 109         u32 major;
 110         u32 minor;
 111         u32 rev = 0;
 112
 113         id = ar71xx_reset_rr(AR71XX_RESET_REG_REV_ID);
 114         major = id & REV_ID_MAJOR_MASK;
 115
 116         switch (major) {
 117         case REV_ID_MAJOR_AR71XX:
 118                 minor = id & AR71XX_REV_ID_MINOR_MASK;
 119                 rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
 120                 rev &= AR71XX_REV_ID_REVISION_MASK;
 121                 switch (minor) {
 122                 case AR71XX_REV_ID_MINOR_AR7130:
 123                         ar71xx_soc = AR71XX_SOC_AR7130;
 124                         chip = "7130";
 125                         break;
 126
 127                 case AR71XX_REV_ID_MINOR_AR7141:
 128                         ar71xx_soc = AR71XX_SOC_AR7141;
 129                         chip = "7141";
 130                         break;
 131
 132                 case AR71XX_REV_ID_MINOR_AR7161:
 133                         ar71xx_soc = AR71XX_SOC_AR7161;
 134                         chip = "7161";
 135                         break;
 136                 }
 137                 break;
 138
 139         case REV_ID_MAJOR_AR724X:
 140                 ar71xx_soc = AR71XX_SOC_AR7240;
 141                 chip = "7240";
 142                 rev = (id & AR724X_REV_ID_REVISION_MASK);
 143                 break;
 144
 145         case REV_ID_MAJOR_AR913X:
 146                 minor = id & AR91XX_REV_ID_MINOR_MASK;
 147                 rev = id >> AR91XX_REV_ID_REVISION_SHIFT;
 148                 rev &= AR91XX_REV_ID_REVISION_MASK;
 149                 switch (minor) {
 150                 case AR91XX_REV_ID_MINOR_AR9130:
 151                         ar71xx_soc = AR71XX_SOC_AR9130;
 152                         chip = "9130";
 153                         break;
 154
 155                 case AR91XX_REV_ID_MINOR_AR9132:
 156                         ar71xx_soc = AR71XX_SOC_AR9132;
 157                         chip = "9132";
 158                         break;
 159                 }
 160                 break;
 161
 162         default:
 163                 panic("ar71xx: unknown chip id:0x%08x\n", id);
 164         }
 165
 166         sprintf(ar71xx_sys_type, "Atheros AR%s rev %u", chip, rev);
 167 }
 168
 169 static void __init ar91xx_detect_sys_frequency(void)
 170 {
 171         u32 pll;
 172         u32 freq;
 173         u32 div;
 174
 175         pll = ar71xx_pll_rr(AR91XX_PLL_REG_CPU_CONFIG);
 176
 177         div = ((pll >> AR91XX_PLL_DIV_SHIFT) & AR91XX_PLL_DIV_MASK);
 178         freq = div * AR91XX_BASE_FREQ;
 179
 180         ar71xx_cpu_freq = freq;
 181
 182         div = ((pll >> AR91XX_DDR_DIV_SHIFT) & AR91XX_DDR_DIV_MASK) + 1;
 183         ar71xx_ddr_freq = freq / div;
 184
 185         div = (((pll >> AR91XX_AHB_DIV_SHIFT) & AR91XX_AHB_DIV_MASK) + 1) * 2;
 186         ar71xx_ahb_freq = ar71xx_cpu_freq / div;
 187 }
 188
 189 static void __init ar71xx_detect_sys_frequency(void)
 190 {
 191         u32 pll;
 192         u32 freq;
 193         u32 div;
 194
 195         pll = ar71xx_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);
 196
 197         div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1;
 198         freq = div * AR71XX_BASE_FREQ;
 199
 200         div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
 201         ar71xx_cpu_freq = freq / div;
 202
 203         div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
 204         ar71xx_ddr_freq = freq / div;
 205
 206         div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
 207         ar71xx_ahb_freq = ar71xx_cpu_freq / div;
 208 }
 209
 210 static void __init ar724x_detect_sys_frequency(void)
 211 {
 212         u32 pll;
 213         u32 freq;
 214         u32 div;
 215
 216         pll = ar71xx_pll_rr(AR724X_PLL_REG_CPU_CONFIG);
 217
 218         div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK);
 219         freq = div * AR724X_BASE_FREQ;
 220
 221         div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK);
 222         freq *= div;
 223
 224         ar71xx_cpu_freq = freq;
 225
 226         div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
 227         ar71xx_ddr_freq = freq / div;
 228
 229         div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
 230         ar71xx_ahb_freq = ar71xx_cpu_freq / div;
 231 }
 232
 233 static void __init detect_sys_frequency(void)
 234 {
 235         switch (ar71xx_soc) {
 236         case AR71XX_SOC_AR7130:
 237         case AR71XX_SOC_AR7141:
 238         case AR71XX_SOC_AR7161:
 239                 ar71xx_detect_sys_frequency();
 240                 break;
 241
 242         case AR71XX_SOC_AR7240:
 243                 ar724x_detect_sys_frequency();
 244                 break;
 245
 246         case AR71XX_SOC_AR9130:
 247         case AR71XX_SOC_AR9132:
 248                 ar91xx_detect_sys_frequency();
 249                 break;
 250
 251         default:
 252                 BUG();
 253         }
 254 }
 255
 256 #ifdef CONFIG_AR71XX_EARLY_SERIAL
 257 static void __init ar71xx_early_serial_setup(void)
 258 {
 259         struct uart_port p;
 260
 261         memset(&p, 0, sizeof(p));
 262
 263         p.flags         = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP;
 264         p.iotype        = UPIO_MEM32;
 265         p.uartclk       = ar71xx_ahb_freq;
 266         p.irq           = AR71XX_MISC_IRQ_UART;
 267         p.regshift      = 2;
 268         p.mapbase       = AR71XX_UART_BASE;
 269
 270         early_serial_setup(&p);
 271 }
 272 #else
 273 static inline void ar71xx_early_serial_setup(void) {};
 274 #endif /* CONFIG_AR71XX_EARLY_SERIAL */
 275
 276 const char *get_system_type(void)
 277 {
 278         return ar71xx_sys_type;
 279 }
 280
 281 unsigned int __cpuinit get_c0_compare_irq(void)
 282 {
 283         return CP0_LEGACY_COMPARE_IRQ;
 284 }
 285
 286 void __init plat_mem_setup(void)
 287 {
 288         set_io_port_base(KSEG1);
 289
 290         ar71xx_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE,
 291                                                 AR71XX_DDR_CTRL_SIZE);
 292
 293         ar71xx_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
 294                                                 AR71XX_PLL_SIZE);
 295
 296         ar71xx_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
 297                                                 AR71XX_RESET_SIZE);
 298
 299         ar71xx_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
 300
 301         ar71xx_usb_ctrl_base = ioremap_nocache(AR71XX_USB_CTRL_BASE,
 302                                                 AR71XX_USB_CTRL_SIZE);
 303
 304         ar71xx_detect_mem_size();
 305         ar71xx_detect_sys_type();
 306         detect_sys_frequency();
 307
 308         printk(KERN_INFO
 309                 "%s, CPU:%u.%03u MHz, AHB:%u.%03u MHz, DDR:%u.%03u MHz\n",
 310                 ar71xx_sys_type,
 311                 ar71xx_cpu_freq / 1000000, (ar71xx_cpu_freq / 1000) % 1000,
 312                 ar71xx_ahb_freq / 1000000, (ar71xx_ahb_freq / 1000) % 1000,
 313                 ar71xx_ddr_freq / 1000000, (ar71xx_ddr_freq / 1000) % 1000);
 314
 315         _machine_restart = ar71xx_restart;
 316         _machine_halt = ar71xx_halt;
 317         pm_power_off = ar71xx_halt;
 318
 319         board_be_handler = ar71xx_be_handler;
 320
 321         ar71xx_early_serial_setup();
 322 }
 323
 324 void __init plat_time_init(void)
 325 {
 326         mips_hpt_frequency = ar71xx_cpu_freq / 2;
 327 }
 328
 329 static int __init ar71xx_machine_setup(void)
 330 {
 331         ar71xx_gpio_init();
 332
 333         ar71xx_add_device_uart();
 334         ar71xx_add_device_wdt();
 335
 336         mips_machine_setup(ar71xx_mach);
 337         return 0;
 338 }
 339
 340 arch_initcall(ar71xx_machine_setup);