2 * Atheros AR71xx SoC specific setup
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
8 * Parts of this file are based on Atheros 2.6.15 BSP
9 * Parts of this file are based on Atheros 2.6.31 BSP
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/bootmem.h>
20 #include <asm/bootinfo.h>
21 #include <asm/time.h> /* for mips_hpt_frequency */
22 #include <asm/reboot.h> /* for _machine_{restart,halt} */
23 #include <asm/mips_machine.h>
25 #include <asm/mach-ar71xx/ar71xx.h>
30 #define AR71XX_SYS_TYPE_LEN 64
33 EXPORT_SYMBOL_GPL(ar71xx_cpu_freq);
36 EXPORT_SYMBOL_GPL(ar71xx_ahb_freq);
39 EXPORT_SYMBOL_GPL(ar71xx_ddr_freq);
42 EXPORT_SYMBOL_GPL(ar71xx_ref_freq);
44 enum ar71xx_soc_type ar71xx_soc;
45 EXPORT_SYMBOL_GPL(ar71xx_soc);
47 static char ar71xx_sys_type[AR71XX_SYS_TYPE_LEN];
49 static void ar71xx_restart(char *command)
51 ar71xx_device_stop(RESET_MODULE_FULL_CHIP);
57 static void ar71xx_halt(void)
63 static void __init ar71xx_detect_mem_size(void)
67 for (size = AR71XX_MEM_SIZE_MIN; size < AR71XX_MEM_SIZE_MAX;
69 if (!memcmp(ar71xx_detect_mem_size,
70 ar71xx_detect_mem_size + size, 1024))
74 add_memory_region(0, size, BOOT_MEM_RAM);
77 static void __init ar71xx_detect_sys_type(void)
85 id = ar71xx_reset_rr(AR71XX_RESET_REG_REV_ID);
86 major = id & REV_ID_MAJOR_MASK;
89 case REV_ID_MAJOR_AR71XX:
90 minor = id & AR71XX_REV_ID_MINOR_MASK;
91 rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
92 rev &= AR71XX_REV_ID_REVISION_MASK;
94 case AR71XX_REV_ID_MINOR_AR7130:
95 ar71xx_soc = AR71XX_SOC_AR7130;
99 case AR71XX_REV_ID_MINOR_AR7141:
100 ar71xx_soc = AR71XX_SOC_AR7141;
104 case AR71XX_REV_ID_MINOR_AR7161:
105 ar71xx_soc = AR71XX_SOC_AR7161;
111 case REV_ID_MAJOR_AR7240:
112 ar71xx_soc = AR71XX_SOC_AR7240;
114 rev = id & AR724X_REV_ID_REVISION_MASK;
117 case REV_ID_MAJOR_AR7241:
118 ar71xx_soc = AR71XX_SOC_AR7241;
120 rev = id & AR724X_REV_ID_REVISION_MASK;
123 case REV_ID_MAJOR_AR7242:
124 ar71xx_soc = AR71XX_SOC_AR7242;
126 rev = id & AR724X_REV_ID_REVISION_MASK;
129 case REV_ID_MAJOR_AR913X:
130 minor = id & AR91XX_REV_ID_MINOR_MASK;
131 rev = id >> AR91XX_REV_ID_REVISION_SHIFT;
132 rev &= AR91XX_REV_ID_REVISION_MASK;
134 case AR91XX_REV_ID_MINOR_AR9130:
135 ar71xx_soc = AR71XX_SOC_AR9130;
139 case AR91XX_REV_ID_MINOR_AR9132:
140 ar71xx_soc = AR71XX_SOC_AR9132;
146 case REV_ID_MAJOR_AR9330:
147 ar71xx_soc = AR71XX_SOC_AR9330;
149 rev = id & AR933X_REV_ID_REVISION_MASK;
152 case REV_ID_MAJOR_AR9331:
153 ar71xx_soc = AR71XX_SOC_AR9331;
155 rev = id & AR933X_REV_ID_REVISION_MASK;
158 case REV_ID_MAJOR_AR9342:
159 ar71xx_soc = AR71XX_SOC_AR9342;
161 rev = id & AR934X_REV_ID_REVISION_MASK;
164 case REV_ID_MAJOR_AR9344:
165 ar71xx_soc = AR71XX_SOC_AR9344;
167 rev = id & AR934X_REV_ID_REVISION_MASK;
171 panic("ar71xx: unknown chip id:0x%08x\n", id);
174 sprintf(ar71xx_sys_type, "Atheros AR%s rev %u", chip, rev);
175 pr_info("SoC: %s\n", ar71xx_sys_type);
178 static void __init ar934x_detect_sys_frequency(void)
180 u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
182 if (ar71xx_reset_rr(AR934X_RESET_REG_BOOTSTRAP) & AR934X_REF_CLK_40)
183 ar71xx_ref_freq = 40 * 1000 * 1000;
185 ar71xx_ref_freq = 25 * 1000 * 1000;
187 clk_ctrl = ar71xx_pll_rr(AR934X_PLL_REG_DDR_CTRL_CLOCK);
189 pll = ar71xx_pll_rr(AR934X_PLL_REG_CPU_CONFIG);
190 out_div = AR934X_CPU_PLL_CFG_OUTDIV_GET(pll);
191 ref_div = AR934X_CPU_PLL_CFG_REFDIV_GET(pll);
192 nint = AR934X_CPU_PLL_CFG_NINT_GET(pll);
193 frac = AR934X_CPU_PLL_CFG_NFRAC_GET(pll);
194 postdiv = AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_GET(clk_ctrl);
195 ar71xx_cpu_freq = ((nint * ar71xx_ref_freq / ref_div) >> out_div) /
198 out_div = AR934X_DDR_PLL_CFG_OUTDIV_GET(pll);
199 ref_div = AR934X_DDR_PLL_CFG_REFDIV_GET(pll);
200 nint = AR934X_DDR_PLL_CFG_NINT_GET(pll);
201 frac = AR934X_DDR_PLL_CFG_NFRAC_GET(pll);
202 postdiv = AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_GET(clk_ctrl);
203 ar71xx_ddr_freq = ((nint * ar71xx_ref_freq / ref_div) >> out_div) /
206 postdiv = AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_GET(clk_ctrl);
208 if (AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_GET(clk_ctrl)) {
209 ar71xx_ahb_freq = ar71xx_ddr_freq / (postdiv + 1);
211 ar71xx_ahb_freq = ar71xx_cpu_freq / (postdiv + 1);
216 static void __init ar91xx_detect_sys_frequency(void)
222 ar71xx_ref_freq = 5 * 1000 * 1000;
224 pll = ar71xx_pll_rr(AR91XX_PLL_REG_CPU_CONFIG);
226 div = ((pll >> AR91XX_PLL_DIV_SHIFT) & AR91XX_PLL_DIV_MASK);
227 freq = div * ar71xx_ref_freq;
229 ar71xx_cpu_freq = freq;
231 div = ((pll >> AR91XX_DDR_DIV_SHIFT) & AR91XX_DDR_DIV_MASK) + 1;
232 ar71xx_ddr_freq = freq / div;
234 div = (((pll >> AR91XX_AHB_DIV_SHIFT) & AR91XX_AHB_DIV_MASK) + 1) * 2;
235 ar71xx_ahb_freq = ar71xx_cpu_freq / div;
238 static void __init ar71xx_detect_sys_frequency(void)
244 ar71xx_ref_freq = 40 * 1000 * 1000;
246 pll = ar71xx_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);
248 div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1;
249 freq = div * ar71xx_ref_freq;
251 div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
252 ar71xx_cpu_freq = freq / div;
254 div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
255 ar71xx_ddr_freq = freq / div;
257 div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
258 ar71xx_ahb_freq = ar71xx_cpu_freq / div;
261 static void __init ar724x_detect_sys_frequency(void)
267 ar71xx_ref_freq = 5 * 1000 * 1000;
269 pll = ar71xx_pll_rr(AR724X_PLL_REG_CPU_CONFIG);
271 div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK);
272 freq = div * ar71xx_ref_freq;
274 div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK);
277 ar71xx_cpu_freq = freq;
279 div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
280 ar71xx_ddr_freq = freq / div;
282 div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
283 ar71xx_ahb_freq = ar71xx_cpu_freq / div;
286 static void __init ar933x_detect_sys_frequency(void)
293 t = ar71xx_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
294 if (t & AR933X_BOOTSTRAP_REF_CLK_40)
295 ar71xx_ref_freq = (40 * 1000 * 1000);
297 ar71xx_ref_freq = (25 * 1000 * 1000);
299 clock_ctrl = ar71xx_pll_rr(AR933X_PLL_CLOCK_CTRL_REG);
300 if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
301 ar71xx_cpu_freq = ar71xx_ref_freq;
302 ar71xx_ahb_freq = ar71xx_ref_freq;
303 ar71xx_ddr_freq = ar71xx_ref_freq;
305 cpu_config = ar71xx_pll_rr(AR933X_PLL_CPU_CONFIG_REG);
307 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
308 AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
309 freq = ar71xx_ref_freq / t;
311 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
312 AR933X_PLL_CPU_CONFIG_NINT_MASK;
315 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
316 AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
322 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) &
323 AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1;
324 ar71xx_cpu_freq = freq / t;
326 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) &
327 AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1;
328 ar71xx_ddr_freq = freq / t;
330 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) &
331 AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
332 ar71xx_ahb_freq = freq / t;
336 static void __init detect_sys_frequency(void)
338 switch (ar71xx_soc) {
339 case AR71XX_SOC_AR7130:
340 case AR71XX_SOC_AR7141:
341 case AR71XX_SOC_AR7161:
342 ar71xx_detect_sys_frequency();
345 case AR71XX_SOC_AR7240:
346 case AR71XX_SOC_AR7241:
347 case AR71XX_SOC_AR7242:
348 ar724x_detect_sys_frequency();
351 case AR71XX_SOC_AR9130:
352 case AR71XX_SOC_AR9132:
353 ar91xx_detect_sys_frequency();
356 case AR71XX_SOC_AR9330:
357 case AR71XX_SOC_AR9331:
358 ar933x_detect_sys_frequency();
361 case AR71XX_SOC_AR9341:
362 case AR71XX_SOC_AR9342:
363 case AR71XX_SOC_AR9344:
364 ar934x_detect_sys_frequency();
371 const char *get_system_type(void)
373 return ar71xx_sys_type;
376 unsigned int __cpuinit get_c0_compare_irq(void)
378 return CP0_LEGACY_COMPARE_IRQ;
381 void __init plat_mem_setup(void)
383 set_io_port_base(KSEG1);
385 ar71xx_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE,
386 AR71XX_DDR_CTRL_SIZE);
388 ar71xx_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
391 ar71xx_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
394 ar71xx_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
396 ar71xx_usb_ctrl_base = ioremap_nocache(AR71XX_USB_CTRL_BASE,
397 AR71XX_USB_CTRL_SIZE);
399 ar71xx_detect_mem_size();
400 ar71xx_detect_sys_type();
401 detect_sys_frequency();
403 pr_info("Clocks: CPU:%u.%03uMHz, DDR:%u.%03uMHz, AHB:%u.%03uMHz, "
405 ar71xx_cpu_freq / 1000000, (ar71xx_cpu_freq / 1000) % 1000,
406 ar71xx_ddr_freq / 1000000, (ar71xx_ddr_freq / 1000) % 1000,
407 ar71xx_ahb_freq / 1000000, (ar71xx_ahb_freq / 1000) % 1000,
408 ar71xx_ref_freq / 1000000, (ar71xx_ref_freq / 1000) % 1000);
410 _machine_restart = ar71xx_restart;
411 _machine_halt = ar71xx_halt;
412 pm_power_off = ar71xx_halt;
415 void __init plat_time_init(void)
417 mips_hpt_frequency = ar71xx_cpu_freq / 2;
420 __setup("board=", mips_machtype_setup);
422 static int __init ar71xx_machine_setup(void)
426 ar71xx_add_device_uart();
427 ar71xx_add_device_wdt();
429 mips_machine_setup();
433 arch_initcall(ar71xx_machine_setup);
435 static void __init ar71xx_generic_init(void)
440 MIPS_MACHINE(AR71XX_MACH_GENERIC, "Generic", "Generic AR71xx board",
441 ar71xx_generic_init);