target/linux/ar71xx/files/arch/mips/ar71xx/setup.c

   1 /*
   2  *  Atheros AR71xx SoC specific setup
   3  *
   4  *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
   5  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  *  Parts of this file are based on Atheros' 2.6.15 BSP
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms of the GNU General Public License version 2 as published
  11  *  by the Free Software Foundation.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/serial_8250.h>
  17 #include <linux/bootmem.h>
  18
  19 #include <asm/bootinfo.h>
  20 #include <asm/time.h>           /* for mips_hpt_frequency */
  21 #include <asm/reboot.h>         /* for _machine_{restart,halt} */
  22 #include <asm/mips_machine.h>
  23
  24 #include <asm/mach-ar71xx/ar71xx.h>
  25 #include <asm/mach-ar71xx/pci.h>
  26
  27 #include "machtype.h"
  28 #include "devices.h"
  29
  30 #define AR71XX_SYS_TYPE_LEN     64
  31 #define AR71XX_BASE_FREQ        40000000
  32 #define AR91XX_BASE_FREQ        5000000
  33 #define AR724X_BASE_FREQ        5000000
  34
  35 enum ar71xx_mach_type ar71xx_mach;
  36
  37 u32 ar71xx_cpu_freq;
  38 EXPORT_SYMBOL_GPL(ar71xx_cpu_freq);
  39
  40 u32 ar71xx_ahb_freq;
  41 EXPORT_SYMBOL_GPL(ar71xx_ahb_freq);
  42
  43 u32 ar71xx_ddr_freq;
  44 EXPORT_SYMBOL_GPL(ar71xx_ddr_freq);
  45
  46 enum ar71xx_soc_type ar71xx_soc;
  47 EXPORT_SYMBOL_GPL(ar71xx_soc);
  48
  49 static char ar71xx_sys_type[AR71XX_SYS_TYPE_LEN];
  50
  51 static void ar71xx_restart(char *command)
  52 {
  53         ar71xx_device_stop(RESET_MODULE_FULL_CHIP);
  54         for (;;)
  55                 if (cpu_wait)
  56                         cpu_wait();
  57 }
  58
  59 static void ar71xx_halt(void)
  60 {
  61         while (1)
  62                 cpu_wait();
  63 }
  64
  65 static void __init ar71xx_detect_mem_size(void)
  66 {
  67         unsigned long size;
  68
  69         for (size = AR71XX_MEM_SIZE_MIN; size < AR71XX_MEM_SIZE_MAX;
  70              size <<= 1 ) {
  71                 if (!memcmp(ar71xx_detect_mem_size,
  72                             ar71xx_detect_mem_size + size, 1024))
  73                         break;
  74         }
  75
  76         add_memory_region(0, size, BOOT_MEM_RAM);
  77 }
  78
  79 static void __init ar71xx_detect_sys_type(void)
  80 {
  81         char *chip = "????";
  82         u32 id;
  83         u32 major;
  84         u32 minor;
  85         u32 rev = 0;
  86
  87         id = ar71xx_reset_rr(AR71XX_RESET_REG_REV_ID);
  88         major = id & REV_ID_MAJOR_MASK;
  89
  90         switch (major) {
  91         case REV_ID_MAJOR_AR71XX:
  92                 minor = id & AR71XX_REV_ID_MINOR_MASK;
  93                 rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
  94                 rev &= AR71XX_REV_ID_REVISION_MASK;
  95                 switch (minor) {
  96                 case AR71XX_REV_ID_MINOR_AR7130:
  97                         ar71xx_soc = AR71XX_SOC_AR7130;
  98                         chip = "7130";
  99                         break;
 100
 101                 case AR71XX_REV_ID_MINOR_AR7141:
 102                         ar71xx_soc = AR71XX_SOC_AR7141;
 103                         chip = "7141";
 104                         break;
 105
 106                 case AR71XX_REV_ID_MINOR_AR7161:
 107                         ar71xx_soc = AR71XX_SOC_AR7161;
 108                         chip = "7161";
 109                         break;
 110                 }
 111                 break;
 112
 113         case REV_ID_MAJOR_AR724X:
 114                 ar71xx_soc = AR71XX_SOC_AR7240;
 115                 chip = "7240";
 116                 rev = (id & AR724X_REV_ID_REVISION_MASK);
 117                 break;
 118
 119         case REV_ID_MAJOR_AR913X:
 120                 minor = id & AR91XX_REV_ID_MINOR_MASK;
 121                 rev = id >> AR91XX_REV_ID_REVISION_SHIFT;
 122                 rev &= AR91XX_REV_ID_REVISION_MASK;
 123                 switch (minor) {
 124                 case AR91XX_REV_ID_MINOR_AR9130:
 125                         ar71xx_soc = AR71XX_SOC_AR9130;
 126                         chip = "9130";
 127                         break;
 128
 129                 case AR91XX_REV_ID_MINOR_AR9132:
 130                         ar71xx_soc = AR71XX_SOC_AR9132;
 131                         chip = "9132";
 132                         break;
 133                 }
 134                 break;
 135
 136         default:
 137                 panic("ar71xx: unknown chip id:0x%08x\n", id);
 138         }
 139
 140         sprintf(ar71xx_sys_type, "Atheros AR%s rev %u", chip, rev);
 141 }
 142
 143 static void __init ar91xx_detect_sys_frequency(void)
 144 {
 145         u32 pll;
 146         u32 freq;
 147         u32 div;
 148
 149         pll = ar71xx_pll_rr(AR91XX_PLL_REG_CPU_CONFIG);
 150
 151         div = ((pll >> AR91XX_PLL_DIV_SHIFT) & AR91XX_PLL_DIV_MASK);
 152         freq = div * AR91XX_BASE_FREQ;
 153
 154         ar71xx_cpu_freq = freq;
 155
 156         div = ((pll >> AR91XX_DDR_DIV_SHIFT) & AR91XX_DDR_DIV_MASK) + 1;
 157         ar71xx_ddr_freq = freq / div;
 158
 159         div = (((pll >> AR91XX_AHB_DIV_SHIFT) & AR91XX_AHB_DIV_MASK) + 1) * 2;
 160         ar71xx_ahb_freq = ar71xx_cpu_freq / div;
 161 }
 162
 163 static void __init ar71xx_detect_sys_frequency(void)
 164 {
 165         u32 pll;
 166         u32 freq;
 167         u32 div;
 168
 169         pll = ar71xx_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);
 170
 171         div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1;
 172         freq = div * AR71XX_BASE_FREQ;
 173
 174         div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
 175         ar71xx_cpu_freq = freq / div;
 176
 177         div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
 178         ar71xx_ddr_freq = freq / div;
 179
 180         div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
 181         ar71xx_ahb_freq = ar71xx_cpu_freq / div;
 182 }
 183
 184 static void __init ar724x_detect_sys_frequency(void)
 185 {
 186         u32 pll;
 187         u32 freq;
 188         u32 div;
 189
 190         pll = ar71xx_pll_rr(AR724X_PLL_REG_CPU_CONFIG);
 191
 192         div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK);
 193         freq = div * AR724X_BASE_FREQ;
 194
 195         div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK);
 196         freq *= div;
 197
 198         ar71xx_cpu_freq = freq;
 199
 200         div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
 201         ar71xx_ddr_freq = freq / div;
 202
 203         div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
 204         ar71xx_ahb_freq = ar71xx_cpu_freq / div;
 205 }
 206
 207 static void __init detect_sys_frequency(void)
 208 {
 209         switch (ar71xx_soc) {
 210         case AR71XX_SOC_AR7130:
 211         case AR71XX_SOC_AR7141:
 212         case AR71XX_SOC_AR7161:
 213                 ar71xx_detect_sys_frequency();
 214                 break;
 215
 216         case AR71XX_SOC_AR7240:
 217                 ar724x_detect_sys_frequency();
 218                 break;
 219
 220         case AR71XX_SOC_AR9130:
 221         case AR71XX_SOC_AR9132:
 222                 ar91xx_detect_sys_frequency();
 223                 break;
 224
 225         default:
 226                 BUG();
 227         }
 228 }
 229
 230 const char *get_system_type(void)
 231 {
 232         return ar71xx_sys_type;
 233 }
 234
 235 unsigned int __cpuinit get_c0_compare_irq(void)
 236 {
 237         return CP0_LEGACY_COMPARE_IRQ;
 238 }
 239
 240 void __init plat_mem_setup(void)
 241 {
 242         set_io_port_base(KSEG1);
 243
 244         ar71xx_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE,
 245                                                 AR71XX_DDR_CTRL_SIZE);
 246
 247         ar71xx_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
 248                                                 AR71XX_PLL_SIZE);
 249
 250         ar71xx_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
 251                                                 AR71XX_RESET_SIZE);
 252
 253         ar71xx_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
 254
 255         ar71xx_usb_ctrl_base = ioremap_nocache(AR71XX_USB_CTRL_BASE,
 256                                                 AR71XX_USB_CTRL_SIZE);
 257
 258         ar71xx_detect_mem_size();
 259         ar71xx_detect_sys_type();
 260         detect_sys_frequency();
 261
 262         printk(KERN_INFO
 263                 "%s, CPU:%u.%03u MHz, AHB:%u.%03u MHz, DDR:%u.%03u MHz\n",
 264                 ar71xx_sys_type,
 265                 ar71xx_cpu_freq / 1000000, (ar71xx_cpu_freq / 1000) % 1000,
 266                 ar71xx_ahb_freq / 1000000, (ar71xx_ahb_freq / 1000) % 1000,
 267                 ar71xx_ddr_freq / 1000000, (ar71xx_ddr_freq / 1000) % 1000);
 268
 269         _machine_restart = ar71xx_restart;
 270         _machine_halt = ar71xx_halt;
 271         pm_power_off = ar71xx_halt;
 272 }
 273
 274 void __init plat_time_init(void)
 275 {
 276         mips_hpt_frequency = ar71xx_cpu_freq / 2;
 277 }
 278
 279 static int __init ar71xx_machine_setup(void)
 280 {
 281         ar71xx_gpio_init();
 282
 283         ar71xx_add_device_uart();
 284         ar71xx_add_device_wdt();
 285
 286         mips_machine_setup(ar71xx_mach);
 287         return 0;
 288 }
 289
 290 arch_initcall(ar71xx_machine_setup);