2 * Atheros AR71xx SoC specific setup
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
8 * Parts of this file are based on Atheros 2.6.15 BSP
9 * Parts of this file are based on Atheros 2.6.31 BSP
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/bootmem.h>
20 #include <asm/bootinfo.h>
21 #include <asm/time.h> /* for mips_hpt_frequency */
22 #include <asm/reboot.h> /* for _machine_{restart,halt} */
23 #include <asm/mips_machine.h>
25 #include <asm/mach-ar71xx/ar71xx.h>
30 #define AR71XX_SYS_TYPE_LEN 64
31 #define AR71XX_BASE_FREQ 40000000
32 #define AR91XX_BASE_FREQ 5000000
33 #define AR724X_BASE_FREQ 5000000
36 EXPORT_SYMBOL_GPL(ar71xx_cpu_freq);
39 EXPORT_SYMBOL_GPL(ar71xx_ahb_freq);
42 EXPORT_SYMBOL_GPL(ar71xx_ddr_freq);
45 EXPORT_SYMBOL_GPL(ar934x_ref_freq);
47 enum ar71xx_soc_type ar71xx_soc;
48 EXPORT_SYMBOL_GPL(ar71xx_soc);
50 static char ar71xx_sys_type[AR71XX_SYS_TYPE_LEN];
52 static void ar71xx_restart(char *command)
54 ar71xx_device_stop(RESET_MODULE_FULL_CHIP);
60 static void ar71xx_halt(void)
66 static void __init ar71xx_detect_mem_size(void)
70 for (size = AR71XX_MEM_SIZE_MIN; size < AR71XX_MEM_SIZE_MAX;
72 if (!memcmp(ar71xx_detect_mem_size,
73 ar71xx_detect_mem_size + size, 1024))
77 add_memory_region(0, size, BOOT_MEM_RAM);
80 static void __init ar71xx_detect_sys_type(void)
88 id = ar71xx_reset_rr(AR71XX_RESET_REG_REV_ID);
89 major = id & REV_ID_MAJOR_MASK;
92 case REV_ID_MAJOR_AR71XX:
93 minor = id & AR71XX_REV_ID_MINOR_MASK;
94 rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
95 rev &= AR71XX_REV_ID_REVISION_MASK;
97 case AR71XX_REV_ID_MINOR_AR7130:
98 ar71xx_soc = AR71XX_SOC_AR7130;
102 case AR71XX_REV_ID_MINOR_AR7141:
103 ar71xx_soc = AR71XX_SOC_AR7141;
107 case AR71XX_REV_ID_MINOR_AR7161:
108 ar71xx_soc = AR71XX_SOC_AR7161;
114 case REV_ID_MAJOR_AR7240:
115 ar71xx_soc = AR71XX_SOC_AR7240;
117 rev = id & AR724X_REV_ID_REVISION_MASK;
120 case REV_ID_MAJOR_AR7241:
121 ar71xx_soc = AR71XX_SOC_AR7241;
123 rev = id & AR724X_REV_ID_REVISION_MASK;
126 case REV_ID_MAJOR_AR7242:
127 ar71xx_soc = AR71XX_SOC_AR7242;
129 rev = id & AR724X_REV_ID_REVISION_MASK;
132 case REV_ID_MAJOR_AR913X:
133 minor = id & AR91XX_REV_ID_MINOR_MASK;
134 rev = id >> AR91XX_REV_ID_REVISION_SHIFT;
135 rev &= AR91XX_REV_ID_REVISION_MASK;
137 case AR91XX_REV_ID_MINOR_AR9130:
138 ar71xx_soc = AR71XX_SOC_AR9130;
142 case AR91XX_REV_ID_MINOR_AR9132:
143 ar71xx_soc = AR71XX_SOC_AR9132;
149 case REV_ID_MAJOR_AR9341:
150 ar71xx_soc = AR71XX_SOC_AR9341;
152 rev = id & AR934X_REV_ID_REVISION_MASK;
155 case REV_ID_MAJOR_AR9342:
156 ar71xx_soc = AR71XX_SOC_AR9342;
158 rev = id & AR934X_REV_ID_REVISION_MASK;
161 case REV_ID_MAJOR_AR9344:
162 ar71xx_soc = AR71XX_SOC_AR9344;
164 rev = id & AR934X_REV_ID_REVISION_MASK;
168 panic("ar71xx: unknown chip id:0x%08x\n", id);
171 sprintf(ar71xx_sys_type, "Atheros AR%s rev %u", chip, rev);
174 static void __init ar934x_detect_sys_frequency(void)
176 u32 pll, out_div, ref_div, nint, frac, clk_ctrl, ref, postdiv;
178 if (ar71xx_reset_rr(AR934X_RESET_REG_BOOTSTRAP) & AR934X_REF_CLK_40)
179 ref = (40 * 1000000);
181 ref = (25 * 1000000);
183 ar934x_ref_freq = ref;
185 clk_ctrl = ar71xx_pll_rr(AR934X_PLL_REG_DDR_CTRL_CLOCK);
187 pll = ar71xx_pll_rr(AR934X_PLL_REG_CPU_CONFIG);
188 out_div = AR934X_CPU_PLL_CFG_OUTDIV_GET(pll);
189 ref_div = AR934X_CPU_PLL_CFG_REFDIV_GET(pll);
190 nint = AR934X_CPU_PLL_CFG_NINT_GET(pll);
191 frac = AR934X_CPU_PLL_CFG_NFRAC_GET(pll);
192 postdiv = AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_GET(clk_ctrl);
193 ar71xx_cpu_freq = ((nint * ref / ref_div) >> out_div) / (postdiv + 1);
195 out_div = AR934X_DDR_PLL_CFG_OUTDIV_GET(pll);
196 ref_div = AR934X_DDR_PLL_CFG_REFDIV_GET(pll);
197 nint = AR934X_DDR_PLL_CFG_NINT_GET(pll);
198 frac = AR934X_DDR_PLL_CFG_NFRAC_GET(pll);
199 postdiv = AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_GET(clk_ctrl);
200 ar71xx_ddr_freq = ((nint * ref / ref_div) >> out_div) / (postdiv + 1);
202 postdiv = AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_GET(clk_ctrl);
204 if (AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_GET(clk_ctrl)) {
205 ar71xx_ahb_freq = ar71xx_ddr_freq / (postdiv + 1);
207 ar71xx_ahb_freq = ar71xx_cpu_freq / (postdiv + 1);
212 static void __init ar91xx_detect_sys_frequency(void)
218 pll = ar71xx_pll_rr(AR91XX_PLL_REG_CPU_CONFIG);
220 div = ((pll >> AR91XX_PLL_DIV_SHIFT) & AR91XX_PLL_DIV_MASK);
221 freq = div * AR91XX_BASE_FREQ;
223 ar71xx_cpu_freq = freq;
225 div = ((pll >> AR91XX_DDR_DIV_SHIFT) & AR91XX_DDR_DIV_MASK) + 1;
226 ar71xx_ddr_freq = freq / div;
228 div = (((pll >> AR91XX_AHB_DIV_SHIFT) & AR91XX_AHB_DIV_MASK) + 1) * 2;
229 ar71xx_ahb_freq = ar71xx_cpu_freq / div;
232 static void __init ar71xx_detect_sys_frequency(void)
238 pll = ar71xx_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);
240 div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1;
241 freq = div * AR71XX_BASE_FREQ;
243 div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
244 ar71xx_cpu_freq = freq / div;
246 div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
247 ar71xx_ddr_freq = freq / div;
249 div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
250 ar71xx_ahb_freq = ar71xx_cpu_freq / div;
253 static void __init ar724x_detect_sys_frequency(void)
259 pll = ar71xx_pll_rr(AR724X_PLL_REG_CPU_CONFIG);
261 div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK);
262 freq = div * AR724X_BASE_FREQ;
264 div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK);
267 ar71xx_cpu_freq = freq;
269 div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
270 ar71xx_ddr_freq = freq / div;
272 div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
273 ar71xx_ahb_freq = ar71xx_cpu_freq / div;
276 static void __init detect_sys_frequency(void)
278 switch (ar71xx_soc) {
279 case AR71XX_SOC_AR7130:
280 case AR71XX_SOC_AR7141:
281 case AR71XX_SOC_AR7161:
282 ar71xx_detect_sys_frequency();
285 case AR71XX_SOC_AR7240:
286 case AR71XX_SOC_AR7241:
287 case AR71XX_SOC_AR7242:
288 ar724x_detect_sys_frequency();
291 case AR71XX_SOC_AR9130:
292 case AR71XX_SOC_AR9132:
293 ar91xx_detect_sys_frequency();
296 case AR71XX_SOC_AR9341:
297 case AR71XX_SOC_AR9342:
298 case AR71XX_SOC_AR9344:
299 ar934x_detect_sys_frequency();
306 const char *get_system_type(void)
308 return ar71xx_sys_type;
311 unsigned int __cpuinit get_c0_compare_irq(void)
313 return CP0_LEGACY_COMPARE_IRQ;
316 void __init plat_mem_setup(void)
318 set_io_port_base(KSEG1);
320 ar71xx_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE,
321 AR71XX_DDR_CTRL_SIZE);
323 ar71xx_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
326 ar71xx_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
329 ar71xx_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
331 ar71xx_usb_ctrl_base = ioremap_nocache(AR71XX_USB_CTRL_BASE,
332 AR71XX_USB_CTRL_SIZE);
334 ar71xx_detect_mem_size();
335 ar71xx_detect_sys_type();
336 detect_sys_frequency();
339 "%s, CPU:%u.%03u MHz, AHB:%u.%03u MHz, DDR:%u.%03u MHz\n",
341 ar71xx_cpu_freq / 1000000, (ar71xx_cpu_freq / 1000) % 1000,
342 ar71xx_ahb_freq / 1000000, (ar71xx_ahb_freq / 1000) % 1000,
343 ar71xx_ddr_freq / 1000000, (ar71xx_ddr_freq / 1000) % 1000);
345 _machine_restart = ar71xx_restart;
346 _machine_halt = ar71xx_halt;
347 pm_power_off = ar71xx_halt;
350 void __init plat_time_init(void)
352 mips_hpt_frequency = ar71xx_cpu_freq / 2;
355 __setup("board=", mips_machtype_setup);
357 static int __init ar71xx_machine_setup(void)
361 ar71xx_add_device_uart();
362 ar71xx_add_device_wdt();
364 mips_machine_setup();
368 arch_initcall(ar71xx_machine_setup);
370 static void __init ar71xx_generic_init(void)
375 MIPS_MACHINE(AR71XX_MACH_GENERIC, "Generic", "Generic AR71xx board",
376 ar71xx_generic_init);