target/linux/ar71xx/files/arch/mips/ar71xx/setup.c

   1 /*
   2  *  Atheros AR71xx SoC specific setup
   3  *
   4  *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
   5  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  *  Parts of this file are based on Atheros' 2.6.15 BSP
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms of the GNU General Public License version 2 as published
  11  *  by the Free Software Foundation.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/bootmem.h>
  17
  18 #include <asm/bootinfo.h>
  19 #include <asm/time.h>           /* for mips_hpt_frequency */
  20 #include <asm/reboot.h>         /* for _machine_{restart,halt} */
  21 #include <asm/mips_machine.h>
  22
  23 #include <asm/mach-ar71xx/ar71xx.h>
  24
  25 #include "machtype.h"
  26 #include "devices.h"
  27
  28 #define AR71XX_SYS_TYPE_LEN     64
  29 #define AR71XX_BASE_FREQ        40000000
  30 #define AR91XX_BASE_FREQ        5000000
  31 #define AR724X_BASE_FREQ        5000000
  32
  33 u32 ar71xx_cpu_freq;
  34 EXPORT_SYMBOL_GPL(ar71xx_cpu_freq);
  35
  36 u32 ar71xx_ahb_freq;
  37 EXPORT_SYMBOL_GPL(ar71xx_ahb_freq);
  38
  39 u32 ar71xx_ddr_freq;
  40 EXPORT_SYMBOL_GPL(ar71xx_ddr_freq);
  41
  42 enum ar71xx_soc_type ar71xx_soc;
  43 EXPORT_SYMBOL_GPL(ar71xx_soc);
  44
  45 static char ar71xx_sys_type[AR71XX_SYS_TYPE_LEN];
  46
  47 static void ar71xx_restart(char *command)
  48 {
  49         ar71xx_device_stop(RESET_MODULE_FULL_CHIP);
  50         for (;;)
  51                 if (cpu_wait)
  52                         cpu_wait();
  53 }
  54
  55 static void ar71xx_halt(void)
  56 {
  57         while (1)
  58                 cpu_wait();
  59 }
  60
  61 static void __init ar71xx_detect_mem_size(void)
  62 {
  63         unsigned long size;
  64
  65         for (size = AR71XX_MEM_SIZE_MIN; size < AR71XX_MEM_SIZE_MAX;
  66              size <<= 1 ) {
  67                 if (!memcmp(ar71xx_detect_mem_size,
  68                             ar71xx_detect_mem_size + size, 1024))
  69                         break;
  70         }
  71
  72         add_memory_region(0, size, BOOT_MEM_RAM);
  73 }
  74
  75 static void __init ar71xx_detect_sys_type(void)
  76 {
  77         char *chip = "????";
  78         u32 id;
  79         u32 major;
  80         u32 minor;
  81         u32 rev = 0;
  82
  83         id = ar71xx_reset_rr(AR71XX_RESET_REG_REV_ID);
  84         major = id & REV_ID_MAJOR_MASK;
  85
  86         switch (major) {
  87         case REV_ID_MAJOR_AR71XX:
  88                 minor = id & AR71XX_REV_ID_MINOR_MASK;
  89                 rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
  90                 rev &= AR71XX_REV_ID_REVISION_MASK;
  91                 switch (minor) {
  92                 case AR71XX_REV_ID_MINOR_AR7130:
  93                         ar71xx_soc = AR71XX_SOC_AR7130;
  94                         chip = "7130";
  95                         break;
  96
  97                 case AR71XX_REV_ID_MINOR_AR7141:
  98                         ar71xx_soc = AR71XX_SOC_AR7141;
  99                         chip = "7141";
 100                         break;
 101
 102                 case AR71XX_REV_ID_MINOR_AR7161:
 103                         ar71xx_soc = AR71XX_SOC_AR7161;
 104                         chip = "7161";
 105                         break;
 106                 }
 107                 break;
 108
 109         case REV_ID_MAJOR_AR724X:
 110                 ar71xx_soc = AR71XX_SOC_AR7240;
 111                 chip = "7240";
 112                 rev = (id & AR724X_REV_ID_REVISION_MASK);
 113                 break;
 114
 115         case REV_ID_MAJOR_AR913X:
 116                 minor = id & AR91XX_REV_ID_MINOR_MASK;
 117                 rev = id >> AR91XX_REV_ID_REVISION_SHIFT;
 118                 rev &= AR91XX_REV_ID_REVISION_MASK;
 119                 switch (minor) {
 120                 case AR91XX_REV_ID_MINOR_AR9130:
 121                         ar71xx_soc = AR71XX_SOC_AR9130;
 122                         chip = "9130";
 123                         break;
 124
 125                 case AR91XX_REV_ID_MINOR_AR9132:
 126                         ar71xx_soc = AR71XX_SOC_AR9132;
 127                         chip = "9132";
 128                         break;
 129                 }
 130                 break;
 131
 132         default:
 133                 panic("ar71xx: unknown chip id:0x%08x\n", id);
 134         }
 135
 136         sprintf(ar71xx_sys_type, "Atheros AR%s rev %u", chip, rev);
 137 }
 138
 139 static void __init ar91xx_detect_sys_frequency(void)
 140 {
 141         u32 pll;
 142         u32 freq;
 143         u32 div;
 144
 145         pll = ar71xx_pll_rr(AR91XX_PLL_REG_CPU_CONFIG);
 146
 147         div = ((pll >> AR91XX_PLL_DIV_SHIFT) & AR91XX_PLL_DIV_MASK);
 148         freq = div * AR91XX_BASE_FREQ;
 149
 150         ar71xx_cpu_freq = freq;
 151
 152         div = ((pll >> AR91XX_DDR_DIV_SHIFT) & AR91XX_DDR_DIV_MASK) + 1;
 153         ar71xx_ddr_freq = freq / div;
 154
 155         div = (((pll >> AR91XX_AHB_DIV_SHIFT) & AR91XX_AHB_DIV_MASK) + 1) * 2;
 156         ar71xx_ahb_freq = ar71xx_cpu_freq / div;
 157 }
 158
 159 static void __init ar71xx_detect_sys_frequency(void)
 160 {
 161         u32 pll;
 162         u32 freq;
 163         u32 div;
 164
 165         pll = ar71xx_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);
 166
 167         div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1;
 168         freq = div * AR71XX_BASE_FREQ;
 169
 170         div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
 171         ar71xx_cpu_freq = freq / div;
 172
 173         div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
 174         ar71xx_ddr_freq = freq / div;
 175
 176         div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
 177         ar71xx_ahb_freq = ar71xx_cpu_freq / div;
 178 }
 179
 180 static void __init ar724x_detect_sys_frequency(void)
 181 {
 182         u32 pll;
 183         u32 freq;
 184         u32 div;
 185
 186         pll = ar71xx_pll_rr(AR724X_PLL_REG_CPU_CONFIG);
 187
 188         div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK);
 189         freq = div * AR724X_BASE_FREQ;
 190
 191         div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK);
 192         freq *= div;
 193
 194         ar71xx_cpu_freq = freq;
 195
 196         div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
 197         ar71xx_ddr_freq = freq / div;
 198
 199         div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
 200         ar71xx_ahb_freq = ar71xx_cpu_freq / div;
 201 }
 202
 203 static void __init detect_sys_frequency(void)
 204 {
 205         switch (ar71xx_soc) {
 206         case AR71XX_SOC_AR7130:
 207         case AR71XX_SOC_AR7141:
 208         case AR71XX_SOC_AR7161:
 209                 ar71xx_detect_sys_frequency();
 210                 break;
 211
 212         case AR71XX_SOC_AR7240:
 213                 ar724x_detect_sys_frequency();
 214                 break;
 215
 216         case AR71XX_SOC_AR9130:
 217         case AR71XX_SOC_AR9132:
 218                 ar91xx_detect_sys_frequency();
 219                 break;
 220
 221         default:
 222                 BUG();
 223         }
 224 }
 225
 226 const char *get_system_type(void)
 227 {
 228         return ar71xx_sys_type;
 229 }
 230
 231 unsigned int __cpuinit get_c0_compare_irq(void)
 232 {
 233         return CP0_LEGACY_COMPARE_IRQ;
 234 }
 235
 236 void __init plat_mem_setup(void)
 237 {
 238         set_io_port_base(KSEG1);
 239
 240         ar71xx_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE,
 241                                                 AR71XX_DDR_CTRL_SIZE);
 242
 243         ar71xx_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
 244                                                 AR71XX_PLL_SIZE);
 245
 246         ar71xx_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
 247                                                 AR71XX_RESET_SIZE);
 248
 249         ar71xx_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
 250
 251         ar71xx_usb_ctrl_base = ioremap_nocache(AR71XX_USB_CTRL_BASE,
 252                                                 AR71XX_USB_CTRL_SIZE);
 253
 254         ar71xx_detect_mem_size();
 255         ar71xx_detect_sys_type();
 256         detect_sys_frequency();
 257
 258         printk(KERN_INFO
 259                 "%s, CPU:%u.%03u MHz, AHB:%u.%03u MHz, DDR:%u.%03u MHz\n",
 260                 ar71xx_sys_type,
 261                 ar71xx_cpu_freq / 1000000, (ar71xx_cpu_freq / 1000) % 1000,
 262                 ar71xx_ahb_freq / 1000000, (ar71xx_ahb_freq / 1000) % 1000,
 263                 ar71xx_ddr_freq / 1000000, (ar71xx_ddr_freq / 1000) % 1000);
 264
 265         _machine_restart = ar71xx_restart;
 266         _machine_halt = ar71xx_halt;
 267         pm_power_off = ar71xx_halt;
 268 }
 269
 270 void __init plat_time_init(void)
 271 {
 272         mips_hpt_frequency = ar71xx_cpu_freq / 2;
 273 }
 274
 275 __setup("board=", mips_machtype_setup);
 276
 277 static int __init ar71xx_machine_setup(void)
 278 {
 279         ar71xx_gpio_init();
 280
 281         ar71xx_add_device_uart();
 282         ar71xx_add_device_wdt();
 283
 284         mips_machine_setup();
 285         return 0;
 286 }
 287
 288 arch_initcall(ar71xx_machine_setup);
 289
 290 static void __init ar71xx_generic_init(void)
 291 {
 292         /* Nothing to do */
 293 }
 294
 295 MIPS_MACHINE(AR71XX_MACH_GENERIC, "Generic", "Generic AR71xx board",
 296              ar71xx_generic_init);