2 * Atheros AR71xx SoC specific setup
4 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 * Parts of this file are based on Atheros' 2.6.15 BSP
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/init.h>
17 #include <linux/types.h>
18 #include <linux/pci.h>
19 #include <linux/serial_8250.h>
20 #include <linux/bootmem.h>
22 #include <asm/bootinfo.h>
23 #include <asm/traps.h>
24 #include <asm/time.h> /* for mips_hpt_frequency */
25 #include <asm/reboot.h> /* for _machine_{restart,halt} */
26 #include <asm/mips_machine.h>
28 #include <asm/mach-ar71xx/ar71xx.h>
29 #include <asm/mach-ar71xx/pci.h>
33 #define AR71XX_SYS_TYPE_LEN 64
34 #define AR71XX_BASE_FREQ 40000000
35 #define AR91XX_BASE_FREQ 5000000
37 enum ar71xx_mach_type ar71xx_mach;
40 EXPORT_SYMBOL_GPL(ar71xx_cpu_freq);
43 EXPORT_SYMBOL_GPL(ar71xx_ahb_freq);
46 EXPORT_SYMBOL_GPL(ar71xx_ddr_freq);
48 enum ar71xx_soc_type ar71xx_soc;
49 EXPORT_SYMBOL_GPL(ar71xx_soc);
51 int (*ar71xx_pci_bios_init)(unsigned nr_irqs,
52 struct ar71xx_pci_irq *map) __initdata;
54 int (*ar71xx_pci_be_handler)(int is_fixup);
56 static char ar71xx_sys_type[AR71XX_SYS_TYPE_LEN];
58 static void ar71xx_restart(char *command)
60 ar71xx_device_stop(RESET_MODULE_FULL_CHIP);
66 static void ar71xx_halt(void)
72 static int ar71xx_be_handler(struct pt_regs *regs, int is_fixup)
76 if (ar71xx_pci_be_handler)
77 err = ar71xx_pci_be_handler(is_fixup);
79 return (is_fixup && !err) ? MIPS_BE_FIXUP : MIPS_BE_FATAL;
82 int __init ar71xx_pci_init(unsigned nr_irqs, struct ar71xx_pci_irq *map)
84 if (!ar71xx_pci_bios_init)
87 return ar71xx_pci_bios_init(nr_irqs, map);
90 static void __init ar71xx_detect_mem_size(void)
94 for (size = AR71XX_MEM_SIZE_MIN; size < AR71XX_MEM_SIZE_MAX;
96 if (!memcmp(ar71xx_detect_mem_size,
97 ar71xx_detect_mem_size + size, 1024))
101 add_memory_region(0, size, BOOT_MEM_RAM);
104 static void __init ar71xx_detect_sys_type(void)
112 id = ar71xx_reset_rr(AR71XX_RESET_REG_REV_ID);
113 major = id & REV_ID_MAJOR_MASK;
116 case REV_ID_MAJOR_AR71XX:
117 minor = id & AR71XX_REV_ID_MINOR_MASK;
118 rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
119 rev &= AR71XX_REV_ID_REVISION_MASK;
121 case AR71XX_REV_ID_MINOR_AR7130:
122 ar71xx_soc = AR71XX_SOC_AR7130;
126 case AR71XX_REV_ID_MINOR_AR7141:
127 ar71xx_soc = AR71XX_SOC_AR7141;
131 case AR71XX_REV_ID_MINOR_AR7161:
132 ar71xx_soc = AR71XX_SOC_AR7161;
138 case REV_ID_MAJOR_AR724X:
139 ar71xx_soc = AR71XX_SOC_AR7240;
141 rev = (id & AR724X_REV_ID_REVISION_MASK);
144 case REV_ID_MAJOR_AR913X:
145 minor = id & AR91XX_REV_ID_MINOR_MASK;
146 rev = id >> AR91XX_REV_ID_REVISION_SHIFT;
147 rev &= AR91XX_REV_ID_REVISION_MASK;
149 case AR91XX_REV_ID_MINOR_AR9130:
150 ar71xx_soc = AR71XX_SOC_AR9130;
154 case AR91XX_REV_ID_MINOR_AR9132:
155 ar71xx_soc = AR71XX_SOC_AR9132;
162 panic("ar71xx: unknown chip id:0x%08x\n", id);
165 sprintf(ar71xx_sys_type, "Atheros AR%s rev %u", chip, rev);
168 static void __init ar91xx_detect_sys_frequency(void)
174 pll = ar71xx_pll_rr(AR91XX_PLL_REG_CPU_CONFIG);
176 div = ((pll >> AR91XX_PLL_DIV_SHIFT) & AR91XX_PLL_DIV_MASK);
177 freq = div * AR91XX_BASE_FREQ;
179 ar71xx_cpu_freq = freq;
181 div = ((pll >> AR91XX_DDR_DIV_SHIFT) & AR91XX_DDR_DIV_MASK) + 1;
182 ar71xx_ddr_freq = freq / div;
184 div = (((pll >> AR91XX_AHB_DIV_SHIFT) & AR91XX_AHB_DIV_MASK) + 1) * 2;
185 ar71xx_ahb_freq = ar71xx_cpu_freq / div;
188 static void __init ar71xx_detect_sys_frequency(void)
194 pll = ar71xx_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);
196 div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1;
197 freq = div * AR71XX_BASE_FREQ;
199 div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
200 ar71xx_cpu_freq = freq / div;
202 div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
203 ar71xx_ddr_freq = freq / div;
205 div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
206 ar71xx_ahb_freq = ar71xx_cpu_freq / div;
209 static void __init detect_sys_frequency(void)
211 switch (ar71xx_soc) {
212 case AR71XX_SOC_AR7130:
213 case AR71XX_SOC_AR7141:
214 case AR71XX_SOC_AR7161:
215 ar71xx_detect_sys_frequency();
218 case AR71XX_SOC_AR9130:
219 case AR71XX_SOC_AR9132:
220 ar91xx_detect_sys_frequency();
228 #ifdef CONFIG_AR71XX_EARLY_SERIAL
229 static void __init ar71xx_early_serial_setup(void)
233 memset(&p, 0, sizeof(p));
235 p.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP;
236 p.iotype = UPIO_MEM32;
237 p.uartclk = ar71xx_ahb_freq;
238 p.irq = AR71XX_MISC_IRQ_UART;
240 p.mapbase = AR71XX_UART_BASE;
242 early_serial_setup(&p);
245 static inline void ar71xx_early_serial_setup(void) {};
246 #endif /* CONFIG_AR71XX_EARLY_SERIAL */
248 const char *get_system_type(void)
250 return ar71xx_sys_type;
253 unsigned int __cpuinit get_c0_compare_irq(void)
255 return CP0_LEGACY_COMPARE_IRQ;
258 void __init plat_mem_setup(void)
260 set_io_port_base(KSEG1);
262 ar71xx_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE,
263 AR71XX_DDR_CTRL_SIZE);
265 ar71xx_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
268 ar71xx_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
271 ar71xx_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
273 ar71xx_usb_ctrl_base = ioremap_nocache(AR71XX_USB_CTRL_BASE,
274 AR71XX_USB_CTRL_SIZE);
276 ar71xx_detect_mem_size();
277 ar71xx_detect_sys_type();
278 detect_sys_frequency();
281 "%s, CPU:%u.%03u MHz, AHB:%u.%03u MHz, DDR:%u.%03u MHz\n",
283 ar71xx_cpu_freq / 1000000, (ar71xx_cpu_freq / 1000) % 1000,
284 ar71xx_ahb_freq / 1000000, (ar71xx_ahb_freq / 1000) % 1000,
285 ar71xx_ddr_freq / 1000000, (ar71xx_ddr_freq / 1000) % 1000);
287 _machine_restart = ar71xx_restart;
288 _machine_halt = ar71xx_halt;
289 pm_power_off = ar71xx_halt;
291 board_be_handler = ar71xx_be_handler;
293 ar71xx_early_serial_setup();
296 void __init plat_time_init(void)
298 mips_hpt_frequency = ar71xx_cpu_freq / 2;
301 static int __init ar71xx_machine_setup(void)
305 ar71xx_add_device_uart();
306 ar71xx_add_device_wdt();
308 mips_machine_setup(ar71xx_mach);
312 arch_initcall(ar71xx_machine_setup);