2 * Atheros AR71xx SoC specific setup
4 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 * Parts of this file are based on Atheros' 2.6.15 BSP
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/serial_8250.h>
17 #include <linux/bootmem.h>
19 #include <asm/bootinfo.h>
20 #include <asm/time.h> /* for mips_hpt_frequency */
21 #include <asm/reboot.h> /* for _machine_{restart,halt} */
22 #include <asm/mips_machine.h>
24 #include <asm/mach-ar71xx/ar71xx.h>
25 #include <asm/mach-ar71xx/pci.h>
29 #define AR71XX_SYS_TYPE_LEN 64
30 #define AR71XX_BASE_FREQ 40000000
31 #define AR91XX_BASE_FREQ 5000000
32 #define AR724X_BASE_FREQ 5000000
34 enum ar71xx_mach_type ar71xx_mach;
37 EXPORT_SYMBOL_GPL(ar71xx_cpu_freq);
40 EXPORT_SYMBOL_GPL(ar71xx_ahb_freq);
43 EXPORT_SYMBOL_GPL(ar71xx_ddr_freq);
45 enum ar71xx_soc_type ar71xx_soc;
46 EXPORT_SYMBOL_GPL(ar71xx_soc);
48 static char ar71xx_sys_type[AR71XX_SYS_TYPE_LEN];
50 static void ar71xx_restart(char *command)
52 ar71xx_device_stop(RESET_MODULE_FULL_CHIP);
58 static void ar71xx_halt(void)
64 static void __init ar71xx_detect_mem_size(void)
68 for (size = AR71XX_MEM_SIZE_MIN; size < AR71XX_MEM_SIZE_MAX;
70 if (!memcmp(ar71xx_detect_mem_size,
71 ar71xx_detect_mem_size + size, 1024))
75 add_memory_region(0, size, BOOT_MEM_RAM);
78 static void __init ar71xx_detect_sys_type(void)
86 id = ar71xx_reset_rr(AR71XX_RESET_REG_REV_ID);
87 major = id & REV_ID_MAJOR_MASK;
90 case REV_ID_MAJOR_AR71XX:
91 minor = id & AR71XX_REV_ID_MINOR_MASK;
92 rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
93 rev &= AR71XX_REV_ID_REVISION_MASK;
95 case AR71XX_REV_ID_MINOR_AR7130:
96 ar71xx_soc = AR71XX_SOC_AR7130;
100 case AR71XX_REV_ID_MINOR_AR7141:
101 ar71xx_soc = AR71XX_SOC_AR7141;
105 case AR71XX_REV_ID_MINOR_AR7161:
106 ar71xx_soc = AR71XX_SOC_AR7161;
112 case REV_ID_MAJOR_AR724X:
113 ar71xx_soc = AR71XX_SOC_AR7240;
115 rev = (id & AR724X_REV_ID_REVISION_MASK);
118 case REV_ID_MAJOR_AR913X:
119 minor = id & AR91XX_REV_ID_MINOR_MASK;
120 rev = id >> AR91XX_REV_ID_REVISION_SHIFT;
121 rev &= AR91XX_REV_ID_REVISION_MASK;
123 case AR91XX_REV_ID_MINOR_AR9130:
124 ar71xx_soc = AR71XX_SOC_AR9130;
128 case AR91XX_REV_ID_MINOR_AR9132:
129 ar71xx_soc = AR71XX_SOC_AR9132;
136 panic("ar71xx: unknown chip id:0x%08x\n", id);
139 sprintf(ar71xx_sys_type, "Atheros AR%s rev %u", chip, rev);
142 static void __init ar91xx_detect_sys_frequency(void)
148 pll = ar71xx_pll_rr(AR91XX_PLL_REG_CPU_CONFIG);
150 div = ((pll >> AR91XX_PLL_DIV_SHIFT) & AR91XX_PLL_DIV_MASK);
151 freq = div * AR91XX_BASE_FREQ;
153 ar71xx_cpu_freq = freq;
155 div = ((pll >> AR91XX_DDR_DIV_SHIFT) & AR91XX_DDR_DIV_MASK) + 1;
156 ar71xx_ddr_freq = freq / div;
158 div = (((pll >> AR91XX_AHB_DIV_SHIFT) & AR91XX_AHB_DIV_MASK) + 1) * 2;
159 ar71xx_ahb_freq = ar71xx_cpu_freq / div;
162 static void __init ar71xx_detect_sys_frequency(void)
168 pll = ar71xx_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);
170 div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1;
171 freq = div * AR71XX_BASE_FREQ;
173 div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
174 ar71xx_cpu_freq = freq / div;
176 div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
177 ar71xx_ddr_freq = freq / div;
179 div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
180 ar71xx_ahb_freq = ar71xx_cpu_freq / div;
183 static void __init ar724x_detect_sys_frequency(void)
189 pll = ar71xx_pll_rr(AR724X_PLL_REG_CPU_CONFIG);
191 div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK);
192 freq = div * AR724X_BASE_FREQ;
194 div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK);
197 ar71xx_cpu_freq = freq;
199 div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
200 ar71xx_ddr_freq = freq / div;
202 div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
203 ar71xx_ahb_freq = ar71xx_cpu_freq / div;
206 static void __init detect_sys_frequency(void)
208 switch (ar71xx_soc) {
209 case AR71XX_SOC_AR7130:
210 case AR71XX_SOC_AR7141:
211 case AR71XX_SOC_AR7161:
212 ar71xx_detect_sys_frequency();
215 case AR71XX_SOC_AR7240:
216 ar724x_detect_sys_frequency();
219 case AR71XX_SOC_AR9130:
220 case AR71XX_SOC_AR9132:
221 ar91xx_detect_sys_frequency();
229 #ifdef CONFIG_AR71XX_EARLY_SERIAL
230 static void __init ar71xx_early_serial_setup(void)
234 memset(&p, 0, sizeof(p));
236 p.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP;
237 p.iotype = UPIO_MEM32;
238 p.uartclk = ar71xx_ahb_freq;
239 p.irq = AR71XX_MISC_IRQ_UART;
241 p.mapbase = AR71XX_UART_BASE;
243 early_serial_setup(&p);
246 static inline void ar71xx_early_serial_setup(void) {};
247 #endif /* CONFIG_AR71XX_EARLY_SERIAL */
249 const char *get_system_type(void)
251 return ar71xx_sys_type;
254 unsigned int __cpuinit get_c0_compare_irq(void)
256 return CP0_LEGACY_COMPARE_IRQ;
259 void __init plat_mem_setup(void)
261 set_io_port_base(KSEG1);
263 ar71xx_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE,
264 AR71XX_DDR_CTRL_SIZE);
266 ar71xx_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
269 ar71xx_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
272 ar71xx_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
274 ar71xx_usb_ctrl_base = ioremap_nocache(AR71XX_USB_CTRL_BASE,
275 AR71XX_USB_CTRL_SIZE);
277 ar71xx_detect_mem_size();
278 ar71xx_detect_sys_type();
279 detect_sys_frequency();
282 "%s, CPU:%u.%03u MHz, AHB:%u.%03u MHz, DDR:%u.%03u MHz\n",
284 ar71xx_cpu_freq / 1000000, (ar71xx_cpu_freq / 1000) % 1000,
285 ar71xx_ahb_freq / 1000000, (ar71xx_ahb_freq / 1000) % 1000,
286 ar71xx_ddr_freq / 1000000, (ar71xx_ddr_freq / 1000) % 1000);
288 _machine_restart = ar71xx_restart;
289 _machine_halt = ar71xx_halt;
290 pm_power_off = ar71xx_halt;
292 ar71xx_early_serial_setup();
295 void __init plat_time_init(void)
297 mips_hpt_frequency = ar71xx_cpu_freq / 2;
300 static int __init ar71xx_machine_setup(void)
304 ar71xx_add_device_uart();
305 ar71xx_add_device_wdt();
307 mips_machine_setup(ar71xx_mach);
311 arch_initcall(ar71xx_machine_setup);