target/linux/ar71xx/files/arch/mips/ar71xx/setup.c

   1 /*
   2  *  Atheros AR71xx SoC specific setup
   3  *
   4  *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
   5  *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
   6  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   7  *
   8  *  Parts of this file are based on Atheros 2.6.15 BSP
   9  *  Parts of this file are based on Atheros 2.6.31 BSP
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License version 2 as published
  13  *  by the Free Software Foundation.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/bootmem.h>
  19
  20 #include <asm/bootinfo.h>
  21 #include <asm/time.h>           /* for mips_hpt_frequency */
  22 #include <asm/reboot.h>         /* for _machine_{restart,halt} */
  23 #include <asm/mips_machine.h>
  24
  25 #include <asm/mach-ar71xx/ar71xx.h>
  26
  27 #include "machtype.h"
  28 #include "devices.h"
  29
  30 #define AR71XX_SYS_TYPE_LEN     64
  31
  32 u32 ar71xx_cpu_freq;
  33 EXPORT_SYMBOL_GPL(ar71xx_cpu_freq);
  34
  35 u32 ar71xx_ahb_freq;
  36 EXPORT_SYMBOL_GPL(ar71xx_ahb_freq);
  37
  38 u32 ar71xx_ddr_freq;
  39 EXPORT_SYMBOL_GPL(ar71xx_ddr_freq);
  40
  41 u32 ar71xx_ref_freq;
  42 EXPORT_SYMBOL_GPL(ar71xx_ref_freq);
  43
  44 enum ar71xx_soc_type ar71xx_soc;
  45 EXPORT_SYMBOL_GPL(ar71xx_soc);
  46
  47 static char ar71xx_sys_type[AR71XX_SYS_TYPE_LEN];
  48
  49 static void ar71xx_restart(char *command)
  50 {
  51         ar71xx_device_stop(RESET_MODULE_FULL_CHIP);
  52         for (;;)
  53                 if (cpu_wait)
  54                         cpu_wait();
  55 }
  56
  57 static void ar71xx_halt(void)
  58 {
  59         while (1)
  60                 cpu_wait();
  61 }
  62
  63 static void __init ar71xx_detect_mem_size(void)
  64 {
  65         unsigned long size;
  66
  67         for (size = AR71XX_MEM_SIZE_MIN; size < AR71XX_MEM_SIZE_MAX;
  68              size <<= 1) {
  69                 if (!memcmp(ar71xx_detect_mem_size,
  70                             ar71xx_detect_mem_size + size, 1024))
  71                         break;
  72         }
  73
  74         add_memory_region(0, size, BOOT_MEM_RAM);
  75 }
  76
  77 static void __init ar71xx_detect_sys_type(void)
  78 {
  79         char *chip = "????";
  80         u32 id;
  81         u32 major;
  82         u32 minor;
  83         u32 rev = 0;
  84
  85         id = ar71xx_reset_rr(AR71XX_RESET_REG_REV_ID);
  86         major = id & REV_ID_MAJOR_MASK;
  87
  88         switch (major) {
  89         case REV_ID_MAJOR_AR71XX:
  90                 minor = id & AR71XX_REV_ID_MINOR_MASK;
  91                 rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
  92                 rev &= AR71XX_REV_ID_REVISION_MASK;
  93                 switch (minor) {
  94                 case AR71XX_REV_ID_MINOR_AR7130:
  95                         ar71xx_soc = AR71XX_SOC_AR7130;
  96                         chip = "7130";
  97                         break;
  98
  99                 case AR71XX_REV_ID_MINOR_AR7141:
 100                         ar71xx_soc = AR71XX_SOC_AR7141;
 101                         chip = "7141";
 102                         break;
 103
 104                 case AR71XX_REV_ID_MINOR_AR7161:
 105                         ar71xx_soc = AR71XX_SOC_AR7161;
 106                         chip = "7161";
 107                         break;
 108                 }
 109                 break;
 110
 111         case REV_ID_MAJOR_AR7240:
 112                 ar71xx_soc = AR71XX_SOC_AR7240;
 113                 chip = "7240";
 114                 rev = id & AR724X_REV_ID_REVISION_MASK;
 115                 break;
 116
 117         case REV_ID_MAJOR_AR7241:
 118                 ar71xx_soc = AR71XX_SOC_AR7241;
 119                 chip = "7241";
 120                 rev = id & AR724X_REV_ID_REVISION_MASK;
 121                 break;
 122
 123         case REV_ID_MAJOR_AR7242:
 124                 ar71xx_soc = AR71XX_SOC_AR7242;
 125                 chip = "7242";
 126                 rev = id & AR724X_REV_ID_REVISION_MASK;
 127                 break;
 128
 129         case REV_ID_MAJOR_AR913X:
 130                 minor = id & AR91XX_REV_ID_MINOR_MASK;
 131                 rev = id >> AR91XX_REV_ID_REVISION_SHIFT;
 132                 rev &= AR91XX_REV_ID_REVISION_MASK;
 133                 switch (minor) {
 134                 case AR91XX_REV_ID_MINOR_AR9130:
 135                         ar71xx_soc = AR71XX_SOC_AR9130;
 136                         chip = "9130";
 137                         break;
 138
 139                 case AR91XX_REV_ID_MINOR_AR9132:
 140                         ar71xx_soc = AR71XX_SOC_AR9132;
 141                         chip = "9132";
 142                         break;
 143                 }
 144                 break;
 145
 146         case REV_ID_MAJOR_AR9341:
 147                 ar71xx_soc = AR71XX_SOC_AR9341;
 148                 chip = "9341";
 149                 rev = id & AR934X_REV_ID_REVISION_MASK;
 150                 break;
 151
 152         case REV_ID_MAJOR_AR9342:
 153                 ar71xx_soc = AR71XX_SOC_AR9342;
 154                 chip = "9342";
 155                 rev = id & AR934X_REV_ID_REVISION_MASK;
 156                 break;
 157
 158         case REV_ID_MAJOR_AR9344:
 159                 ar71xx_soc = AR71XX_SOC_AR9344;
 160                 chip = "9344";
 161                 rev = id & AR934X_REV_ID_REVISION_MASK;
 162                 break;
 163
 164         default:
 165                 panic("ar71xx: unknown chip id:0x%08x\n", id);
 166         }
 167
 168         sprintf(ar71xx_sys_type, "Atheros AR%s rev %u", chip, rev);
 169         pr_info("SoC: %s\n", ar71xx_sys_type);
 170 }
 171
 172 static void __init ar934x_detect_sys_frequency(void)
 173 {
 174         u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
 175
 176         if (ar71xx_reset_rr(AR934X_RESET_REG_BOOTSTRAP) & AR934X_REF_CLK_40)
 177                 ar71xx_ref_freq = 40 * 1000 * 1000;
 178         else
 179                 ar71xx_ref_freq = 25 * 1000 * 1000;
 180
 181         clk_ctrl = ar71xx_pll_rr(AR934X_PLL_REG_DDR_CTRL_CLOCK);
 182
 183         pll = ar71xx_pll_rr(AR934X_PLL_REG_CPU_CONFIG);
 184         out_div = AR934X_CPU_PLL_CFG_OUTDIV_GET(pll);
 185         ref_div = AR934X_CPU_PLL_CFG_REFDIV_GET(pll);
 186         nint    = AR934X_CPU_PLL_CFG_NINT_GET(pll);
 187         frac    = AR934X_CPU_PLL_CFG_NFRAC_GET(pll);
 188         postdiv = AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_GET(clk_ctrl);
 189         ar71xx_cpu_freq = ((nint * ar71xx_ref_freq / ref_div) >> out_div) /
 190                           (postdiv + 1);
 191
 192         out_div = AR934X_DDR_PLL_CFG_OUTDIV_GET(pll);
 193         ref_div = AR934X_DDR_PLL_CFG_REFDIV_GET(pll);
 194         nint    = AR934X_DDR_PLL_CFG_NINT_GET(pll);
 195         frac    = AR934X_DDR_PLL_CFG_NFRAC_GET(pll);
 196         postdiv = AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_GET(clk_ctrl);
 197         ar71xx_ddr_freq = ((nint * ar71xx_ref_freq / ref_div) >> out_div) /
 198                           (postdiv + 1);
 199
 200         postdiv = AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_GET(clk_ctrl);
 201
 202         if (AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_GET(clk_ctrl)) {
 203                 ar71xx_ahb_freq = ar71xx_ddr_freq / (postdiv + 1);
 204         } else {
 205                 ar71xx_ahb_freq = ar71xx_cpu_freq / (postdiv + 1);
 206         }
 207
 208 }
 209
 210 static void __init ar91xx_detect_sys_frequency(void)
 211 {
 212         u32 pll;
 213         u32 freq;
 214         u32 div;
 215
 216         ar71xx_ref_freq = 5 * 1000 * 1000;
 217
 218         pll = ar71xx_pll_rr(AR91XX_PLL_REG_CPU_CONFIG);
 219
 220         div = ((pll >> AR91XX_PLL_DIV_SHIFT) & AR91XX_PLL_DIV_MASK);
 221         freq = div * ar71xx_ref_freq;
 222
 223         ar71xx_cpu_freq = freq;
 224
 225         div = ((pll >> AR91XX_DDR_DIV_SHIFT) & AR91XX_DDR_DIV_MASK) + 1;
 226         ar71xx_ddr_freq = freq / div;
 227
 228         div = (((pll >> AR91XX_AHB_DIV_SHIFT) & AR91XX_AHB_DIV_MASK) + 1) * 2;
 229         ar71xx_ahb_freq = ar71xx_cpu_freq / div;
 230 }
 231
 232 static void __init ar71xx_detect_sys_frequency(void)
 233 {
 234         u32 pll;
 235         u32 freq;
 236         u32 div;
 237
 238         ar71xx_ref_freq = 40 * 1000 * 1000;
 239
 240         pll = ar71xx_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);
 241
 242         div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1;
 243         freq = div * ar71xx_ref_freq;
 244
 245         div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
 246         ar71xx_cpu_freq = freq / div;
 247
 248         div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
 249         ar71xx_ddr_freq = freq / div;
 250
 251         div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
 252         ar71xx_ahb_freq = ar71xx_cpu_freq / div;
 253 }
 254
 255 static void __init ar724x_detect_sys_frequency(void)
 256 {
 257         u32 pll;
 258         u32 freq;
 259         u32 div;
 260
 261         ar71xx_ref_freq = 5 * 1000 * 1000;
 262
 263         pll = ar71xx_pll_rr(AR724X_PLL_REG_CPU_CONFIG);
 264
 265         div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK);
 266         freq = div * ar71xx_ref_freq;
 267
 268         div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK);
 269         freq *= div;
 270
 271         ar71xx_cpu_freq = freq;
 272
 273         div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
 274         ar71xx_ddr_freq = freq / div;
 275
 276         div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
 277         ar71xx_ahb_freq = ar71xx_cpu_freq / div;
 278 }
 279
 280 static void __init detect_sys_frequency(void)
 281 {
 282         switch (ar71xx_soc) {
 283         case AR71XX_SOC_AR7130:
 284         case AR71XX_SOC_AR7141:
 285         case AR71XX_SOC_AR7161:
 286                 ar71xx_detect_sys_frequency();
 287                 break;
 288
 289         case AR71XX_SOC_AR7240:
 290         case AR71XX_SOC_AR7241:
 291         case AR71XX_SOC_AR7242:
 292                 ar724x_detect_sys_frequency();
 293                 break;
 294
 295         case AR71XX_SOC_AR9130:
 296         case AR71XX_SOC_AR9132:
 297                 ar91xx_detect_sys_frequency();
 298                 break;
 299
 300         case AR71XX_SOC_AR9341:
 301         case AR71XX_SOC_AR9342:
 302         case AR71XX_SOC_AR9344:
 303                 ar934x_detect_sys_frequency();
 304                 break;
 305         default:
 306                 BUG();
 307         }
 308 }
 309
 310 const char *get_system_type(void)
 311 {
 312         return ar71xx_sys_type;
 313 }
 314
 315 unsigned int __cpuinit get_c0_compare_irq(void)
 316 {
 317         return CP0_LEGACY_COMPARE_IRQ;
 318 }
 319
 320 void __init plat_mem_setup(void)
 321 {
 322         set_io_port_base(KSEG1);
 323
 324         ar71xx_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE,
 325                                                 AR71XX_DDR_CTRL_SIZE);
 326
 327         ar71xx_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
 328                                                 AR71XX_PLL_SIZE);
 329
 330         ar71xx_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
 331                                                 AR71XX_RESET_SIZE);
 332
 333         ar71xx_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
 334
 335         ar71xx_usb_ctrl_base = ioremap_nocache(AR71XX_USB_CTRL_BASE,
 336                                                 AR71XX_USB_CTRL_SIZE);
 337
 338         ar71xx_detect_mem_size();
 339         ar71xx_detect_sys_type();
 340         detect_sys_frequency();
 341
 342         pr_info("Clocks: CPU:%u.%03uMHz, DDR:%u.%03uMHz, AHB:%u.%03uMHz, "
 343                 "Ref:%u.%03uMHz",
 344                 ar71xx_cpu_freq / 1000000, (ar71xx_cpu_freq / 1000) % 1000,
 345                 ar71xx_ddr_freq / 1000000, (ar71xx_ddr_freq / 1000) % 1000,
 346                 ar71xx_ahb_freq / 1000000, (ar71xx_ahb_freq / 1000) % 1000,
 347                 ar71xx_ref_freq / 1000000, (ar71xx_ref_freq / 1000) % 1000);
 348
 349         _machine_restart = ar71xx_restart;
 350         _machine_halt = ar71xx_halt;
 351         pm_power_off = ar71xx_halt;
 352 }
 353
 354 void __init plat_time_init(void)
 355 {
 356         mips_hpt_frequency = ar71xx_cpu_freq / 2;
 357 }
 358
 359 __setup("board=", mips_machtype_setup);
 360
 361 static int __init ar71xx_machine_setup(void)
 362 {
 363         ar71xx_gpio_init();
 364
 365         ar71xx_add_device_uart();
 366         ar71xx_add_device_wdt();
 367
 368         mips_machine_setup();
 369         return 0;
 370 }
 371
 372 arch_initcall(ar71xx_machine_setup);
 373
 374 static void __init ar71xx_generic_init(void)
 375 {
 376         /* Nothing to do */
 377 }
 378
 379 MIPS_MACHINE(AR71XX_MACH_GENERIC, "Generic", "Generic AR71xx board",
 380              ar71xx_generic_init);