2 * Atheros AR71xx SoC specific setup
4 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 * Parts of this file are based on Atheros' 2.6.15 BSP
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/serial_8250.h>
17 #include <linux/bootmem.h>
19 #include <asm/bootinfo.h>
20 #include <asm/time.h> /* for mips_hpt_frequency */
21 #include <asm/reboot.h> /* for _machine_{restart,halt} */
22 #include <asm/mips_machine.h>
24 #include <asm/mach-ar71xx/ar71xx.h>
25 #include <asm/mach-ar71xx/pci.h>
30 #define AR71XX_SYS_TYPE_LEN 64
31 #define AR71XX_BASE_FREQ 40000000
32 #define AR91XX_BASE_FREQ 5000000
33 #define AR724X_BASE_FREQ 5000000
36 EXPORT_SYMBOL_GPL(ar71xx_cpu_freq);
39 EXPORT_SYMBOL_GPL(ar71xx_ahb_freq);
42 EXPORT_SYMBOL_GPL(ar71xx_ddr_freq);
44 enum ar71xx_soc_type ar71xx_soc;
45 EXPORT_SYMBOL_GPL(ar71xx_soc);
47 static char ar71xx_sys_type[AR71XX_SYS_TYPE_LEN];
49 static void ar71xx_restart(char *command)
51 ar71xx_device_stop(RESET_MODULE_FULL_CHIP);
57 static void ar71xx_halt(void)
63 static void __init ar71xx_detect_mem_size(void)
67 for (size = AR71XX_MEM_SIZE_MIN; size < AR71XX_MEM_SIZE_MAX;
69 if (!memcmp(ar71xx_detect_mem_size,
70 ar71xx_detect_mem_size + size, 1024))
74 add_memory_region(0, size, BOOT_MEM_RAM);
77 static void __init ar71xx_detect_sys_type(void)
85 id = ar71xx_reset_rr(AR71XX_RESET_REG_REV_ID);
86 major = id & REV_ID_MAJOR_MASK;
89 case REV_ID_MAJOR_AR71XX:
90 minor = id & AR71XX_REV_ID_MINOR_MASK;
91 rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
92 rev &= AR71XX_REV_ID_REVISION_MASK;
94 case AR71XX_REV_ID_MINOR_AR7130:
95 ar71xx_soc = AR71XX_SOC_AR7130;
99 case AR71XX_REV_ID_MINOR_AR7141:
100 ar71xx_soc = AR71XX_SOC_AR7141;
104 case AR71XX_REV_ID_MINOR_AR7161:
105 ar71xx_soc = AR71XX_SOC_AR7161;
111 case REV_ID_MAJOR_AR724X:
112 ar71xx_soc = AR71XX_SOC_AR7240;
114 rev = (id & AR724X_REV_ID_REVISION_MASK);
117 case REV_ID_MAJOR_AR913X:
118 minor = id & AR91XX_REV_ID_MINOR_MASK;
119 rev = id >> AR91XX_REV_ID_REVISION_SHIFT;
120 rev &= AR91XX_REV_ID_REVISION_MASK;
122 case AR91XX_REV_ID_MINOR_AR9130:
123 ar71xx_soc = AR71XX_SOC_AR9130;
127 case AR91XX_REV_ID_MINOR_AR9132:
128 ar71xx_soc = AR71XX_SOC_AR9132;
135 panic("ar71xx: unknown chip id:0x%08x\n", id);
138 sprintf(ar71xx_sys_type, "Atheros AR%s rev %u", chip, rev);
141 static void __init ar91xx_detect_sys_frequency(void)
147 pll = ar71xx_pll_rr(AR91XX_PLL_REG_CPU_CONFIG);
149 div = ((pll >> AR91XX_PLL_DIV_SHIFT) & AR91XX_PLL_DIV_MASK);
150 freq = div * AR91XX_BASE_FREQ;
152 ar71xx_cpu_freq = freq;
154 div = ((pll >> AR91XX_DDR_DIV_SHIFT) & AR91XX_DDR_DIV_MASK) + 1;
155 ar71xx_ddr_freq = freq / div;
157 div = (((pll >> AR91XX_AHB_DIV_SHIFT) & AR91XX_AHB_DIV_MASK) + 1) * 2;
158 ar71xx_ahb_freq = ar71xx_cpu_freq / div;
161 static void __init ar71xx_detect_sys_frequency(void)
167 pll = ar71xx_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);
169 div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1;
170 freq = div * AR71XX_BASE_FREQ;
172 div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
173 ar71xx_cpu_freq = freq / div;
175 div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
176 ar71xx_ddr_freq = freq / div;
178 div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
179 ar71xx_ahb_freq = ar71xx_cpu_freq / div;
182 static void __init ar724x_detect_sys_frequency(void)
188 pll = ar71xx_pll_rr(AR724X_PLL_REG_CPU_CONFIG);
190 div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK);
191 freq = div * AR724X_BASE_FREQ;
193 div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK);
196 ar71xx_cpu_freq = freq;
198 div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
199 ar71xx_ddr_freq = freq / div;
201 div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
202 ar71xx_ahb_freq = ar71xx_cpu_freq / div;
205 static void __init detect_sys_frequency(void)
207 switch (ar71xx_soc) {
208 case AR71XX_SOC_AR7130:
209 case AR71XX_SOC_AR7141:
210 case AR71XX_SOC_AR7161:
211 ar71xx_detect_sys_frequency();
214 case AR71XX_SOC_AR7240:
215 ar724x_detect_sys_frequency();
218 case AR71XX_SOC_AR9130:
219 case AR71XX_SOC_AR9132:
220 ar91xx_detect_sys_frequency();
228 const char *get_system_type(void)
230 return ar71xx_sys_type;
233 unsigned int __cpuinit get_c0_compare_irq(void)
235 return CP0_LEGACY_COMPARE_IRQ;
238 void __init plat_mem_setup(void)
240 set_io_port_base(KSEG1);
242 ar71xx_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE,
243 AR71XX_DDR_CTRL_SIZE);
245 ar71xx_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
248 ar71xx_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
251 ar71xx_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
253 ar71xx_usb_ctrl_base = ioremap_nocache(AR71XX_USB_CTRL_BASE,
254 AR71XX_USB_CTRL_SIZE);
256 ar71xx_detect_mem_size();
257 ar71xx_detect_sys_type();
258 detect_sys_frequency();
261 "%s, CPU:%u.%03u MHz, AHB:%u.%03u MHz, DDR:%u.%03u MHz\n",
263 ar71xx_cpu_freq / 1000000, (ar71xx_cpu_freq / 1000) % 1000,
264 ar71xx_ahb_freq / 1000000, (ar71xx_ahb_freq / 1000) % 1000,
265 ar71xx_ddr_freq / 1000000, (ar71xx_ddr_freq / 1000) % 1000);
267 _machine_restart = ar71xx_restart;
268 _machine_halt = ar71xx_halt;
269 pm_power_off = ar71xx_halt;
272 void __init plat_time_init(void)
274 mips_hpt_frequency = ar71xx_cpu_freq / 2;
277 __setup("board=", mips_machtype_setup);
279 static int __init ar71xx_machine_setup(void)
283 ar71xx_add_device_uart();
284 ar71xx_add_device_wdt();
286 mips_machine_setup();
290 arch_initcall(ar71xx_machine_setup);
292 static void __init ar71xx_generic_init(void)
297 MIPS_MACHINE(AR71XX_MACH_GENERIC, "Generic", "Generic AR71xx board",
298 ar71xx_generic_init);