target/linux/ar71xx/files/arch/mips/ar71xx/mach-dir-825-b1.c

   1 /*
   2  *  D-Link DIR-825 rev. B1 board support
   3  *
   4  *  Copyright (C) 2009 Lukas Kuna, Evkanet, s.r.o.
   5  *
   6  *  based on mach-wndr3700.c
   7  *
   8  *  This program is free software; you can redistribute it and/or modify it
   9  *  under the terms of the GNU General Public License version 2 as published
  10  *  by the Free Software Foundation.
  11  */
  12
  13 #include <linux/platform_device.h>
  14 #include <linux/mtd/mtd.h>
  15 #include <linux/mtd/partitions.h>
  16 #include <linux/spi/spi.h>
  17 #include <linux/spi/flash.h>
  18 #include <linux/input.h>
  19 #include <linux/pci.h>
  20 #include <linux/ath9k_platform.h>
  21 #include <linux/delay.h>
  22
  23 #include <asm/mips_machine.h>
  24 #include <asm/mach-ar71xx/ar71xx.h>
  25 #include <asm/mach-ar71xx/pci.h>
  26
  27 #include "devices.h"
  28
  29 #define DIR825B1_GPIO_LED_BLUE_USB              0
  30 #define DIR825B1_GPIO_LED_ORANGE_POWER          1
  31 #define DIR825B1_GPIO_LED_BLUE_POWER            2
  32 #define DIR825B1_GPIO_LED_BLUE_POWERSAVE        4
  33 #define DIR825B1_GPIO_LED_ORANGE_PLANET         6
  34 #define DIR825B1_GPIO_LED_BLUE_PLANET           11
  35
  36 #define DIR825B1_GPIO_BTN_RESET                 3
  37 #define DIR825B1_GPIO_BTN_POWERSAVE             8
  38
  39 #define DIR825B1_BUTTONS_POLL_INTERVAL          20
  40
  41 #define DIR825B1_CAL_LOCATION_0                 0x1f661000
  42 #define DIR825B1_CAL_LOCATION_1                 0x1f665000
  43
  44 #define DIR825B1_MAC_LOCATION_0                 0x2ffa81b8
  45 #define DIR825B1_MAC_LOCATION_1                 0x2ffa8370
  46
  47 static struct ath9k_platform_data dir825b1_wmac0_data;
  48 static struct ath9k_platform_data dir825b1_wmac1_data;
  49 static char dir825b1_wmac0_mac[6];
  50 static char dir825b1_wmac1_mac[6];
  51
  52 #ifdef CONFIG_MTD_PARTITIONS
  53 static struct mtd_partition dir825b1_partitions[] = {
  54         {
  55                 .name           = "uboot",
  56                 .offset         = 0,
  57                 .size           = 0x040000,
  58                 .mask_flags     = MTD_WRITEABLE,
  59         } , {
  60                 .name           = "config",
  61                 .offset         = 0x040000,
  62                 .size           = 0x010000,
  63                 .mask_flags     = MTD_WRITEABLE,
  64         } , {
  65                 .name           = "firmware",
  66                 .offset         = 0x050000,
  67                 .size           = 0x610000,
  68         } , {
  69                 .name           = "caldata",
  70                 .offset         = 0x660000,
  71                 .size           = 0x010000,
  72                 .mask_flags     = MTD_WRITEABLE,
  73         }
  74 };
  75 #endif /* CONFIG_MTD_PARTITIONS */
  76
  77 static struct flash_platform_data dir825b1_flash_data = {
  78 #ifdef CONFIG_MTD_PARTITIONS
  79         .parts          = dir825b1_partitions,
  80         .nr_parts       = ARRAY_SIZE(dir825b1_partitions),
  81 #endif
  82 };
  83
  84 static struct spi_board_info dir825b1_spi_info[] = {
  85         {
  86                 .bus_num        = 0,
  87                 .chip_select    = 0,
  88                 .max_speed_hz   = 25000000,
  89                 .modalias       = "m25p80",
  90                 .platform_data  = &dir825b1_flash_data,
  91         }
  92 };
  93
  94 static struct gpio_led dir825b1_leds_gpio[] __initdata = {
  95         {
  96                 .name           = "dir825b1:blue:usb",
  97                 .gpio           = DIR825B1_GPIO_LED_BLUE_USB,
  98                 .active_low     = 1,
  99         }, {
 100                 .name           = "dir825b1:orange:power",
 101                 .gpio           = DIR825B1_GPIO_LED_ORANGE_POWER,
 102                 .active_low     = 1,
 103         }, {
 104                 .name           = "dir825b1:blue:power",
 105                 .gpio           = DIR825B1_GPIO_LED_BLUE_POWER,
 106                 .active_low     = 1,
 107         }, {
 108                 .name           = "dir825b1:blue:powersave",
 109                 .gpio           = DIR825B1_GPIO_LED_BLUE_POWERSAVE,
 110                 .active_low     = 1,
 111         }, {
 112                 .name           = "dir825b1:orange:planet",
 113                 .gpio           = DIR825B1_GPIO_LED_ORANGE_PLANET,
 114                 .active_low     = 1,
 115         }, {
 116                 .name           = "dir825b1:blue:planet",
 117                 .gpio           = DIR825B1_GPIO_LED_BLUE_PLANET,
 118                 .active_low     = 1,
 119         }
 120 };
 121
 122 static struct gpio_button dir825b1_gpio_buttons[] __initdata = {
 123         {
 124                 .desc           = "reset",
 125                 .type           = EV_KEY,
 126                 .code           = BTN_0,
 127                 .threshold      = 5,
 128                 .gpio           = DIR825B1_GPIO_BTN_RESET,
 129                 .active_low     = 1,
 130         } , {
 131                 .desc           = "powersave",
 132                 .type           = EV_KEY,
 133                 .code           = BTN_1,
 134                 .threshold      = 5,
 135                 .gpio           = DIR825B1_GPIO_BTN_POWERSAVE,
 136                 .active_low     = 1,
 137         }
 138 };
 139
 140 #ifdef CONFIG_PCI
 141 static struct ar71xx_pci_irq dir825b1_pci_irqs[] __initdata = {
 142         {
 143                 .slot   = 0,
 144                 .pin    = 1,
 145                 .irq    = AR71XX_PCI_IRQ_DEV0,
 146         }, {
 147                 .slot   = 1,
 148                 .pin    = 1,
 149                 .irq    = AR71XX_PCI_IRQ_DEV1,
 150         }
 151 };
 152
 153 static int dir825b1_pci_plat_dev_init(struct pci_dev *dev)
 154 {
 155         switch(PCI_SLOT(dev->devfn)) {
 156         case 17:
 157                 dev->dev.platform_data = &dir825b1_wmac0_data;
 158                 break;
 159
 160         case 18:
 161                 dev->dev.platform_data = &dir825b1_wmac1_data;
 162                 break;
 163         }
 164
 165         return 0;
 166 }
 167
 168 static void dir825b1_pci_fixup(struct pci_dev *dev)
 169 {
 170         void __iomem *mem;
 171         u16 *cal_data;
 172         u16 cmd;
 173         u32 bar0;
 174         u32 val;
 175
 176         if (ar71xx_mach != AR71XX_MACH_DIR_825_B1)
 177                 return;
 178
 179         dir825b1_pci_plat_dev_init(dev);
 180         cal_data = dev->dev.platform_data;
 181
 182         if (*cal_data != 0xa55a) {
 183                 printk(KERN_ERR "PCI: no calibration data found for %s\n",
 184                        pci_name(dev));
 185                 return;
 186         }
 187
 188         mem = ioremap(AR71XX_PCI_MEM_BASE, 0x10000);
 189         if (!mem) {
 190                 printk(KERN_ERR "PCI: ioremap error for device %s\n",
 191                        pci_name(dev));
 192                 return;
 193         }
 194
 195         printk(KERN_INFO "PCI: fixup device %s\n", pci_name(dev));
 196
 197         pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar0);
 198
 199         /* Setup the PCI device to allow access to the internal registers */
 200         pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, AR71XX_PCI_MEM_BASE);
 201         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 202         cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
 203         pci_write_config_word(dev, PCI_COMMAND, cmd);
 204
 205         /* set pointer to first reg address */
 206         cal_data += 3;
 207         while (*cal_data != 0xffff) {
 208                 u32 reg;
 209                 reg = *cal_data++;
 210                 val = *cal_data++;
 211                 val |= (*cal_data++) << 16;
 212
 213                 __raw_writel(val, mem + reg);
 214                 udelay(100);
 215         }
 216
 217         pci_read_config_dword(dev, PCI_VENDOR_ID, &val);
 218         dev->vendor = val & 0xffff;
 219         dev->device = (val >> 16) & 0xffff;
 220
 221         pci_read_config_dword(dev, PCI_CLASS_REVISION, &val);
 222         dev->revision = val & 0xff;
 223         dev->class = val >> 8; /* upper 3 bytes */
 224
 225         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 226         cmd &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
 227         pci_write_config_word(dev, PCI_COMMAND, cmd);
 228
 229         pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, bar0);
 230
 231         iounmap(mem);
 232 }
 233 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATHEROS, PCI_ANY_ID,
 234                         dir825b1_pci_fixup);
 235
 236 static void __init dir825b1_pci_init(void)
 237 {
 238         memcpy(dir825b1_wmac0_data.eeprom_data,
 239                (u8 *) KSEG1ADDR(DIR825B1_CAL_LOCATION_0),
 240                sizeof(dir825b1_wmac0_data.eeprom_data));
 241
 242         memcpy(dir825b1_wmac1_data.eeprom_data,
 243                (u8 *) KSEG1ADDR(DIR825B1_CAL_LOCATION_1),
 244                sizeof(dir825b1_wmac1_data.eeprom_data));
 245
 246         memcpy(dir825b1_wmac0_mac, (u8 *)KSEG1ADDR(DIR825B1_MAC_LOCATION_0), 6);
 247         dir825b1_wmac0_data.macaddr = dir825b1_wmac0_mac;
 248         memcpy(dir825b1_wmac1_mac, (u8 *)KSEG1ADDR(DIR825B1_MAC_LOCATION_1), 6);
 249         dir825b1_wmac1_data.macaddr = dir825b1_wmac1_mac;
 250
 251         ar71xx_pci_plat_dev_init = dir825b1_pci_plat_dev_init;
 252         ar71xx_pci_init(ARRAY_SIZE(dir825b1_pci_irqs), dir825b1_pci_irqs);
 253 }
 254 #else
 255 static void __init dir825b1_pci_init(void) { }
 256 #endif /* CONFIG_PCI */
 257
 258 static void __init dir825b1_setup(void)
 259 {
 260         u8 mac[6], i;
 261
 262         memcpy(mac, (u8*)KSEG1ADDR(DIR825B1_MAC_LOCATION_1), 6);
 263         for(i = 5; i >= 3; i--)
 264                 if(++mac[i] != 0x00) break;
 265
 266         ar71xx_set_mac_base(mac);
 267
 268         ar71xx_add_device_mdio(0x0);
 269
 270         ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
 271         ar71xx_eth0_data.phy_mask = 0x1e;
 272         ar71xx_eth0_data.speed = SPEED_1000;
 273         ar71xx_eth0_data.duplex = DUPLEX_FULL;
 274         ar71xx_eth0_pll_data.pll_1000 = 0x11110000;
 275
 276         ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
 277         ar71xx_eth1_data.phy_mask = 0xc0;
 278         ar71xx_eth1_data.speed = SPEED_1000;
 279         ar71xx_eth1_data.duplex = DUPLEX_FULL;
 280         ar71xx_eth1_pll_data.pll_1000 = 0x11110000;
 281
 282         ar71xx_add_device_eth(0);
 283         ar71xx_add_device_eth(1);
 284
 285         ar71xx_add_device_spi(NULL, dir825b1_spi_info,
 286                               ARRAY_SIZE(dir825b1_spi_info));
 287
 288         ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(dir825b1_leds_gpio),
 289                                         dir825b1_leds_gpio);
 290
 291         ar71xx_add_device_gpio_buttons(-1, DIR825B1_BUTTONS_POLL_INTERVAL,
 292                                         ARRAY_SIZE(dir825b1_gpio_buttons),
 293                                         dir825b1_gpio_buttons);
 294
 295         ar71xx_add_device_usb();
 296
 297         dir825b1_pci_init();
 298 }
 299
 300 MIPS_MACHINE(AR71XX_MACH_DIR_825_B1, "D-Link DIR-825 rev. B1", dir825b1_setup);