target/linux/ar71xx/files/arch/mips/ar71xx/mach-dir-825-b1.c

   1 /*
   2  *  D-Link DIR-825 rev. B1 board support
   3  *
   4  *  Copyright (C) 2009 Lukas Kuna, Evkanet, s.r.o.
   5  *
   6  *  based on mach-wndr3700.c
   7  *
   8  *  This program is free software; you can redistribute it and/or modify it
   9  *  under the terms of the GNU General Public License version 2 as published
  10  *  by the Free Software Foundation.
  11  */
  12
  13 #include <linux/platform_device.h>
  14 #include <linux/mtd/mtd.h>
  15 #include <linux/mtd/partitions.h>
  16 #include <linux/input.h>
  17 #include <linux/pci.h>
  18 #include <linux/ath9k_platform.h>
  19 #include <linux/delay.h>
  20 #include <linux/rtl8366_smi.h>
  21
  22 #include <asm/mips_machine.h>
  23 #include <asm/mach-ar71xx/ar71xx.h>
  24 #include <asm/mach-ar71xx/pci.h>
  25
  26 #include "devices.h"
  27 #include "dev-m25p80.h"
  28
  29 #define DIR825B1_GPIO_LED_BLUE_USB              0
  30 #define DIR825B1_GPIO_LED_ORANGE_POWER          1
  31 #define DIR825B1_GPIO_LED_BLUE_POWER            2
  32 #define DIR825B1_GPIO_LED_BLUE_POWERSAVE        4
  33 #define DIR825B1_GPIO_LED_ORANGE_PLANET         6
  34 #define DIR825B1_GPIO_LED_BLUE_PLANET           11
  35
  36 #define DIR825B1_GPIO_BTN_RESET                 3
  37 #define DIR825B1_GPIO_BTN_POWERSAVE             8
  38
  39 #define DIR825B1_GPIO_RTL8366_SDA               5
  40 #define DIR825B1_GPIO_RTL8366_SCK               7
  41
  42 #define DIR825B1_BUTTONS_POLL_INTERVAL          20
  43
  44 #define DIR825B1_CAL_LOCATION_0                 0x1f661000
  45 #define DIR825B1_CAL_LOCATION_1                 0x1f665000
  46
  47 #define DIR825B1_MAC_LOCATION_0                 0x2ffa81b8
  48 #define DIR825B1_MAC_LOCATION_1                 0x2ffa8370
  49
  50 static struct ath9k_platform_data dir825b1_wmac0_data;
  51 static struct ath9k_platform_data dir825b1_wmac1_data;
  52 static char dir825b1_wmac0_mac[6];
  53 static char dir825b1_wmac1_mac[6];
  54
  55 #ifdef CONFIG_MTD_PARTITIONS
  56 static struct mtd_partition dir825b1_partitions[] = {
  57         {
  58                 .name           = "uboot",
  59                 .offset         = 0,
  60                 .size           = 0x040000,
  61                 .mask_flags     = MTD_WRITEABLE,
  62         } , {
  63                 .name           = "config",
  64                 .offset         = 0x040000,
  65                 .size           = 0x010000,
  66                 .mask_flags     = MTD_WRITEABLE,
  67         } , {
  68                 .name           = "firmware",
  69                 .offset         = 0x050000,
  70                 .size           = 0x610000,
  71         } , {
  72                 .name           = "caldata",
  73                 .offset         = 0x660000,
  74                 .size           = 0x010000,
  75                 .mask_flags     = MTD_WRITEABLE,
  76         }
  77 };
  78 #endif /* CONFIG_MTD_PARTITIONS */
  79
  80 static struct flash_platform_data dir825b1_flash_data = {
  81 #ifdef CONFIG_MTD_PARTITIONS
  82         .parts          = dir825b1_partitions,
  83         .nr_parts       = ARRAY_SIZE(dir825b1_partitions),
  84 #endif
  85 };
  86
  87 static struct gpio_led dir825b1_leds_gpio[] __initdata = {
  88         {
  89                 .name           = "dir825b1:blue:usb",
  90                 .gpio           = DIR825B1_GPIO_LED_BLUE_USB,
  91                 .active_low     = 1,
  92         }, {
  93                 .name           = "dir825b1:orange:power",
  94                 .gpio           = DIR825B1_GPIO_LED_ORANGE_POWER,
  95                 .active_low     = 1,
  96         }, {
  97                 .name           = "dir825b1:blue:power",
  98                 .gpio           = DIR825B1_GPIO_LED_BLUE_POWER,
  99                 .active_low     = 1,
 100         }, {
 101                 .name           = "dir825b1:blue:powersave",
 102                 .gpio           = DIR825B1_GPIO_LED_BLUE_POWERSAVE,
 103                 .active_low     = 1,
 104         }, {
 105                 .name           = "dir825b1:orange:planet",
 106                 .gpio           = DIR825B1_GPIO_LED_ORANGE_PLANET,
 107                 .active_low     = 1,
 108         }, {
 109                 .name           = "dir825b1:blue:planet",
 110                 .gpio           = DIR825B1_GPIO_LED_BLUE_PLANET,
 111                 .active_low     = 1,
 112         }
 113 };
 114
 115 static struct gpio_button dir825b1_gpio_buttons[] __initdata = {
 116         {
 117                 .desc           = "reset",
 118                 .type           = EV_KEY,
 119                 .code           = BTN_0,
 120                 .threshold      = 5,
 121                 .gpio           = DIR825B1_GPIO_BTN_RESET,
 122                 .active_low     = 1,
 123         } , {
 124                 .desc           = "powersave",
 125                 .type           = EV_KEY,
 126                 .code           = BTN_1,
 127                 .threshold      = 5,
 128                 .gpio           = DIR825B1_GPIO_BTN_POWERSAVE,
 129                 .active_low     = 1,
 130         }
 131 };
 132
 133 static struct rtl8366_smi_platform_data dir825b1_rtl8366_smi_data = {
 134         .gpio_sda        = DIR825B1_GPIO_RTL8366_SDA,
 135         .gpio_sck        = DIR825B1_GPIO_RTL8366_SCK,
 136 };
 137
 138 static struct platform_device dir825b1_rtl8366_smi_device = {
 139         .name           = "rtl8366-smi",
 140         .id             = -1,
 141         .dev = {
 142                 .platform_data  = &dir825b1_rtl8366_smi_data,
 143         }
 144 };
 145
 146 #ifdef CONFIG_PCI
 147 static struct ar71xx_pci_irq dir825b1_pci_irqs[] __initdata = {
 148         {
 149                 .slot   = 0,
 150                 .pin    = 1,
 151                 .irq    = AR71XX_PCI_IRQ_DEV0,
 152         }, {
 153                 .slot   = 1,
 154                 .pin    = 1,
 155                 .irq    = AR71XX_PCI_IRQ_DEV1,
 156         }
 157 };
 158
 159 static int dir825b1_pci_plat_dev_init(struct pci_dev *dev)
 160 {
 161         switch(PCI_SLOT(dev->devfn)) {
 162         case 17:
 163                 dev->dev.platform_data = &dir825b1_wmac0_data;
 164                 break;
 165
 166         case 18:
 167                 dev->dev.platform_data = &dir825b1_wmac1_data;
 168                 break;
 169         }
 170
 171         return 0;
 172 }
 173
 174 static void dir825b1_pci_fixup(struct pci_dev *dev)
 175 {
 176         void __iomem *mem;
 177         u16 *cal_data;
 178         u16 cmd;
 179         u32 bar0;
 180         u32 val;
 181
 182         if (ar71xx_mach != AR71XX_MACH_DIR_825_B1)
 183                 return;
 184
 185         dir825b1_pci_plat_dev_init(dev);
 186         cal_data = dev->dev.platform_data;
 187
 188         if (*cal_data != 0xa55a) {
 189                 printk(KERN_ERR "PCI: no calibration data found for %s\n",
 190                        pci_name(dev));
 191                 return;
 192         }
 193
 194         mem = ioremap(AR71XX_PCI_MEM_BASE, 0x10000);
 195         if (!mem) {
 196                 printk(KERN_ERR "PCI: ioremap error for device %s\n",
 197                        pci_name(dev));
 198                 return;
 199         }
 200
 201         printk(KERN_INFO "PCI: fixup device %s\n", pci_name(dev));
 202
 203         pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar0);
 204
 205         /* Setup the PCI device to allow access to the internal registers */
 206         pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, AR71XX_PCI_MEM_BASE);
 207         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 208         cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
 209         pci_write_config_word(dev, PCI_COMMAND, cmd);
 210
 211         /* set pointer to first reg address */
 212         cal_data += 3;
 213         while (*cal_data != 0xffff) {
 214                 u32 reg;
 215                 reg = *cal_data++;
 216                 val = *cal_data++;
 217                 val |= (*cal_data++) << 16;
 218
 219                 __raw_writel(val, mem + reg);
 220                 udelay(100);
 221         }
 222
 223         pci_read_config_dword(dev, PCI_VENDOR_ID, &val);
 224         dev->vendor = val & 0xffff;
 225         dev->device = (val >> 16) & 0xffff;
 226
 227         pci_read_config_dword(dev, PCI_CLASS_REVISION, &val);
 228         dev->revision = val & 0xff;
 229         dev->class = val >> 8; /* upper 3 bytes */
 230
 231         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 232         cmd &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
 233         pci_write_config_word(dev, PCI_COMMAND, cmd);
 234
 235         pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, bar0);
 236
 237         iounmap(mem);
 238 }
 239 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATHEROS, PCI_ANY_ID,
 240                         dir825b1_pci_fixup);
 241
 242 static void __init dir825b1_pci_init(void)
 243 {
 244         memcpy(dir825b1_wmac0_data.eeprom_data,
 245                (u8 *) KSEG1ADDR(DIR825B1_CAL_LOCATION_0),
 246                sizeof(dir825b1_wmac0_data.eeprom_data));
 247
 248         memcpy(dir825b1_wmac1_data.eeprom_data,
 249                (u8 *) KSEG1ADDR(DIR825B1_CAL_LOCATION_1),
 250                sizeof(dir825b1_wmac1_data.eeprom_data));
 251
 252         memcpy(dir825b1_wmac0_mac, (u8 *)KSEG1ADDR(DIR825B1_MAC_LOCATION_0), 6);
 253         dir825b1_wmac0_data.macaddr = dir825b1_wmac0_mac;
 254         memcpy(dir825b1_wmac1_mac, (u8 *)KSEG1ADDR(DIR825B1_MAC_LOCATION_1), 6);
 255         dir825b1_wmac1_data.macaddr = dir825b1_wmac1_mac;
 256
 257         ar71xx_pci_plat_dev_init = dir825b1_pci_plat_dev_init;
 258         ar71xx_pci_init(ARRAY_SIZE(dir825b1_pci_irqs), dir825b1_pci_irqs);
 259 }
 260 #else
 261 static void __init dir825b1_pci_init(void) { }
 262 #endif /* CONFIG_PCI */
 263
 264 static void __init dir825b1_setup(void)
 265 {
 266         u8 mac[6], i;
 267
 268         memcpy(mac, (u8*)KSEG1ADDR(DIR825B1_MAC_LOCATION_1), 6);
 269         for(i = 5; i >= 3; i--)
 270                 if(++mac[i] != 0x00) break;
 271
 272         ar71xx_set_mac_base(mac);
 273
 274         ar71xx_add_device_mdio(0x0);
 275
 276         ar71xx_eth0_data.mii_bus_dev = &dir825b1_rtl8366_smi_device.dev;
 277         ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
 278         ar71xx_eth0_data.speed = SPEED_1000;
 279         ar71xx_eth0_data.duplex = DUPLEX_FULL;
 280         ar71xx_eth0_pll_data.pll_1000 = 0x11110000;
 281
 282         ar71xx_eth1_data.mii_bus_dev = &dir825b1_rtl8366_smi_device.dev;
 283         ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
 284         ar71xx_eth1_data.phy_mask = 0x10;
 285         ar71xx_eth1_pll_data.pll_1000 = 0x11110000;
 286
 287         ar71xx_add_device_eth(0);
 288         ar71xx_add_device_eth(1);
 289
 290         ar71xx_add_device_m25p80(&dir825b1_flash_data);
 291
 292         ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(dir825b1_leds_gpio),
 293                                         dir825b1_leds_gpio);
 294
 295         ar71xx_add_device_gpio_buttons(-1, DIR825B1_BUTTONS_POLL_INTERVAL,
 296                                         ARRAY_SIZE(dir825b1_gpio_buttons),
 297                                         dir825b1_gpio_buttons);
 298
 299         ar71xx_add_device_usb();
 300
 301         platform_device_register(&dir825b1_rtl8366_smi_device);
 302         dir825b1_pci_init();
 303 }
 304
 305 MIPS_MACHINE(AR71XX_MACH_DIR_825_B1, "D-Link DIR-825 rev. B1", dir825b1_setup);