2 * Atheros AR71xx SoC specific interrupt handling
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 * Parts of this file are based on Atheros' 2.6.15 BSP
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
17 #include <linux/irq.h>
19 #include <asm/irq_cpu.h>
20 #include <asm/mipsregs.h>
22 #include <asm/mach-ar71xx/ar71xx.h>
24 static void ar71xx_gpio_irq_dispatch(void)
26 void __iomem *base = ar71xx_gpio_base;
29 pending = __raw_readl(base + GPIO_REG_INT_PENDING) &
30 __raw_readl(base + GPIO_REG_INT_ENABLE);
33 do_IRQ(AR71XX_GPIO_IRQ_BASE + fls(pending) - 1);
38 static void ar71xx_gpio_irq_unmask(unsigned int irq)
40 void __iomem *base = ar71xx_gpio_base;
43 irq -= AR71XX_GPIO_IRQ_BASE;
45 t = __raw_readl(base + GPIO_REG_INT_ENABLE);
46 __raw_writel(t | (1 << irq), base + GPIO_REG_INT_ENABLE);
49 (void) __raw_readl(base + GPIO_REG_INT_ENABLE);
52 static void ar71xx_gpio_irq_mask(unsigned int irq)
54 void __iomem *base = ar71xx_gpio_base;
57 irq -= AR71XX_GPIO_IRQ_BASE;
59 t = __raw_readl(base + GPIO_REG_INT_ENABLE);
60 __raw_writel(t & ~(1 << irq), base + GPIO_REG_INT_ENABLE);
63 (void) __raw_readl(base + GPIO_REG_INT_ENABLE);
67 static int ar71xx_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
73 #define ar71xx_gpio_irq_set_type NULL
76 static struct irq_chip ar71xx_gpio_irq_chip = {
77 .name = "AR71XX GPIO",
78 .unmask = ar71xx_gpio_irq_unmask,
79 .mask = ar71xx_gpio_irq_mask,
80 .mask_ack = ar71xx_gpio_irq_mask,
81 .set_type = ar71xx_gpio_irq_set_type,
84 static struct irqaction ar71xx_gpio_irqaction = {
86 .name = "cascade [AR71XX GPIO]",
89 #define GPIO_IRQ_INIT_STATUS (IRQ_LEVEL | IRQ_TYPE_LEVEL_HIGH | IRQ_DISABLED)
90 #define GPIO_INT_ALL 0xffff
92 static void __init ar71xx_gpio_irq_init(void)
94 void __iomem *base = ar71xx_gpio_base;
97 __raw_writel(0, base + GPIO_REG_INT_ENABLE);
98 __raw_writel(0, base + GPIO_REG_INT_PENDING);
100 /* setup type of all GPIO interrupts to level sensitive */
101 __raw_writel(GPIO_INT_ALL, base + GPIO_REG_INT_TYPE);
103 /* setup polarity of all GPIO interrupts to active high */
104 __raw_writel(GPIO_INT_ALL, base + GPIO_REG_INT_POLARITY);
106 for (i = AR71XX_GPIO_IRQ_BASE;
107 i < AR71XX_GPIO_IRQ_BASE + AR71XX_GPIO_IRQ_COUNT; i++) {
108 irq_desc[i].status = GPIO_IRQ_INIT_STATUS;
109 set_irq_chip_and_handler(i, &ar71xx_gpio_irq_chip,
113 setup_irq(AR71XX_MISC_IRQ_GPIO, &ar71xx_gpio_irqaction);
116 static void ar71xx_misc_irq_dispatch(void)
120 pending = ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS)
121 & ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
123 if (pending & MISC_INT_UART)
124 do_IRQ(AR71XX_MISC_IRQ_UART);
126 else if (pending & MISC_INT_DMA)
127 do_IRQ(AR71XX_MISC_IRQ_DMA);
129 else if (pending & MISC_INT_PERFC)
130 do_IRQ(AR71XX_MISC_IRQ_PERFC);
132 else if (pending & MISC_INT_TIMER)
133 do_IRQ(AR71XX_MISC_IRQ_TIMER);
135 else if (pending & MISC_INT_OHCI)
136 do_IRQ(AR71XX_MISC_IRQ_OHCI);
138 else if (pending & MISC_INT_ERROR)
139 do_IRQ(AR71XX_MISC_IRQ_ERROR);
141 else if (pending & MISC_INT_GPIO)
142 ar71xx_gpio_irq_dispatch();
144 else if (pending & MISC_INT_WDOG)
145 do_IRQ(AR71XX_MISC_IRQ_WDOG);
148 spurious_interrupt();
151 static void ar71xx_misc_irq_unmask(unsigned int irq)
153 void __iomem *base = ar71xx_reset_base;
156 irq -= AR71XX_MISC_IRQ_BASE;
158 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
159 __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
162 (void) __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
165 static void ar71xx_misc_irq_mask(unsigned int irq)
167 void __iomem *base = ar71xx_reset_base;
170 irq -= AR71XX_MISC_IRQ_BASE;
172 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
173 __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
176 (void) __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
179 static void ar724x_misc_irq_ack(unsigned int irq)
181 void __iomem *base = ar71xx_reset_base;
184 irq -= AR71XX_MISC_IRQ_BASE;
186 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
187 __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_STATUS);
190 (void) __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
193 static struct irq_chip ar71xx_misc_irq_chip = {
194 .name = "AR71XX MISC",
195 .unmask = ar71xx_misc_irq_unmask,
196 .mask = ar71xx_misc_irq_mask,
199 static struct irqaction ar71xx_misc_irqaction = {
200 .handler = no_action,
201 .name = "cascade [AR71XX MISC]",
204 static void __init ar71xx_misc_irq_init(void)
206 void __iomem *base = ar71xx_reset_base;
209 __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE);
210 __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS);
212 switch (ar71xx_soc) {
213 case AR71XX_SOC_AR7240:
214 case AR71XX_SOC_AR7241:
215 case AR71XX_SOC_AR7242:
216 ar71xx_misc_irq_chip.ack = ar724x_misc_irq_ack;
219 ar71xx_misc_irq_chip.mask_ack = ar71xx_misc_irq_mask;
223 for (i = AR71XX_MISC_IRQ_BASE;
224 i < AR71XX_MISC_IRQ_BASE + AR71XX_MISC_IRQ_COUNT; i++) {
225 irq_desc[i].status = IRQ_DISABLED;
226 set_irq_chip_and_handler(i, &ar71xx_misc_irq_chip,
230 setup_irq(AR71XX_CPU_IRQ_MISC, &ar71xx_misc_irqaction);
233 asmlinkage void plat_irq_dispatch(void)
235 unsigned long pending;
237 pending = read_c0_status() & read_c0_cause() & ST0_IM;
239 if (pending & STATUSF_IP7)
240 do_IRQ(AR71XX_CPU_IRQ_TIMER);
242 else if (pending & STATUSF_IP2)
243 do_IRQ(AR71XX_CPU_IRQ_IP2);
245 else if (pending & STATUSF_IP4)
246 do_IRQ(AR71XX_CPU_IRQ_GE0);
248 else if (pending & STATUSF_IP5)
249 do_IRQ(AR71XX_CPU_IRQ_GE1);
251 else if (pending & STATUSF_IP3)
252 do_IRQ(AR71XX_CPU_IRQ_USB);
254 else if (pending & STATUSF_IP6)
255 ar71xx_misc_irq_dispatch();
258 spurious_interrupt();
261 void __init arch_init_irq(void)
265 ar71xx_misc_irq_init();
267 cp0_perfcount_irq = AR71XX_MISC_IRQ_PERFC;
269 ar71xx_gpio_irq_init();