2 * Atheros AR71xx SoC specific interrupt handling
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
8 * Parts of this file are based on Atheros 2.6.15 BSP
9 * Parts of this file are based on Atheros 2.6.31 BSP
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/interrupt.h>
19 #include <linux/irq.h>
21 #include <asm/irq_cpu.h>
22 #include <asm/mipsregs.h>
24 #include <asm/mach-ar71xx/ar71xx.h>
26 static int ip2_flush_reg;
28 static void ar71xx_gpio_irq_dispatch(void)
30 void __iomem *base = ar71xx_gpio_base;
33 pending = __raw_readl(base + GPIO_REG_INT_PENDING) &
34 __raw_readl(base + GPIO_REG_INT_ENABLE);
37 do_IRQ(AR71XX_GPIO_IRQ_BASE + fls(pending) - 1);
42 static void ar71xx_gpio_irq_unmask(unsigned int irq)
44 void __iomem *base = ar71xx_gpio_base;
47 irq -= AR71XX_GPIO_IRQ_BASE;
49 t = __raw_readl(base + GPIO_REG_INT_ENABLE);
50 __raw_writel(t | (1 << irq), base + GPIO_REG_INT_ENABLE);
53 (void) __raw_readl(base + GPIO_REG_INT_ENABLE);
56 static void ar71xx_gpio_irq_mask(unsigned int irq)
58 void __iomem *base = ar71xx_gpio_base;
61 irq -= AR71XX_GPIO_IRQ_BASE;
63 t = __raw_readl(base + GPIO_REG_INT_ENABLE);
64 __raw_writel(t & ~(1 << irq), base + GPIO_REG_INT_ENABLE);
67 (void) __raw_readl(base + GPIO_REG_INT_ENABLE);
71 static int ar71xx_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
77 #define ar71xx_gpio_irq_set_type NULL
80 static struct irq_chip ar71xx_gpio_irq_chip = {
81 .name = "AR71XX GPIO",
82 .unmask = ar71xx_gpio_irq_unmask,
83 .mask = ar71xx_gpio_irq_mask,
84 .mask_ack = ar71xx_gpio_irq_mask,
85 .set_type = ar71xx_gpio_irq_set_type,
88 static struct irqaction ar71xx_gpio_irqaction = {
90 .name = "cascade [AR71XX GPIO]",
93 #define GPIO_INT_ALL 0xffff
95 static void __init ar71xx_gpio_irq_init(void)
97 void __iomem *base = ar71xx_gpio_base;
100 __raw_writel(0, base + GPIO_REG_INT_ENABLE);
101 __raw_writel(0, base + GPIO_REG_INT_PENDING);
103 /* setup type of all GPIO interrupts to level sensitive */
104 __raw_writel(GPIO_INT_ALL, base + GPIO_REG_INT_TYPE);
106 /* setup polarity of all GPIO interrupts to active high */
107 __raw_writel(GPIO_INT_ALL, base + GPIO_REG_INT_POLARITY);
109 for (i = AR71XX_GPIO_IRQ_BASE;
110 i < AR71XX_GPIO_IRQ_BASE + AR71XX_GPIO_IRQ_COUNT; i++)
111 set_irq_chip_and_handler(i, &ar71xx_gpio_irq_chip,
114 setup_irq(AR71XX_MISC_IRQ_GPIO, &ar71xx_gpio_irqaction);
117 static void ar71xx_misc_irq_dispatch(void)
121 pending = ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS)
122 & ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
124 if (pending & MISC_INT_UART)
125 do_IRQ(AR71XX_MISC_IRQ_UART);
127 else if (pending & MISC_INT_DMA)
128 do_IRQ(AR71XX_MISC_IRQ_DMA);
130 else if (pending & MISC_INT_PERFC)
131 do_IRQ(AR71XX_MISC_IRQ_PERFC);
133 else if (pending & MISC_INT_TIMER)
134 do_IRQ(AR71XX_MISC_IRQ_TIMER);
136 else if (pending & MISC_INT_OHCI)
137 do_IRQ(AR71XX_MISC_IRQ_OHCI);
139 else if (pending & MISC_INT_ERROR)
140 do_IRQ(AR71XX_MISC_IRQ_ERROR);
142 else if (pending & MISC_INT_GPIO)
143 ar71xx_gpio_irq_dispatch();
145 else if (pending & MISC_INT_WDOG)
146 do_IRQ(AR71XX_MISC_IRQ_WDOG);
148 else if (pending & MISC_INT_TIMER2)
149 do_IRQ(AR71XX_MISC_IRQ_TIMER2);
151 else if (pending & MISC_INT_TIMER3)
152 do_IRQ(AR71XX_MISC_IRQ_TIMER3);
154 else if (pending & MISC_INT_TIMER4)
155 do_IRQ(AR71XX_MISC_IRQ_TIMER4);
157 else if (pending & MISC_INT_DDR_PERF)
158 do_IRQ(AR71XX_MISC_IRQ_DDR_PERF);
160 else if (pending & MISC_INT_ENET_LINK)
161 do_IRQ(AR71XX_MISC_IRQ_ENET_LINK);
164 spurious_interrupt();
167 static void ar71xx_misc_irq_unmask(unsigned int irq)
169 void __iomem *base = ar71xx_reset_base;
172 irq -= AR71XX_MISC_IRQ_BASE;
174 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
175 __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
178 (void) __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
181 static void ar71xx_misc_irq_mask(unsigned int irq)
183 void __iomem *base = ar71xx_reset_base;
186 irq -= AR71XX_MISC_IRQ_BASE;
188 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
189 __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
192 (void) __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
195 static void ar724x_misc_irq_ack(unsigned int irq)
197 void __iomem *base = ar71xx_reset_base;
200 irq -= AR71XX_MISC_IRQ_BASE;
202 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
203 __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_STATUS);
206 (void) __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
209 static struct irq_chip ar71xx_misc_irq_chip = {
210 .name = "AR71XX MISC",
211 .unmask = ar71xx_misc_irq_unmask,
212 .mask = ar71xx_misc_irq_mask,
215 static struct irqaction ar71xx_misc_irqaction = {
216 .handler = no_action,
217 .name = "cascade [AR71XX MISC]",
220 static void __init ar71xx_misc_irq_init(void)
222 void __iomem *base = ar71xx_reset_base;
225 __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE);
226 __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS);
228 switch (ar71xx_soc) {
229 case AR71XX_SOC_AR7240:
230 case AR71XX_SOC_AR7241:
231 case AR71XX_SOC_AR7242:
232 case AR71XX_SOC_AR9330:
233 case AR71XX_SOC_AR9331:
234 case AR71XX_SOC_AR9341:
235 case AR71XX_SOC_AR9342:
236 case AR71XX_SOC_AR9344:
237 ar71xx_misc_irq_chip.ack = ar724x_misc_irq_ack;
240 ar71xx_misc_irq_chip.mask_ack = ar71xx_misc_irq_mask;
244 for (i = AR71XX_MISC_IRQ_BASE;
245 i < AR71XX_MISC_IRQ_BASE + AR71XX_MISC_IRQ_COUNT; i++)
246 set_irq_chip_and_handler(i, &ar71xx_misc_irq_chip,
249 setup_irq(AR71XX_CPU_IRQ_MISC, &ar71xx_misc_irqaction);
252 asmlinkage void plat_irq_dispatch(void)
254 unsigned long pending;
256 pending = read_c0_status() & read_c0_cause() & ST0_IM;
258 if (pending & STATUSF_IP7)
259 do_IRQ(AR71XX_CPU_IRQ_TIMER);
261 else if (pending & STATUSF_IP2) {
263 * This IRQ is meant for a PCI device. Drivers for PCI devices
264 * typically allocate coherent DMA memory for the descriptor
265 * ring, however the DMA controller may still have some
266 * unsynchronized data in the FIFO.
267 * Issue a flush here to ensure that the driver sees the update.
269 ar71xx_ddr_flush(ip2_flush_reg);
270 do_IRQ(AR71XX_CPU_IRQ_IP2);
273 else if (pending & STATUSF_IP4)
274 do_IRQ(AR71XX_CPU_IRQ_GE0);
276 else if (pending & STATUSF_IP5)
277 do_IRQ(AR71XX_CPU_IRQ_GE1);
279 else if (pending & STATUSF_IP3)
280 do_IRQ(AR71XX_CPU_IRQ_USB);
282 else if (pending & STATUSF_IP6)
283 ar71xx_misc_irq_dispatch();
286 spurious_interrupt();
289 void __init arch_init_irq(void)
291 switch (ar71xx_soc) {
292 case AR71XX_SOC_AR7130:
293 case AR71XX_SOC_AR7141:
294 case AR71XX_SOC_AR7161:
295 ip2_flush_reg = AR71XX_DDR_REG_FLUSH_PCI;
298 case AR71XX_SOC_AR7240:
299 case AR71XX_SOC_AR7241:
300 case AR71XX_SOC_AR7242:
301 ip2_flush_reg = AR724X_DDR_REG_FLUSH_PCIE;
304 case AR71XX_SOC_AR9130:
305 case AR71XX_SOC_AR9132:
306 ip2_flush_reg = AR91XX_DDR_REG_FLUSH_WMAC;
309 case AR71XX_SOC_AR9330:
310 case AR71XX_SOC_AR9331:
311 ip2_flush_reg = AR933X_DDR_REG_FLUSH_WMAC;
314 case AR71XX_SOC_AR9341:
315 case AR71XX_SOC_AR9342:
316 case AR71XX_SOC_AR9344:
317 ip2_flush_reg = AR934X_DDR_REG_FLUSH_PCIE;
326 ar71xx_misc_irq_init();
328 cp0_perfcount_irq = AR71XX_MISC_IRQ_PERFC;
330 ar71xx_gpio_irq_init();