2 * Atheros AR71xx SoC specific interrupt handling
4 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 * Parts of this file are based on Atheros' 2.6.15 BSP
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
17 #include <linux/irq.h>
19 #include <asm/irq_cpu.h>
20 #include <asm/mipsregs.h>
22 #include <asm/mach-ar71xx/ar71xx.h>
24 static void (* ar71xx_ip2_irq_handler)(void) = spurious_interrupt;
27 static void ar71xx_pci_irq_dispatch(void)
31 pending = ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_STATUS) &
32 ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE);
34 if (pending & PCI_INT_DEV0)
35 do_IRQ(AR71XX_PCI_IRQ_DEV0);
37 else if (pending & PCI_INT_DEV1)
38 do_IRQ(AR71XX_PCI_IRQ_DEV1);
40 else if (pending & PCI_INT_DEV2)
41 do_IRQ(AR71XX_PCI_IRQ_DEV2);
43 else if (pending & PCI_INT_CORE)
44 do_IRQ(AR71XX_PCI_IRQ_CORE);
50 static void ar71xx_pci_irq_unmask(unsigned int irq)
52 irq -= AR71XX_PCI_IRQ_BASE;
53 ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE,
54 ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE) | (1 << irq));
57 ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE);
60 static void ar71xx_pci_irq_mask(unsigned int irq)
62 irq -= AR71XX_PCI_IRQ_BASE;
63 ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE,
64 ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE) & ~(1 << irq));
67 ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE);
70 static struct irq_chip ar71xx_pci_irq_chip = {
71 .name = "AR71XX PCI ",
72 .mask = ar71xx_pci_irq_mask,
73 .unmask = ar71xx_pci_irq_unmask,
74 .mask_ack = ar71xx_pci_irq_mask,
77 static struct irqaction ar71xx_pci_irqaction = {
79 .name = "cascade [AR71XX PCI]",
82 static void __init ar71xx_pci_irq_init(void)
86 ar71xx_ip2_irq_handler = ar71xx_pci_irq_dispatch;
88 ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE, 0);
89 ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_STATUS, 0);
91 for (i = AR71XX_PCI_IRQ_BASE;
92 i < AR71XX_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) {
93 irq_desc[i].status = IRQ_DISABLED;
94 set_irq_chip_and_handler(i, &ar71xx_pci_irq_chip,
98 setup_irq(AR71XX_CPU_IRQ_PCI, &ar71xx_pci_irqaction);
101 static void ar724x_pci_irq_dispatch(void)
105 pending = ar724x_pci_rr(AR724X_PCI_REG_INT_STATUS) &
106 ar724x_pci_rr(AR724X_PCI_REG_INT_MASK);
108 if (pending & AR724X_PCI_INT_DEV0)
109 do_IRQ(AR71XX_PCI_IRQ_DEV0);
112 spurious_interrupt();
115 static void ar724x_pci_irq_unmask(unsigned int irq)
118 case AR71XX_PCI_IRQ_DEV0:
119 irq -= AR71XX_PCI_IRQ_BASE;
120 ar724x_pci_wr(AR724X_PCI_REG_INT_MASK,
121 ar724x_pci_rr(AR724X_PCI_REG_INT_MASK) |
122 AR724X_PCI_INT_DEV0);
124 ar724x_pci_rr(AR724X_PCI_REG_INT_MASK);
128 static void ar724x_pci_irq_mask(unsigned int irq)
131 case AR71XX_PCI_IRQ_DEV0:
132 irq -= AR71XX_PCI_IRQ_BASE;
133 ar724x_pci_wr(AR724X_PCI_REG_INT_MASK,
134 ar724x_pci_rr(AR724X_PCI_REG_INT_MASK) &
135 ~AR724X_PCI_INT_DEV0);
137 ar724x_pci_rr(AR724X_PCI_REG_INT_MASK);
139 ar724x_pci_wr(AR724X_PCI_REG_INT_STATUS,
140 ar724x_pci_rr(AR724X_PCI_REG_INT_STATUS) |
141 AR724X_PCI_INT_DEV0);
143 ar724x_pci_rr(AR724X_PCI_REG_INT_STATUS);
147 static struct irq_chip ar724x_pci_irq_chip = {
148 .name = "AR724X PCI ",
149 .mask = ar724x_pci_irq_mask,
150 .unmask = ar724x_pci_irq_unmask,
151 .mask_ack = ar724x_pci_irq_mask,
154 static struct irqaction ar724x_pci_irqaction = {
155 .handler = no_action,
156 .name = "cascade [AR724X PCI]",
159 static void __init ar724x_pci_irq_init(void)
164 t = ar71xx_reset_rr(AR724X_RESET_REG_RESET_MODULE);
165 if (t & (AR724X_RESET_PCIE | AR724X_RESET_PCIE_PHY |
166 AR724X_RESET_PCIE_PHY_SERIAL)) {
170 ar71xx_ip2_irq_handler = ar724x_pci_irq_dispatch;
172 ar724x_pci_wr(AR724X_PCI_REG_INT_MASK, 0);
173 ar724x_pci_wr(AR724X_PCI_REG_INT_STATUS, 0);
175 for (i = AR71XX_PCI_IRQ_BASE;
176 i < AR71XX_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) {
177 irq_desc[i].status = IRQ_DISABLED;
178 set_irq_chip_and_handler(i, &ar724x_pci_irq_chip,
182 setup_irq(AR71XX_CPU_IRQ_PCI, &ar724x_pci_irqaction);
185 static inline void ar71xx_pci_irq_init(void) {};
186 static inline void ar724x_pci_irq_init(void) {};
187 #endif /* CONFIG_PCI */
189 static void ar71xx_gpio_irq_dispatch(void)
193 pending = ar71xx_gpio_rr(GPIO_REG_INT_PENDING)
194 & ar71xx_gpio_rr(GPIO_REG_INT_ENABLE);
197 do_IRQ(AR71XX_GPIO_IRQ_BASE + fls(pending) - 1);
199 spurious_interrupt();
202 static void ar71xx_gpio_irq_unmask(unsigned int irq)
204 irq -= AR71XX_GPIO_IRQ_BASE;
205 ar71xx_gpio_wr(GPIO_REG_INT_ENABLE,
206 ar71xx_gpio_rr(GPIO_REG_INT_ENABLE) | (1 << irq));
209 ar71xx_gpio_rr(GPIO_REG_INT_ENABLE);
212 static void ar71xx_gpio_irq_mask(unsigned int irq)
214 irq -= AR71XX_GPIO_IRQ_BASE;
215 ar71xx_gpio_wr(GPIO_REG_INT_ENABLE,
216 ar71xx_gpio_rr(GPIO_REG_INT_ENABLE) & ~(1 << irq));
219 ar71xx_gpio_rr(GPIO_REG_INT_ENABLE);
223 static int ar71xx_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
225 /* TODO: implement */
229 #define ar71xx_gpio_irq_set_type NULL
232 static struct irq_chip ar71xx_gpio_irq_chip = {
233 .name = "AR71XX GPIO",
234 .unmask = ar71xx_gpio_irq_unmask,
235 .mask = ar71xx_gpio_irq_mask,
236 .mask_ack = ar71xx_gpio_irq_mask,
237 .set_type = ar71xx_gpio_irq_set_type,
240 static struct irqaction ar71xx_gpio_irqaction = {
241 .handler = no_action,
242 .name = "cascade [AR71XX GPIO]",
245 #define GPIO_IRQ_INIT_STATUS (IRQ_LEVEL | IRQ_TYPE_LEVEL_HIGH | IRQ_DISABLED)
246 #define GPIO_INT_ALL 0xffff
248 static void __init ar71xx_gpio_irq_init(void)
252 ar71xx_gpio_wr(GPIO_REG_INT_ENABLE, 0);
253 ar71xx_gpio_wr(GPIO_REG_INT_PENDING, 0);
255 /* setup type of all GPIO interrupts to level sensitive */
256 ar71xx_gpio_wr(GPIO_REG_INT_TYPE, GPIO_INT_ALL);
258 /* setup polarity of all GPIO interrupts to active high */
259 ar71xx_gpio_wr(GPIO_REG_INT_POLARITY, GPIO_INT_ALL);
261 for (i = AR71XX_GPIO_IRQ_BASE;
262 i < AR71XX_GPIO_IRQ_BASE + AR71XX_GPIO_IRQ_COUNT; i++) {
263 irq_desc[i].status = GPIO_IRQ_INIT_STATUS;
264 set_irq_chip_and_handler(i, &ar71xx_gpio_irq_chip,
268 setup_irq(AR71XX_MISC_IRQ_GPIO, &ar71xx_gpio_irqaction);
271 static void ar71xx_misc_irq_dispatch(void)
275 pending = ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS)
276 & ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
278 if (pending & MISC_INT_UART)
279 do_IRQ(AR71XX_MISC_IRQ_UART);
281 else if (pending & MISC_INT_DMA)
282 do_IRQ(AR71XX_MISC_IRQ_DMA);
284 else if (pending & MISC_INT_PERFC)
285 do_IRQ(AR71XX_MISC_IRQ_PERFC);
287 else if (pending & MISC_INT_TIMER)
288 do_IRQ(AR71XX_MISC_IRQ_TIMER);
290 else if (pending & MISC_INT_OHCI)
291 do_IRQ(AR71XX_MISC_IRQ_OHCI);
293 else if (pending & MISC_INT_ERROR)
294 do_IRQ(AR71XX_MISC_IRQ_ERROR);
296 else if (pending & MISC_INT_GPIO)
297 ar71xx_gpio_irq_dispatch();
299 else if (pending & MISC_INT_WDOG)
300 do_IRQ(AR71XX_MISC_IRQ_WDOG);
303 spurious_interrupt();
306 static void ar71xx_misc_irq_unmask(unsigned int irq)
308 irq -= AR71XX_MISC_IRQ_BASE;
309 ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE,
310 ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE) | (1 << irq));
313 ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
316 static void ar71xx_misc_irq_mask(unsigned int irq)
318 irq -= AR71XX_MISC_IRQ_BASE;
319 ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE,
320 ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE) & ~(1 << irq));
323 ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
326 static void ar724x_misc_irq_ack(unsigned int irq)
328 irq -= AR71XX_MISC_IRQ_BASE;
329 ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_STATUS,
330 ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS) & ~(1 << irq));
333 ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS);
336 static struct irq_chip ar71xx_misc_irq_chip = {
337 .name = "AR71XX MISC",
338 .unmask = ar71xx_misc_irq_unmask,
339 .mask = ar71xx_misc_irq_mask,
342 static struct irqaction ar71xx_misc_irqaction = {
343 .handler = no_action,
344 .name = "cascade [AR71XX MISC]",
347 static void __init ar71xx_misc_irq_init(void)
351 ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, 0);
352 ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_STATUS, 0);
354 if (ar71xx_soc == AR71XX_SOC_AR7240)
355 ar71xx_misc_irq_chip.ack = ar724x_misc_irq_ack;
357 ar71xx_misc_irq_chip.mask_ack = ar71xx_misc_irq_mask;
359 for (i = AR71XX_MISC_IRQ_BASE;
360 i < AR71XX_MISC_IRQ_BASE + AR71XX_MISC_IRQ_COUNT; i++) {
361 irq_desc[i].status = IRQ_DISABLED;
362 set_irq_chip_and_handler(i, &ar71xx_misc_irq_chip,
366 setup_irq(AR71XX_CPU_IRQ_MISC, &ar71xx_misc_irqaction);
369 static void ar913x_wmac_irq_dispatch(void)
371 do_IRQ(AR71XX_CPU_IRQ_WMAC);
374 asmlinkage void plat_irq_dispatch(void)
376 unsigned long pending;
378 pending = read_c0_status() & read_c0_cause() & ST0_IM;
380 if (pending & STATUSF_IP7)
381 do_IRQ(AR71XX_CPU_IRQ_TIMER);
383 else if (pending & STATUSF_IP2)
384 ar71xx_ip2_irq_handler();
386 else if (pending & STATUSF_IP4)
387 do_IRQ(AR71XX_CPU_IRQ_GE0);
389 else if (pending & STATUSF_IP5)
390 do_IRQ(AR71XX_CPU_IRQ_GE1);
392 else if (pending & STATUSF_IP3)
393 do_IRQ(AR71XX_CPU_IRQ_USB);
395 else if (pending & STATUSF_IP6)
396 ar71xx_misc_irq_dispatch();
399 spurious_interrupt();
402 void __init arch_init_irq(void)
406 ar71xx_misc_irq_init();
408 switch (ar71xx_soc) {
409 case AR71XX_SOC_AR7130:
410 case AR71XX_SOC_AR7141:
411 case AR71XX_SOC_AR7161:
412 ar71xx_pci_irq_init();
414 case AR71XX_SOC_AR7240:
415 ar724x_pci_irq_init();
417 case AR71XX_SOC_AR9130:
418 case AR71XX_SOC_AR9132:
419 ar71xx_ip2_irq_handler = ar913x_wmac_irq_dispatch;
425 ar71xx_gpio_irq_init();