2 * Atheros AR71xx SoC specific interrupt handling
4 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 * Parts of this file are based on Atheros' 2.6.15 BSP
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
17 #include <linux/irq.h>
19 #include <asm/irq_cpu.h>
20 #include <asm/mipsregs.h>
22 #include <asm/mach-ar71xx/ar71xx.h>
25 static void ar71xx_pci_irq_dispatch(void)
29 pending = ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_STATUS) &
30 ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE);
32 if (pending & PCI_INT_DEV0)
33 do_IRQ(AR71XX_PCI_IRQ_DEV0);
35 else if (pending & PCI_INT_DEV1)
36 do_IRQ(AR71XX_PCI_IRQ_DEV1);
38 else if (pending & PCI_INT_DEV2)
39 do_IRQ(AR71XX_PCI_IRQ_DEV2);
41 else if (pending & PCI_INT_CORE)
42 do_IRQ(AR71XX_PCI_IRQ_CORE);
48 static void ar71xx_pci_irq_unmask(unsigned int irq)
50 irq -= AR71XX_PCI_IRQ_BASE;
51 ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE,
52 ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE) | (1 << irq));
55 static void ar71xx_pci_irq_mask(unsigned int irq)
57 irq -= AR71XX_PCI_IRQ_BASE;
58 ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE,
59 ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE) & ~(1 << irq));
62 static struct irq_chip ar71xx_pci_irq_chip = {
63 .name = "AR71XX PCI ",
64 .mask = ar71xx_pci_irq_mask,
65 .unmask = ar71xx_pci_irq_unmask,
66 .mask_ack = ar71xx_pci_irq_mask,
69 static struct irqaction ar71xx_pci_irqaction = {
71 .name = "cascade [AR71XX PCI]",
74 static void __init ar71xx_pci_irq_init(void)
78 ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE, 0);
79 ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_STATUS, 0);
81 for (i = AR71XX_PCI_IRQ_BASE;
82 i < AR71XX_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) {
83 irq_desc[i].status = IRQ_DISABLED;
84 set_irq_chip_and_handler(i, &ar71xx_pci_irq_chip,
88 setup_irq(AR71XX_CPU_IRQ_PCI, &ar71xx_pci_irqaction);
90 #endif /* CONFIG_PCI */
92 static void ar71xx_gpio_irq_dispatch(void)
96 pending = ar71xx_gpio_rr(GPIO_REG_INT_PENDING)
97 & ar71xx_gpio_rr(GPIO_REG_INT_ENABLE);
100 do_IRQ(AR71XX_GPIO_IRQ_BASE + fls(pending) - 1);
102 spurious_interrupt();
105 static void ar71xx_gpio_irq_unmask(unsigned int irq)
107 irq -= AR71XX_GPIO_IRQ_BASE;
108 ar71xx_gpio_wr(GPIO_REG_INT_ENABLE,
109 ar71xx_gpio_rr(GPIO_REG_INT_ENABLE) | (1 << irq));
112 static void ar71xx_gpio_irq_mask(unsigned int irq)
114 irq -= AR71XX_GPIO_IRQ_BASE;
115 ar71xx_gpio_wr(GPIO_REG_INT_ENABLE,
116 ar71xx_gpio_rr(GPIO_REG_INT_ENABLE) & ~(1 << irq));
120 static int ar71xx_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
122 /* TODO: implement */
126 #define ar71xx_gpio_irq_set_type NULL
129 struct irq_chip ar71xx_gpio_irq_chip = {
130 .name = "AR71XX GPIO",
131 .unmask = ar71xx_gpio_irq_unmask,
132 .mask = ar71xx_gpio_irq_mask,
133 .mask_ack = ar71xx_gpio_irq_mask,
134 .set_type = ar71xx_gpio_irq_set_type,
137 static struct irqaction ar71xx_gpio_irqaction = {
138 .handler = no_action,
139 .name = "cascade [AR71XX GPIO]",
142 #define GPIO_IRQ_INIT_STATUS (IRQ_LEVEL | IRQ_TYPE_LEVEL_HIGH | IRQ_DISABLED)
143 #define GPIO_INT_ALL 0xffff
145 static void __init ar71xx_gpio_irq_init(void)
149 ar71xx_gpio_wr(GPIO_REG_INT_ENABLE, 0);
150 ar71xx_gpio_wr(GPIO_REG_INT_PENDING, 0);
152 /* setup type of all GPIO interrupts to level sensitive */
153 ar71xx_gpio_wr(GPIO_REG_INT_TYPE, GPIO_INT_ALL);
155 /* setup polarity of all GPIO interrupts to active high */
156 ar71xx_gpio_wr(GPIO_REG_INT_POLARITY, GPIO_INT_ALL);
158 for (i = AR71XX_GPIO_IRQ_BASE;
159 i < AR71XX_GPIO_IRQ_BASE + AR71XX_GPIO_IRQ_COUNT; i++) {
160 irq_desc[i].status = GPIO_IRQ_INIT_STATUS;
161 set_irq_chip_and_handler(i, &ar71xx_gpio_irq_chip,
165 setup_irq(AR71XX_MISC_IRQ_GPIO, &ar71xx_gpio_irqaction);
168 static void ar71xx_misc_irq_dispatch(void)
172 pending = ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS)
173 & ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
175 if (pending & MISC_INT_UART)
176 do_IRQ(AR71XX_MISC_IRQ_UART);
178 else if (pending & MISC_INT_DMA)
179 do_IRQ(AR71XX_MISC_IRQ_DMA);
181 else if (pending & MISC_INT_PERFC)
182 do_IRQ(AR71XX_MISC_IRQ_PERFC);
184 else if (pending & MISC_INT_TIMER)
185 do_IRQ(AR71XX_MISC_IRQ_TIMER);
187 else if (pending & MISC_INT_OHCI)
188 do_IRQ(AR71XX_MISC_IRQ_OHCI);
190 else if (pending & MISC_INT_ERROR)
191 do_IRQ(AR71XX_MISC_IRQ_ERROR);
193 else if (pending & MISC_INT_GPIO)
194 ar71xx_gpio_irq_dispatch();
196 else if (pending & MISC_INT_WDOG)
197 do_IRQ(AR71XX_MISC_IRQ_WDOG);
200 spurious_interrupt();
203 static void ar71xx_misc_irq_unmask(unsigned int irq)
205 irq -= AR71XX_MISC_IRQ_BASE;
206 ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE,
207 ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE) | (1 << irq));
210 static void ar71xx_misc_irq_mask(unsigned int irq)
212 irq -= AR71XX_MISC_IRQ_BASE;
213 ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE,
214 ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE) & ~(1 << irq));
217 struct irq_chip ar71xx_misc_irq_chip = {
218 .name = "AR71XX MISC",
219 .unmask = ar71xx_misc_irq_unmask,
220 .mask = ar71xx_misc_irq_mask,
221 .mask_ack = ar71xx_misc_irq_mask,
224 static struct irqaction ar71xx_misc_irqaction = {
225 .handler = no_action,
226 .name = "cascade [AR71XX MISC]",
229 static void __init ar71xx_misc_irq_init(void)
233 ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, 0);
234 ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_STATUS, 0);
236 for (i = AR71XX_MISC_IRQ_BASE;
237 i < AR71XX_MISC_IRQ_BASE + AR71XX_MISC_IRQ_COUNT; i++) {
238 irq_desc[i].status = IRQ_DISABLED;
239 set_irq_chip_and_handler(i, &ar71xx_misc_irq_chip,
243 setup_irq(AR71XX_CPU_IRQ_MISC, &ar71xx_misc_irqaction);
246 static void ar913x_wmac_irq_dispatch(void)
248 do_IRQ(AR71XX_CPU_IRQ_WMAC);
251 static void (* ar71xx_ip2_irq_handler)(void) = spurious_interrupt;
253 asmlinkage void plat_irq_dispatch(void)
255 unsigned long pending;
257 pending = read_c0_status() & read_c0_cause() & ST0_IM;
259 if (pending & STATUSF_IP7)
260 do_IRQ(AR71XX_CPU_IRQ_TIMER);
262 else if (pending & STATUSF_IP2)
263 ar71xx_ip2_irq_handler();
265 else if (pending & STATUSF_IP4)
266 do_IRQ(AR71XX_CPU_IRQ_GE0);
268 else if (pending & STATUSF_IP5)
269 do_IRQ(AR71XX_CPU_IRQ_GE1);
271 else if (pending & STATUSF_IP3)
272 do_IRQ(AR71XX_CPU_IRQ_USB);
274 else if (pending & STATUSF_IP6)
275 ar71xx_misc_irq_dispatch();
278 spurious_interrupt();
281 void __init arch_init_irq(void)
285 ar71xx_misc_irq_init();
287 switch (ar71xx_soc) {
288 case AR71XX_SOC_AR7130:
289 case AR71XX_SOC_AR7141:
290 case AR71XX_SOC_AR7161:
292 ar71xx_pci_irq_init();
293 ar71xx_ip2_irq_handler = ar71xx_pci_irq_dispatch;
296 case AR71XX_SOC_AR9130:
297 case AR71XX_SOC_AR9132:
298 ar71xx_ip2_irq_handler = ar913x_wmac_irq_dispatch;
304 ar71xx_gpio_irq_init();