2 * Atheros AR71xx SoC specific interrupt handling
4 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 * Parts of this file are based on Atheros' 2.6.15 BSP
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
17 #include <linux/irq.h>
19 #include <asm/irq_cpu.h>
20 #include <asm/mipsregs.h>
22 #include <asm/mach-ar71xx/ar71xx.h>
25 static void ar71xx_pci_irq_dispatch(void)
29 pending = ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_STATUS) &
30 ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE);
32 if (pending & PCI_INT_DEV0)
33 do_IRQ(AR71XX_PCI_IRQ_DEV0);
35 else if (pending & PCI_INT_DEV1)
36 do_IRQ(AR71XX_PCI_IRQ_DEV1);
38 else if (pending & PCI_INT_DEV2)
39 do_IRQ(AR71XX_PCI_IRQ_DEV2);
41 else if (pending & PCI_INT_CORE)
42 do_IRQ(AR71XX_PCI_IRQ_CORE);
48 static void ar71xx_pci_irq_unmask(unsigned int irq)
50 irq -= AR71XX_PCI_IRQ_BASE;
51 ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE,
52 ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE) | (1 << irq));
55 ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE);
58 static void ar71xx_pci_irq_mask(unsigned int irq)
60 irq -= AR71XX_PCI_IRQ_BASE;
61 ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE,
62 ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE) & ~(1 << irq));
65 ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE);
68 static struct irq_chip ar71xx_pci_irq_chip = {
69 .name = "AR71XX PCI ",
70 .mask = ar71xx_pci_irq_mask,
71 .unmask = ar71xx_pci_irq_unmask,
72 .mask_ack = ar71xx_pci_irq_mask,
75 static struct irqaction ar71xx_pci_irqaction = {
77 .name = "cascade [AR71XX PCI]",
80 static void __init ar71xx_pci_irq_init(void)
84 ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE, 0);
85 ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_STATUS, 0);
87 for (i = AR71XX_PCI_IRQ_BASE;
88 i < AR71XX_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) {
89 irq_desc[i].status = IRQ_DISABLED;
90 set_irq_chip_and_handler(i, &ar71xx_pci_irq_chip,
94 setup_irq(AR71XX_CPU_IRQ_PCI, &ar71xx_pci_irqaction);
96 #endif /* CONFIG_PCI */
98 static void ar71xx_gpio_irq_dispatch(void)
102 pending = ar71xx_gpio_rr(GPIO_REG_INT_PENDING)
103 & ar71xx_gpio_rr(GPIO_REG_INT_ENABLE);
106 do_IRQ(AR71XX_GPIO_IRQ_BASE + fls(pending) - 1);
108 spurious_interrupt();
111 static void ar71xx_gpio_irq_unmask(unsigned int irq)
113 irq -= AR71XX_GPIO_IRQ_BASE;
114 ar71xx_gpio_wr(GPIO_REG_INT_ENABLE,
115 ar71xx_gpio_rr(GPIO_REG_INT_ENABLE) | (1 << irq));
118 ar71xx_gpio_rr(GPIO_REG_INT_ENABLE);
121 static void ar71xx_gpio_irq_mask(unsigned int irq)
123 irq -= AR71XX_GPIO_IRQ_BASE;
124 ar71xx_gpio_wr(GPIO_REG_INT_ENABLE,
125 ar71xx_gpio_rr(GPIO_REG_INT_ENABLE) & ~(1 << irq));
128 ar71xx_gpio_rr(GPIO_REG_INT_ENABLE);
132 static int ar71xx_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
134 /* TODO: implement */
138 #define ar71xx_gpio_irq_set_type NULL
141 struct irq_chip ar71xx_gpio_irq_chip = {
142 .name = "AR71XX GPIO",
143 .unmask = ar71xx_gpio_irq_unmask,
144 .mask = ar71xx_gpio_irq_mask,
145 .mask_ack = ar71xx_gpio_irq_mask,
146 .set_type = ar71xx_gpio_irq_set_type,
149 static struct irqaction ar71xx_gpio_irqaction = {
150 .handler = no_action,
151 .name = "cascade [AR71XX GPIO]",
154 #define GPIO_IRQ_INIT_STATUS (IRQ_LEVEL | IRQ_TYPE_LEVEL_HIGH | IRQ_DISABLED)
155 #define GPIO_INT_ALL 0xffff
157 static void __init ar71xx_gpio_irq_init(void)
161 ar71xx_gpio_wr(GPIO_REG_INT_ENABLE, 0);
162 ar71xx_gpio_wr(GPIO_REG_INT_PENDING, 0);
164 /* setup type of all GPIO interrupts to level sensitive */
165 ar71xx_gpio_wr(GPIO_REG_INT_TYPE, GPIO_INT_ALL);
167 /* setup polarity of all GPIO interrupts to active high */
168 ar71xx_gpio_wr(GPIO_REG_INT_POLARITY, GPIO_INT_ALL);
170 for (i = AR71XX_GPIO_IRQ_BASE;
171 i < AR71XX_GPIO_IRQ_BASE + AR71XX_GPIO_IRQ_COUNT; i++) {
172 irq_desc[i].status = GPIO_IRQ_INIT_STATUS;
173 set_irq_chip_and_handler(i, &ar71xx_gpio_irq_chip,
177 setup_irq(AR71XX_MISC_IRQ_GPIO, &ar71xx_gpio_irqaction);
180 static void ar71xx_misc_irq_dispatch(void)
184 pending = ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS)
185 & ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
187 if (pending & MISC_INT_UART)
188 do_IRQ(AR71XX_MISC_IRQ_UART);
190 else if (pending & MISC_INT_DMA)
191 do_IRQ(AR71XX_MISC_IRQ_DMA);
193 else if (pending & MISC_INT_PERFC)
194 do_IRQ(AR71XX_MISC_IRQ_PERFC);
196 else if (pending & MISC_INT_TIMER)
197 do_IRQ(AR71XX_MISC_IRQ_TIMER);
199 else if (pending & MISC_INT_OHCI)
200 do_IRQ(AR71XX_MISC_IRQ_OHCI);
202 else if (pending & MISC_INT_ERROR)
203 do_IRQ(AR71XX_MISC_IRQ_ERROR);
205 else if (pending & MISC_INT_GPIO)
206 ar71xx_gpio_irq_dispatch();
208 else if (pending & MISC_INT_WDOG)
209 do_IRQ(AR71XX_MISC_IRQ_WDOG);
212 spurious_interrupt();
215 static void ar71xx_misc_irq_unmask(unsigned int irq)
217 irq -= AR71XX_MISC_IRQ_BASE;
218 ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE,
219 ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE) | (1 << irq));
222 ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
225 static void ar71xx_misc_irq_mask(unsigned int irq)
227 irq -= AR71XX_MISC_IRQ_BASE;
228 ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE,
229 ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE) & ~(1 << irq));
232 ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
235 struct irq_chip ar71xx_misc_irq_chip = {
236 .name = "AR71XX MISC",
237 .unmask = ar71xx_misc_irq_unmask,
238 .mask = ar71xx_misc_irq_mask,
239 .mask_ack = ar71xx_misc_irq_mask,
242 static struct irqaction ar71xx_misc_irqaction = {
243 .handler = no_action,
244 .name = "cascade [AR71XX MISC]",
247 static void __init ar71xx_misc_irq_init(void)
251 ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, 0);
252 ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_STATUS, 0);
254 for (i = AR71XX_MISC_IRQ_BASE;
255 i < AR71XX_MISC_IRQ_BASE + AR71XX_MISC_IRQ_COUNT; i++) {
256 irq_desc[i].status = IRQ_DISABLED;
257 set_irq_chip_and_handler(i, &ar71xx_misc_irq_chip,
261 setup_irq(AR71XX_CPU_IRQ_MISC, &ar71xx_misc_irqaction);
264 static void ar913x_wmac_irq_dispatch(void)
266 do_IRQ(AR71XX_CPU_IRQ_WMAC);
269 static void (* ar71xx_ip2_irq_handler)(void) = spurious_interrupt;
271 asmlinkage void plat_irq_dispatch(void)
273 unsigned long pending;
275 pending = read_c0_status() & read_c0_cause() & ST0_IM;
277 if (pending & STATUSF_IP7)
278 do_IRQ(AR71XX_CPU_IRQ_TIMER);
280 else if (pending & STATUSF_IP2)
281 ar71xx_ip2_irq_handler();
283 else if (pending & STATUSF_IP4)
284 do_IRQ(AR71XX_CPU_IRQ_GE0);
286 else if (pending & STATUSF_IP5)
287 do_IRQ(AR71XX_CPU_IRQ_GE1);
289 else if (pending & STATUSF_IP3)
290 do_IRQ(AR71XX_CPU_IRQ_USB);
292 else if (pending & STATUSF_IP6)
293 ar71xx_misc_irq_dispatch();
296 spurious_interrupt();
299 void __init arch_init_irq(void)
303 ar71xx_misc_irq_init();
305 switch (ar71xx_soc) {
306 case AR71XX_SOC_AR7130:
307 case AR71XX_SOC_AR7141:
308 case AR71XX_SOC_AR7161:
310 ar71xx_pci_irq_init();
311 ar71xx_ip2_irq_handler = ar71xx_pci_irq_dispatch;
314 case AR71XX_SOC_AR9130:
315 case AR71XX_SOC_AR9132:
316 ar71xx_ip2_irq_handler = ar913x_wmac_irq_dispatch;
322 ar71xx_gpio_irq_init();